DE3688042T2 - Verfahren zur herstellung einer submikron-grabenstruktur auf einem halbleitenden substrat. - Google Patents

Verfahren zur herstellung einer submikron-grabenstruktur auf einem halbleitenden substrat.

Info

Publication number
DE3688042T2
DE3688042T2 DE8686114062T DE3688042T DE3688042T2 DE 3688042 T2 DE3688042 T2 DE 3688042T2 DE 8686114062 T DE8686114062 T DE 8686114062T DE 3688042 T DE3688042 T DE 3688042T DE 3688042 T2 DE3688042 T2 DE 3688042T2
Authority
DE
Germany
Prior art keywords
producing
trench structure
semiconductive substrate
submicron
submicron trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686114062T
Other languages
English (en)
Other versions
DE3688042D1 (de
Inventor
Seiki Ogura
Jacob Riseman
Nivo Rovedo
Ronald N Schulz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3688042D1 publication Critical patent/DE3688042D1/de
Publication of DE3688042T2 publication Critical patent/DE3688042T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off
DE8686114062T 1985-10-30 1986-10-10 Verfahren zur herstellung einer submikron-grabenstruktur auf einem halbleitenden substrat. Expired - Fee Related DE3688042T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/792,931 US4648937A (en) 1985-10-30 1985-10-30 Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer

Publications (2)

Publication Number Publication Date
DE3688042D1 DE3688042D1 (de) 1993-04-22
DE3688042T2 true DE3688042T2 (de) 1993-09-16

Family

ID=25158523

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686114062T Expired - Fee Related DE3688042T2 (de) 1985-10-30 1986-10-10 Verfahren zur herstellung einer submikron-grabenstruktur auf einem halbleitenden substrat.

Country Status (4)

Country Link
US (1) US4648937A (de)
EP (1) EP0223994B1 (de)
JP (1) JPS62105426A (de)
DE (1) DE3688042T2 (de)

Families Citing this family (107)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4743565A (en) * 1981-03-30 1988-05-10 International Business Machines Corporation Lateral device structures using self-aligned fabrication techniques
DE3602461A1 (de) * 1986-01-28 1987-07-30 Telefunken Electronic Gmbh Verfahren zum herstellen eines sperrschicht-feldeffekttransistors
US4689869A (en) * 1986-04-07 1987-09-01 International Business Machines Corporation Fabrication of insulated gate gallium arsenide FET with self-aligned source/drain and submicron channel length
US4735681A (en) * 1986-08-15 1988-04-05 Motorola Inc. Fabrication method for sub-micron trench
FR2607600A1 (fr) * 1986-11-28 1988-06-03 Commissariat Energie Atomique Procede de realisation sur un substrat d'elements espaces les uns des autres
GB2198393B (en) * 1986-12-13 1990-06-06 Spectrol Reliance Ltd Method of producing filaments
US4776922A (en) * 1987-10-30 1988-10-11 International Business Machines Corporation Formation of variable-width sidewall structures
US4838991A (en) * 1987-10-30 1989-06-13 International Business Machines Corporation Process for defining organic sidewall structures
US4851368A (en) * 1987-12-04 1989-07-25 Cornell Research Foundation, Inc. Method of making travelling wave semi-conductor laser
JPH01248524A (ja) * 1988-03-30 1989-10-04 Hitachi Ltd 半導体装置とその製造方法
US4992939A (en) * 1988-08-05 1991-02-12 Tyler Brian G Method of producing narrative analytical report
DE3888184D1 (de) * 1988-11-17 1994-04-07 Ibm Verfahren zur Herstellung von Masken mit Strukturen im Submikrometerbereich.
US5223914A (en) * 1989-04-28 1993-06-29 International Business Machines Corporation Follow-up system for etch process monitoring
EP0394597A1 (de) * 1989-04-28 1990-10-31 International Business Machines Corporation System zum Verfolgen eines Ätzprozesses in einer RIE-Vorrichtung und dessen Verwendung zur Herstellung reproduzierbarer Strukturen hoher Auflösung
US5010039A (en) * 1989-05-15 1991-04-23 Ku San Mei Method of forming contacts to a semiconductor device
EP0416141A1 (de) * 1989-09-04 1991-03-13 Siemens Aktiengesellschaft Verfahren zur Herstellung eines FET mit asymmetrisch angeordnetem Gate-Bereich
FR2669466B1 (fr) * 1990-11-16 1997-11-07 Michel Haond Procede de gravure de couches de circuit integre a profondeur fixee et circuit integre correspondant.
US5236853A (en) * 1992-02-21 1993-08-17 United Microelectronics Corporation Self-aligned double density polysilicon lines for ROM and EPROM
JP3022689B2 (ja) * 1992-08-31 2000-03-21 日本電気株式会社 バイポーラトランジスタの製造方法
JP3317582B2 (ja) * 1994-06-01 2002-08-26 菱電セミコンダクタシステムエンジニアリング株式会社 微細パターンの形成方法
US5480823A (en) * 1995-01-19 1996-01-02 United Microelectronics Corporation Method of making high density ROM, without using a code implant
US5460991A (en) * 1995-03-16 1995-10-24 United Microelectronics Corporation Method of making high coupling ratio flash EEPROM device
US5795830A (en) * 1995-06-06 1998-08-18 International Business Machines Corporation Reducing pitch with continuously adjustable line and space dimensions
DE19526011C1 (de) * 1995-07-17 1996-11-28 Siemens Ag Verfahren zur Herstellung von sublithographischen Ätzmasken
DE19536523A1 (de) * 1995-09-29 1997-04-03 Siemens Ag Verfahren zur Herstellung einer Gateelektrode
JPH09181163A (ja) * 1995-11-13 1997-07-11 Texas Instr Inc <Ti> 丸い角を備えたトレンチ分離構造体を有する半導体装置の製造法
US5667632A (en) * 1995-11-13 1997-09-16 Motorola, Inc. Method of defining a line width
US5599738A (en) * 1995-12-11 1997-02-04 Motorola Methods of fabrication of submicron features in semiconductor devices
US5946566A (en) * 1996-03-01 1999-08-31 Ace Memory, Inc. Method of making a smaller geometry high capacity stacked DRAM device
US5851882A (en) 1996-05-06 1998-12-22 Micron Technology, Inc. ZPROM manufacture and design and methods for forming thin structures using spacers as an etching mask
US5952720A (en) * 1996-05-06 1999-09-14 United Microelectronics Corp. Buried contact structure
US5891805A (en) * 1996-12-13 1999-04-06 Intel Corporation Method of forming contacts
US5744391A (en) * 1997-01-15 1998-04-28 Taiwan Semiconductor Manufacturing Company Ltd. Method to improve isolation between EEPROM devices via a field oxide anneal
EP0996982B1 (de) 1997-07-18 2008-10-29 Infineon Technologies AG Verfahren zur herstellung eines vertikalen mos-transistors
JPH11154701A (ja) * 1997-11-21 1999-06-08 Mitsubishi Electric Corp 半導体装置
US6087263A (en) * 1998-01-29 2000-07-11 Micron Technology, Inc. Methods of forming integrated circuitry and integrated circuitry structures
US6191446B1 (en) 1998-03-04 2001-02-20 Advanced Micro Devices, Inc. Formation and control of a vertically oriented transistor channel length
US6210866B1 (en) * 1998-05-04 2001-04-03 International Business Machines Corporation Method for forming features using self-trimming by selective etch and device formed thereby
US6387771B1 (en) * 1999-06-08 2002-05-14 Infineon Technologies Ag Low temperature oxidation of conductive layers for semiconductor fabrication
US6277704B1 (en) 2000-05-24 2001-08-21 Micron Technology, Inc. Microelectronic device fabricating method, method of forming a pair of conductive device components of different base widths from a common deposited conductive layer
US6862798B2 (en) 2002-01-18 2005-03-08 Hitachi Global Storage Technologies Netherlands B.V. Method of making a narrow pole tip by ion beam deposition
US6610604B1 (en) 2002-02-05 2003-08-26 Chartered Semiconductor Manufacturing Ltd. Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask
KR100476924B1 (ko) * 2002-06-14 2005-03-17 삼성전자주식회사 반도체 장치의 미세 패턴 형성 방법
US6806584B2 (en) 2002-10-21 2004-10-19 International Business Machines Corporation Semiconductor device structure including multiple fets having different spacer widths
US7279746B2 (en) * 2003-06-30 2007-10-09 International Business Machines Corporation High performance CMOS device structures and method of manufacture
JP2005116969A (ja) 2003-10-10 2005-04-28 Toshiba Corp 半導体装置及びその製造方法
US7098105B2 (en) * 2004-05-26 2006-08-29 Micron Technology, Inc. Methods for forming semiconductor structures
US7151040B2 (en) * 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
US7442976B2 (en) * 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
US7910288B2 (en) 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
US7655387B2 (en) 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
US7115525B2 (en) * 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
US7259023B2 (en) * 2004-09-10 2007-08-21 Intel Corporation Forming phase change memory arrays
US7170128B2 (en) * 2004-12-02 2007-01-30 Atmel Corporation Multi-bit nanocrystal memory
KR100641980B1 (ko) * 2004-12-17 2006-11-02 동부일렉트로닉스 주식회사 반도체 소자의 배선 및 그 형성방법
WO2006070474A1 (ja) * 2004-12-28 2006-07-06 Spansion Llc 半導体装置の製造方法
US7253118B2 (en) * 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US7390746B2 (en) 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US7611944B2 (en) 2005-03-28 2009-11-03 Micron Technology, Inc. Integrated circuit fabrication
US7120046B1 (en) 2005-05-13 2006-10-10 Micron Technology, Inc. Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
US7371627B1 (en) * 2005-05-13 2008-05-13 Micron Technology, Inc. Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7560390B2 (en) 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
US7396781B2 (en) * 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
US7541632B2 (en) * 2005-06-14 2009-06-02 Micron Technology, Inc. Relaxed-pitch method of aligning active area to digit line
US7902598B2 (en) * 2005-06-24 2011-03-08 Micron Technology, Inc. Two-sided surround access transistor for a 4.5F2 DRAM cell
US7888721B2 (en) * 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) * 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7413981B2 (en) * 2005-07-29 2008-08-19 Micron Technology, Inc. Pitch doubled circuit layout
US8123968B2 (en) * 2005-08-25 2012-02-28 Round Rock Research, Llc Multiple deposition for integration of spacers in pitch multiplication process
US7816262B2 (en) 2005-08-30 2010-10-19 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
US7829262B2 (en) 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7776744B2 (en) * 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US7416943B2 (en) * 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
US7393789B2 (en) * 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7687342B2 (en) * 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7572572B2 (en) 2005-09-01 2009-08-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7759197B2 (en) * 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
US7557032B2 (en) * 2005-09-01 2009-07-07 Micron Technology, Inc. Silicided recessed silicon
US7538858B2 (en) * 2006-01-11 2009-05-26 Micron Technology, Inc. Photolithographic systems and methods for producing sub-diffraction-limited features
US7531367B2 (en) * 2006-01-18 2009-05-12 International Business Machines Corporation Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit
US7842558B2 (en) * 2006-03-02 2010-11-30 Micron Technology, Inc. Masking process for simultaneously patterning separate regions
US7476933B2 (en) * 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
US7902074B2 (en) 2006-04-07 2011-03-08 Micron Technology, Inc. Simplified pitch doubling process flow
US8003310B2 (en) * 2006-04-24 2011-08-23 Micron Technology, Inc. Masking techniques and templates for dense semiconductor fabrication
US7488685B2 (en) * 2006-04-25 2009-02-10 Micron Technology, Inc. Process for improving critical dimension uniformity of integrated circuit arrays
US7795149B2 (en) * 2006-06-01 2010-09-14 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US7723009B2 (en) 2006-06-02 2010-05-25 Micron Technology, Inc. Topography based patterning
US7611980B2 (en) 2006-08-30 2009-11-03 Micron Technology, Inc. Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US7517804B2 (en) * 2006-08-31 2009-04-14 Micron Technologies, Inc. Selective etch chemistries for forming high aspect ratio features and associated structures
US7666578B2 (en) 2006-09-14 2010-02-23 Micron Technology, Inc. Efficient pitch multiplication process
US8129289B2 (en) * 2006-10-05 2012-03-06 Micron Technology, Inc. Method to deposit conformal low temperature SiO2
US7923373B2 (en) * 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8563229B2 (en) * 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US7737039B2 (en) 2007-11-01 2010-06-15 Micron Technology, Inc. Spacer process for on pitch contacts and related structures
US7659208B2 (en) 2007-12-06 2010-02-09 Micron Technology, Inc Method for forming high density patterns
US7790531B2 (en) 2007-12-18 2010-09-07 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US8030218B2 (en) 2008-03-21 2011-10-04 Micron Technology, Inc. Method for selectively modifying spacing between pitch multiplied structures
US8076208B2 (en) 2008-07-03 2011-12-13 Micron Technology, Inc. Method for forming transistor with high breakdown voltage using pitch multiplication technique
US8101497B2 (en) 2008-09-11 2012-01-24 Micron Technology, Inc. Self-aligned trench formation
US8492282B2 (en) * 2008-11-24 2013-07-23 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits
US8557675B2 (en) 2011-11-28 2013-10-15 Globalfoundries Inc. Methods of patterning features in a structure using multiple sidewall image transfer technique
US8669186B2 (en) 2012-01-26 2014-03-11 Globalfoundries Inc. Methods of forming SRAM devices using sidewall image transfer techniques
US9583381B2 (en) * 2013-06-14 2017-02-28 Micron Technology, Inc. Methods for forming semiconductor devices and semiconductor device structures
TWI640042B (zh) 2015-03-09 2018-11-01 聯華電子股份有限公司 半導體裝置之圖案化結構的製作方法
CN117724207A (zh) * 2024-02-18 2024-03-19 上海铭锟半导体有限公司 一种非晶硅光波导的制作方法及非晶硅光波导

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4093503A (en) * 1977-03-07 1978-06-06 International Business Machines Corporation Method for fabricating ultra-narrow metallic lines
US4209349A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching
JPS5691430A (en) * 1979-12-25 1981-07-24 Fujitsu Ltd Preparation of semiconductor device
DE3016736A1 (de) * 1980-04-30 1981-11-05 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen geaetzter strukturen in siliziumoxidschichten
US4358340A (en) * 1980-07-14 1982-11-09 Texas Instruments Incorporated Submicron patterning without using submicron lithographic technique
US4354896A (en) * 1980-08-05 1982-10-19 Texas Instruments Incorporated Formation of submicron substrate element
JPS57130431A (en) * 1981-02-06 1982-08-12 Fujitsu Ltd Manufacture of semiconductor device
US4432132A (en) * 1981-12-07 1984-02-21 Bell Telephone Laboratories, Incorporated Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features
NL8105559A (nl) * 1981-12-10 1983-07-01 Philips Nv Werkwijze voor het aanbrengen van een smalle groef in een substraatgebied, in het bijzonder een halfgeleidersubstraatgebied.
US4385975A (en) * 1981-12-30 1983-05-31 International Business Machines Corp. Method of forming wide, deep dielectric filled isolation trenches in the surface of a silicon semiconductor substrate

Also Published As

Publication number Publication date
EP0223994B1 (de) 1993-03-17
US4648937A (en) 1987-03-10
JPS62105426A (ja) 1987-05-15
DE3688042D1 (de) 1993-04-22
EP0223994A3 (en) 1989-10-25
EP0223994A2 (de) 1987-06-03
JPH0529133B2 (de) 1993-04-28

Similar Documents

Publication Publication Date Title
DE3688042T2 (de) Verfahren zur herstellung einer submikron-grabenstruktur auf einem halbleitenden substrat.
DE3686315D1 (de) Verfahren zur herstellung einer halbleiterstruktur.
DE3583183D1 (de) Verfahren zur herstellung eines halbleitersubstrates.
DE3766940D1 (de) Verfahren zur herstellung einer planaren polymerischen bedeckung auf einem substrat.
DE3875992D1 (de) Verfahren zur herstellung einer epitaxieschicht eines iii-v-verbindungshalbleiters.
DE3788678D1 (de) Vorrichtung und Verfahren zur Herstellung einer Schicht auf einem Substrat.
DE3685709T2 (de) Substratstruktur zur herstellung einer halbleiterverbundanordnung.
DE3775459D1 (de) Verfahren zur herstellung einer diamantenschicht.
DE68907507D1 (de) Verfahren zur herstellung einer halbleitervorrichtung.
DE3868178D1 (de) Verfahren zur herstellung einer leitenden struktur auf einem substrat.
DE3672570D1 (de) Verfahren zur herstellung einer planaren halbleiteranordnung mit graeben.
DE3381126D1 (de) Verfahren zur herstellung einer monokristallinen halbleiterschicht.
DE3582143D1 (de) Verfahren zur herstellung einer halbleitervorrichtung.
DE3777015D1 (de) Verfahren zur herstellung einer verschleissbestaendigen schicht.
DE3678360D1 (de) Verfahren zur herstellung einer graphiteinlagerungsverbindung.
DE3779802T2 (de) Verfahren zur herstellung einer halbleiteranordnung.
DE59202154D1 (de) Verfahren zur herstellung einer leuchtstoffschicht auf einem substrat.
DE3669806D1 (de) Verfahren zur herstellung einer raeumlich periodischen halbleiter-schichtenfolge.
DE3785595T2 (de) Verfahren zur herstellung einer verschleissfesten schicht.
DE68908325D1 (de) Verfahren zur herstellung einer indiumphosphid-epitaxialschicht auf einer substratoberflaeche.
DE3580350D1 (de) Verfahren zur herstellung einer frukto-oligosaccharose.
DE3882882D1 (de) Verfahren zur herstellung einer siliziumstruktur auf einem isolator.
DE3578263D1 (de) Verfahren zur herstellung einer halbleiteranordnung.
DE3886863D1 (de) Verfahren zur Herstellung einer supraleitenden Oxydschicht auf einem Substrat.
DE3786364D1 (de) Verfahren zur herstellung einer niedergeschlagenen schicht.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee