DE3743732C2 - Method for synchronizing a code word with a received spectrally spread signal - Google Patents

Description

The invention relates to a method according to the preamble of claim 1 and circuits for performing this procedure. One such method is for example known from NTZ 28 (1975) H. 3, pp. 79 to 88.

When transmitting messages after Code multiplexing is already done with the message modulated carrier with a code word, its clock frequency is large compared to the bandwidth of the message signal, modulated, causing a spectral spread of the itself narrowband signal modulated with the message he follows. To retrieve the message at the receiving end becomes the spectral spread of the desired signal undone, which is why a phase-synchronized Codeword is required. In the known methods this code word when searching for the received signal out of phase until a  Match the one contained in the received signal Code word and the code word generated in the receiver is present. Then the search process is ended and a Tracking control loop for maintaining the Synchronization during message transmission activated.

The duration of the search is a quadratic function the length of the code word. On the one hand, according to the Length of the code word many phase assignments between the generated code word and that in the received signal contained code word possible. On the other hand, it lasts Check for correlation between the generated one Code word and the code word in the received signal the longer the more bits a code word has. So is for example, the time it takes to search for a 1023 bit long code word and with a bit period of 0.5 µs 523 ms.

In the method known from the aforementioned publication NTZ 28 (1975) H. 3, pp. 79-88, in particular from FIG. 5, the frequency of the oscillator for code generation is adjusted for the search process and the search process only ends when the single phase position of the code word used for the search process matches the code word contained in the received signal. In a capture circuit, only one mixer is provided for a phase position of the code word.

The object of the present invention is the search process when the code word is synchronized with the received one Significantly shorten the signal.  

The inventive method with the characteristic Features of the main claim has the advantage that the Search process significantly compared to the known methods can be shortened.

By the measures listed in the subclaims advantageous developments and improvements in Main claim specified invention and advantageous Circuit arrangements for performing the invention Procedure possible.

Embodiments of the invention are in the drawing represented with several figures and in the following Description explained in more detail. It shows:

Fig. 1 is a block diagram of a known circuit arrangement for the search process,

Figure 2 is a schematic representation of the group consisting of a plurality of successive code words receiver code and the codes contained in the received signal - hereinafter referred to as transmission code.

Fig. 3 is a block diagram of a likewise known circuit for tracking control,

Fig. 4 shows time diagrams of voltage in the circuit arrangement of Figure 3 signals. Occur

Fig. 5 is a block diagram of a circuit arrangement according to the invention,

Fig. 6 are schematic representations of signals. Occur in the circuit of Figure 5 and

FIG. 7 is a table for a logic circuit contained in the circuit arrangement according to FIG. 5.

Identical parts are given the same reference symbols in the figures Mistake. Signals, circuit points at which they occur, and the corresponding timing diagrams are with same letters.

Fig. 1 shows those parts of a receiver for spread spectrum signals, which are required for explaining the seek operation. . The circuit of Figure 1 is at 1, the received signal - optionally after a frequency conversion into an intermediate frequency range - fed to and passed through a mixer 2 for further evaluation. A clock signal supplied at 3 has twice the frequency of the bit clock and is supplied on the one hand to an input of an AND circuit 4 and on the other hand to a logic circuit 5 . The logic circuit can be supplied with a switching signal via an input 6 , which serves to activate the search process. If there is no search operation, the output signal of the logic circuit 5 is a one, so that all clock pulses are forwarded by the AND circuit. If the search process is active, the clock pulses are counted in the logic circuit. After 2n clock pulses, the output voltage of the logic circuit 5 is set to zero for m clock pulses. Here, n is the number of bits of a code word and m is the duration of the pause between two successive code words during the search process in half bit periods.

The output signal of the AND circuit 4 thus consists of pulses with twice the bit frequency, with a pause of m pulses taking place every 2n pulses during the search process. This signal is fed to a code generator 7 , the essential component of which is a shift register which is loaded with the code word and which is clocked with the bit clock. A serial code word is then available at the output of the code generator 7 and is supplied to the mixer 2 . The output signal of the AND circuit 4 is supplied in the code generator 7 to the clock input of the shift register via a frequency divider, with the aid of which the bit clock is obtained by suppressing every second pulse.

In the schematic representation of FIG. 2, the code generated in the receiver (receiver code) is compared with the transmission code. The first code word of the receiver code is out of phase with the corresponding code word in the send code. The second code word of the receiver code is only phase-shifted by half a bit period with respect to the transmit code by inserting a code break of half a bit period, while the third code words match, with which the search process can be ended. The long search time is due, on the one hand, to the fact that the receiver code can only be shifted from codeword to codeword by a small amount, so that a correlation with an accuracy required for the tracking control can be established, and, on the other hand, that for each relative phase position of the receiver code for the transmission code, the entire code word duration must be taken into account when checking for correlation.

For further understanding of the invention, the tracking control which follows the search process is explained below with reference to FIGS. 3 and 4. In the circuit arrangement according to FIG. 3, three mixers are provided, the mixer 2 being used for multiplex demodulation of the received signal supplied at 1 . The mixer 2 is followed by a demodulator 11 , at the output 12 of which the information received is available in the baseband. In practical transmission systems based on the code multiplex method, the demodulator 11 is a PSK demodulator, PSK standing for phase shift keying.

The further mixers 13 , 14 , to which the received signal is also fed, are part of a control loop for tracking the frequency of a controllable oscillator 15 , which is used to clock the code generator 16 . The code generator 16 has three outputs, at which the code is applied out of phase by half a bit period. In this case, the mixer 2 is the code with the average phase position and the mixers 13 and 14 fed to the code with a contrast by a half bit period leading or lagging phase. The control loop is completed by two bandpass filters 17 , 18 connected downstream of the mixers 13 , 14 , each of which is followed by an envelope detector 19 , 20 . The output signals of the envelope detectors 19 and 20 are subtracted in a subtraction circuit 21 and the resulting difference is fed via a low-pass filter 22 to a control input of a controllable oscillator 15 as a control voltage. Such a control loop is referred to in the Anglo-Saxon literature as a delay lock loop.

13, 14 Fig. 4 shows the amplitudes of the output voltages of the mixer 2 in response to the phase difference between the receiver code and the transmit code, wherein the phase difference is measured in bit periods. According to the phase differences of the outputs of the code generator 16 , the output voltage of the mixer 14 has a maximum at -0.5 bits, while the maximum of the output voltage of the mixer 13 is greatest at +0.5 bits. The maximum of the output voltage of the mixer 2 occurs when the phase difference becomes zero.

The function effective for the control is obtained by subtracting the output signals of the mixers 13 and 14 , and tracking between -0.5 and +0.5 bits is possible.

In the circuit arrangement according to FIG. 5, the logic circuit 5 , the AND gate 4 and the code generator 7 are constructed in a similar manner to the circuit arrangement according to FIG. 1. The output signal of the code generator is successively delayed in three delay circuits 31 , 32 , 33 by half a bit period. The delay circuits 31 , 32 , 33 are clocked with the clock signal E. A total of four receiver codes A, B, C, D, each phase-shifted by half a bit period, are available, which are each fed to a mixer 34 , 35 , 36 , 37 , which are also acted upon by the received signal supplied at 38 . The mixers are each followed in a manner known per se by a bandpass filter 39 , 40 , 41 , 42 , each of which is followed by a threshold detector 43 , 44 , 45 , 46 . The output signals G, H, I, K of the threshold value detectors are evaluated in an evaluation logic 47 . The evaluation takes place on the basis of a table stored in the evaluation logic and causes the search process to be stopped or started, the supply of that of signals A, B, C or D, which correlates with the transmission code, to mixer 2 and a selection of those for Tracking control signals to be used.

For the tracking control, the outputs of the bandpass filters 39 to 42 are each connected to an envelope detector 48 , 49 , 50 , 51 . With the aid of a switching device 52 , two of the outputs of the envelope detectors 48 to 51 can be connected to the inputs of a subtraction circuit 21 . The output of the subtraction circuit is - as described in connection with FIG. 3 - connected via a low-pass filter 22 to the control input of a controllable oscillator 15 , from the output of which the clock signal E is switched to the switching point 55 via the changeover switch 54 in the case of regulation.

The function of the circuit arrangement according to FIG. 5 is explained below with reference to FIGS. 6 and 7. The transmission code is shown in line S in FIG. 6, code words with n bits each being transmitted in a continuous sequence. The signals A to D are shifted against each other by half a bit period and in an initially arbitrary phase relationship to the transmit code S. As a result, no correlation is found with any of the mixers 34 to 37 and the subsequent circuits, so that the signals G to K have the value zero have (see table in Fig. 7). The evaluation logic 46 thereby activates the logic circuit 5 for suppressing the clock signal, as is described in connection with FIG. 1. Due to the gaps thus created in the signals A to D, the signals A to D are shifted with respect to the transmission code S. The fact that several receiver codes which are phase-shifted by half a bit period are available means that they can be shifted from code word to code word by more than half a bit period. In the exemplary embodiment shown, the duration of the interruption is two bit periods.

As soon as the phase position of one of the signals A to D approaches the phase position of the transmission code, at least one of the signals G to K jumps to the value one. Only when several of the four signals G to K reach the value one, that is to say when several of the four code words with different phase positions are within the correlation range given by the curves according to FIG. 4, is the search process terminated and the tracking control activated. For this purpose, two of the four output signals of the envelope detectors are connected to inputs of the subtraction circuit 21 according to the table in FIG. 7.

The code Q, which is to be fed to the mixer 2 , is selected by a further switchover device 53 , which is also controlled by the evaluation logic 47 according to the table in accordance with FIG. 7.

As can be seen, the search time is shortened in that instead of an otherwise usual Search correlators search for four correlators at the same time. The  Search time is therefore a little over a quarter shortened. The number of search correlators is not four limited, it is an example.

Claims (6)

1. A method for synchronizing a code word with a received spectrally spread signal, wherein a search process or a tracking control is activated depending on whether there is a synchronization of the code word with the received spectrally spread signal, characterized in that the code word is repeated in several different phase positions are generated and mixed with the different phase positions in each case with the received signal, that there are pauses during the search process between the repeatedly generated code words and that the search process is ended when in at least one of the different phase positions there is a correlation between the code word and the received one Signal is detected. 2. The method according to claim 1, characterized in that the different phases are each half Differentiate bit period from each other. 3. The method according to claim 2, characterized in that generates the code word with four different phase positions and that the pause between successive Repetitions of the code word during the search process two Bit periods is long.   4. The method according to any one of claims 1 to 3, characterized characterized in that after the search, the Mixed products of those code words for one Tracking rules are used, which regarding their Phase position are adjacent to that code word which on End of the search process correlated with the received signal. 5. Circuit arrangement for performing the method according to one of the preceding claims, characterized in that a code generator ( 7 ) is supplied with an interruptible clock signal, which is connected to the output of the code generator ( 7 ) a plurality of series-connected delay circuits ( 31 , 32 , 33 ) are that the output of the code generator ( 7 ) and the outputs of the delay circuits ( 31 , 32 , 33 ) are connected to a first input of each mixing circuit ( 34 , 35 , 36 , 37 ), the second inputs of which are supplied with the received signal that a threshold value detector ( 43 , 44 , 45 , 46 ) is connected to the outputs of the mixing circuits ( 34 to 37 ) via a bandpass filter ( 39 , 40 , 41 , 42 ) and that the outputs of the threshold value detectors ( 43 to 46 ) are connected via a logic circuit ( 47 ) to a circuit ( 5 ) for interrupting the clock pulses. 6. Circuit arrangement according to claim 5, characterized in that the outputs of the bandpass filter are each connected to an envelope detector ( 48 , 49 , 50 , 51 ) and that the outputs of the envelope detectors ( 48 to 51 ) via a switching device ( 52 ) with a Subtraction circuit ( 21 ) are connected such that, depending on the output signals of the logic circuit ( 47 ), the output signals of two envelope detectors ( 48 to 51 ) can be connected to the inputs of the subtraction circuit ( 21 ).