DE3750935T2 - Verfahren und System zum Erleichtern der Befehlsausführung in einem digitalen Rechner. - Google Patents

Verfahren und System zum Erleichtern der Befehlsausführung in einem digitalen Rechner.

Info

Publication number
DE3750935T2
DE3750935T2 DE3750935T DE3750935T DE3750935T2 DE 3750935 T2 DE3750935 T2 DE 3750935T2 DE 3750935 T DE3750935 T DE 3750935T DE 3750935 T DE3750935 T DE 3750935T DE 3750935 T2 DE3750935 T2 DE 3750935T2
Authority
DE
Germany
Prior art keywords
digital computer
command execution
facilitate command
facilitate
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3750935T
Other languages
English (en)
Other versions
DE3750935D1 (de
Inventor
Ruby Bei-Loh Lee
Allen J Baum
Russell Kao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE3750935D1 publication Critical patent/DE3750935D1/de
Publication of DE3750935T2 publication Critical patent/DE3750935T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy
DE3750935T 1986-03-27 1987-01-30 Verfahren und System zum Erleichtern der Befehlsausführung in einem digitalen Rechner. Expired - Lifetime DE3750935T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/845,213 US4722050A (en) 1986-03-27 1986-03-27 Method and apparatus for facilitating instruction processing of a digital computer

Publications (2)

Publication Number Publication Date
DE3750935D1 DE3750935D1 (de) 1995-02-16
DE3750935T2 true DE3750935T2 (de) 1995-08-03

Family

ID=25294662

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3750935T Expired - Lifetime DE3750935T2 (de) 1986-03-27 1987-01-30 Verfahren und System zum Erleichtern der Befehlsausführung in einem digitalen Rechner.

Country Status (5)

Country Link
US (1) US4722050A (de)
EP (1) EP0238810B1 (de)
JP (1) JPS62235658A (de)
CA (1) CA1282181C (de)
DE (1) DE3750935T2 (de)

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US5230068A (en) * 1990-02-26 1993-07-20 Nexgen Microsystems Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
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US5226138A (en) * 1990-11-27 1993-07-06 Sun Microsystems, Inc. Method for selectively transferring data instructions to a cache memory
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US5710912A (en) * 1993-05-06 1998-01-20 Hewlett-Packard Co. Method and apparatus for enabling a computer system to adjust for latency assumptions
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US5420990A (en) * 1993-06-17 1995-05-30 Digital Equipment Corporation Mechanism for enforcing the correct order of instruction execution
US5421022A (en) * 1993-06-17 1995-05-30 Digital Equipment Corporation Apparatus and method for speculatively executing instructions in a computer system
US5428807A (en) * 1993-06-17 1995-06-27 Digital Equipment Corporation Method and apparatus for propagating exception conditions of a computer system
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US5828895A (en) * 1995-09-20 1998-10-27 International Business Machines Corporation Methods and system for predecoding instructions in a superscalar data processing system
US6055628A (en) * 1997-01-24 2000-04-25 Texas Instruments Incorporated Microprocessor with a nestable delayed branch instruction without branch related pipeline interlocks
US6167506A (en) * 1997-11-17 2000-12-26 Advanced Micro Devices, Inc. Replacing displacement in control transfer instruction with encoding indicative of target address, including offset and target cache line location
US6134649A (en) * 1997-11-17 2000-10-17 Advanced Micro Devices, Inc. Control transfer indication in predecode which identifies control transfer instruction and an alternate feature of an instruction
US6061786A (en) * 1998-04-23 2000-05-09 Advanced Micro Devices, Inc. Processor configured to select a next fetch address by partially decoding a byte of a control transfer instruction
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US6615300B1 (en) * 2000-06-19 2003-09-02 Transmeta Corporation Fast look-up of indirect branch destination in a dynamic translation system
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US8484282B2 (en) * 2002-03-21 2013-07-09 International Business Machines Corporation High-speed content transformation engine
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Also Published As

Publication number Publication date
CA1282181C (en) 1991-03-26
US4722050A (en) 1988-01-26
JPS62235658A (ja) 1987-10-15
EP0238810A2 (de) 1987-09-30
EP0238810A3 (en) 1990-04-25
EP0238810B1 (de) 1995-01-04
DE3750935D1 (de) 1995-02-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE),

8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE