DE3766890D1 - Methode zur herstellung eines halbleiterbauelements mit gutem ohmischen kontakt zwischen einer vielzahl von verdrahtungsebenen. - Google Patents

Methode zur herstellung eines halbleiterbauelements mit gutem ohmischen kontakt zwischen einer vielzahl von verdrahtungsebenen.

Info

Publication number
DE3766890D1
DE3766890D1 DE8787305084T DE3766890T DE3766890D1 DE 3766890 D1 DE3766890 D1 DE 3766890D1 DE 8787305084 T DE8787305084 T DE 8787305084T DE 3766890 T DE3766890 T DE 3766890T DE 3766890 D1 DE3766890 D1 DE 3766890D1
Authority
DE
Germany
Prior art keywords
variety
producing
ohmic contact
semiconductor component
good ohmic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787305084T
Other languages
English (en)
Inventor
Ryoichi Mukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3766890D1 publication Critical patent/DE3766890D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H01L23/5254—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/093—Laser beam treatment in general
DE8787305084T 1986-06-13 1987-06-09 Methode zur herstellung eines halbleiterbauelements mit gutem ohmischen kontakt zwischen einer vielzahl von verdrahtungsebenen. Expired - Fee Related DE3766890D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61137509A JPS62293740A (ja) 1986-06-13 1986-06-13 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE3766890D1 true DE3766890D1 (de) 1991-02-07

Family

ID=15200330

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787305084T Expired - Fee Related DE3766890D1 (de) 1986-06-13 1987-06-09 Methode zur herstellung eines halbleiterbauelements mit gutem ohmischen kontakt zwischen einer vielzahl von verdrahtungsebenen.

Country Status (5)

Country Link
US (1) US4800179A (de)
EP (1) EP0251523B1 (de)
JP (1) JPS62293740A (de)
KR (1) KR900004268B1 (de)
DE (1) DE3766890D1 (de)

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DE4200809C2 (de) * 1991-03-20 1996-12-12 Samsung Electronics Co Ltd Verfahren zur Bildung einer metallischen Verdrahtungsschicht in einem Halbleiterbauelement
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US6830993B1 (en) * 2000-03-21 2004-12-14 The Trustees Of Columbia University In The City Of New York Surface planarization of thin silicon films during and after processing by the sequential lateral solidification method
DE10046170A1 (de) 2000-09-19 2002-04-04 Fraunhofer Ges Forschung Verfahren zur Herstellung eines Halbleiter-Metallkontaktes durch eine dielektrische Schicht
US7115503B2 (en) * 2000-10-10 2006-10-03 The Trustees Of Columbia University In The City Of New York Method and apparatus for processing thin metal layers
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WO2005029548A2 (en) * 2003-09-16 2005-03-31 The Trustees Of Columbia University In The City Of New York System and process for providing multiple beam sequential lateral solidification
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US7364952B2 (en) * 2003-09-16 2008-04-29 The Trustees Of Columbia University In The City Of New York Systems and methods for processing thin films
WO2005029550A2 (en) * 2003-09-16 2005-03-31 The Trustees Of Columbia University In The City Of New York Method and system for producing crystalline thin films with a uniform crystalline orientation
WO2005029547A2 (en) * 2003-09-16 2005-03-31 The Trustees Of Columbia University In The City Of New York Enhancing the width of polycrystalline grains with mask
WO2005034193A2 (en) 2003-09-19 2005-04-14 The Trustees Of Columbia University In The City Ofnew York Single scan irradiation for crystallization of thin films
US7645337B2 (en) * 2004-11-18 2010-01-12 The Trustees Of Columbia University In The City Of New York Systems and methods for creating crystallographic-orientation controlled poly-silicon films
US8637340B2 (en) 2004-11-30 2014-01-28 Solexel, Inc. Patterning of silicon oxide layers using pulsed laser ablation
US8399331B2 (en) 2007-10-06 2013-03-19 Solexel Laser processing for high-efficiency thin crystalline silicon solar cell fabrication
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Also Published As

Publication number Publication date
US4800179A (en) 1989-01-24
KR900004268B1 (ko) 1990-06-18
KR880001044A (ko) 1988-03-31
EP0251523A1 (de) 1988-01-07
EP0251523B1 (de) 1991-01-02
JPS62293740A (ja) 1987-12-21

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