DE3767431D1 - Verfahren zur herstellung von halbleiterbauelementen. - Google Patents
Verfahren zur herstellung von halbleiterbauelementen.Info
- Publication number
- DE3767431D1 DE3767431D1 DE8787903050T DE3767431T DE3767431D1 DE 3767431 D1 DE3767431 D1 DE 3767431D1 DE 8787903050 T DE8787903050 T DE 8787903050T DE 3767431 T DE3767431 T DE 3767431T DE 3767431 D1 DE3767431 D1 DE 3767431D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor components
- producing semiconductor
- producing
- components
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
- H01L29/41783—Raised source or drain electrodes self aligned with the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/009—Bi-MOS
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/01—Bipolar transistors-ion implantation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/124—Polycrystalline emitter
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/151—Simultaneous diffusion
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US85488586A | 1986-04-23 | 1986-04-23 | |
PCT/US1987/000766 WO1987006764A1 (en) | 1986-04-23 | 1987-03-31 | Process for manufacturing semiconductor devices |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3767431D1 true DE3767431D1 (de) | 1991-02-21 |
Family
ID=25319783
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8787903050T Expired - Fee Related DE3767431D1 (de) | 1986-04-23 | 1987-03-31 | Verfahren zur herstellung von halbleiterbauelementen. |
Country Status (8)
Country | Link |
---|---|
US (2) | US4784971A (de) |
EP (1) | EP0265489B1 (de) |
JP (1) | JP2537936B2 (de) |
KR (1) | KR910002831B1 (de) |
CA (2) | CA1271566A1 (de) |
DE (1) | DE3767431D1 (de) |
ES (1) | ES2004607A6 (de) |
WO (1) | WO1987006764A1 (de) |
Families Citing this family (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3230077A1 (de) * | 1982-08-12 | 1984-02-16 | Siemens AG, 1000 Berlin und 8000 München | Integrierte bipolar- und mos-transistoren enthaltende halbleiterschaltung auf einem chip und verfahren zu ihrer herstellung |
US5063168A (en) * | 1986-07-02 | 1991-11-05 | National Semiconductor Corporation | Process for making bipolar transistor with polysilicon stringer base contact |
US4812417A (en) * | 1986-07-30 | 1989-03-14 | Mitsubishi Denki Kabushiki Kaisha | Method of making self aligned external and active base regions in I.C. processing |
US4902640A (en) * | 1987-04-17 | 1990-02-20 | Tektronix, Inc. | High speed double polycide bipolar/CMOS integrated circuit process |
US5214302A (en) * | 1987-05-13 | 1993-05-25 | Hitachi, Ltd. | Semiconductor integrated circuit device forming on a common substrate MISFETs isolated by a field oxide and bipolar transistors isolated by a groove |
KR890003827B1 (ko) * | 1987-07-25 | 1989-10-05 | 재단법인 한국전자통신연구소 | 고속 고집적 반도체소자(Bicmos)의 제조방법 |
FR2626406B1 (fr) * | 1988-01-22 | 1992-01-24 | France Etat | Transistor bipolaire compatible avec la technologie mos |
US4857476A (en) * | 1988-01-26 | 1989-08-15 | Hewlett-Packard Company | Bipolar transistor process using sidewall spacer for aligning base insert |
US5003365A (en) * | 1988-06-09 | 1991-03-26 | Texas Instruments Incorporated | Bipolar transistor with a sidewall-diffused subcollector |
JPH0666329B2 (ja) * | 1988-06-30 | 1994-08-24 | 株式会社東芝 | 半導体装置の製造方法 |
US5089433A (en) * | 1988-08-08 | 1992-02-18 | National Semiconductor Corporation | Bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture |
US5015594A (en) * | 1988-10-24 | 1991-05-14 | International Business Machines Corporation | Process of making BiCMOS devices having closely spaced device regions |
US4945070A (en) * | 1989-01-24 | 1990-07-31 | Harris Corporation | Method of making cmos with shallow source and drain junctions |
US5091760A (en) * | 1989-04-14 | 1992-02-25 | Kabushiki Kaisha Toshiba | Semiconductor device |
US4948745A (en) * | 1989-05-22 | 1990-08-14 | Motorola, Inc. | Process for elevated source/drain field effect structure |
JPH03141645A (ja) * | 1989-07-10 | 1991-06-17 | Texas Instr Inc <Ti> | ポリサイドによる局所的相互接続方法とその方法により製造された半導体素子 |
US5294822A (en) * | 1989-07-10 | 1994-03-15 | Texas Instruments Incorporated | Polycide local interconnect method and structure |
US5024959A (en) * | 1989-09-25 | 1991-06-18 | Motorola, Inc. | CMOS process using doped glass layer |
US5057455A (en) * | 1989-11-30 | 1991-10-15 | At&T Bell Laboratories | Formation of integrated circuit electrodes |
US5182225A (en) * | 1990-01-10 | 1993-01-26 | Microunity Systems Engineering, Inc. | Process for fabricating BICMOS with hypershallow junctions |
US5112761A (en) * | 1990-01-10 | 1992-05-12 | Microunity Systems Engineering | Bicmos process utilizing planarization technique |
US4992848A (en) * | 1990-02-20 | 1991-02-12 | At&T Bell Laboratories | Self-aligned contact technology |
US4980304A (en) * | 1990-02-20 | 1990-12-25 | At&T Bell Laboratories | Process for fabricating a bipolar transistor with a self-aligned contact |
US5107321A (en) * | 1990-04-02 | 1992-04-21 | National Semiconductor Corporation | Interconnect method for semiconductor devices |
US5231042A (en) * | 1990-04-02 | 1993-07-27 | National Semiconductor Corporation | Formation of silicide contacts using a sidewall oxide process |
EP0452720A3 (en) * | 1990-04-02 | 1994-10-26 | Nat Semiconductor Corp | A semiconductor structure and method of its manufacture |
US5139961A (en) * | 1990-04-02 | 1992-08-18 | National Semiconductor Corporation | Reducing base resistance of a bjt by forming a self aligned silicide in the single crystal region of the extrinsic base |
US5234847A (en) * | 1990-04-02 | 1993-08-10 | National Semiconductor Corporation | Method of fabricating a BiCMOS device having closely spaced contacts |
GB2245418A (en) * | 1990-06-20 | 1992-01-02 | Koninkl Philips Electronics Nv | A semiconductor device and a method of manufacturing such a device |
US5168072A (en) * | 1990-10-12 | 1992-12-01 | Texas Instruments Incorporated | Method of fabricating an high-performance insulated-gate field-effect transistor |
US5879997A (en) * | 1991-05-30 | 1999-03-09 | Lucent Technologies Inc. | Method for forming self aligned polysilicon contact |
US5187109A (en) * | 1991-07-19 | 1993-02-16 | International Business Machines Corporation | Lateral bipolar transistor and method of making the same |
US5470772A (en) * | 1991-11-06 | 1995-11-28 | Intel Corporation | Silicidation method for contactless EPROM related devices |
US5258317A (en) * | 1992-02-13 | 1993-11-02 | Integrated Device Technology, Inc. | Method for using a field implant mask to correct low doping levels at the outside edges of the base in a walled-emitter transistor structure |
JPH06120211A (ja) * | 1992-10-06 | 1994-04-28 | Nec Corp | 半導体装置の製造方法 |
JPH06132298A (ja) * | 1992-10-14 | 1994-05-13 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US5407841A (en) * | 1992-10-30 | 1995-04-18 | Hughes Aircraft Company | CBiCMOS fabrication method using sacrificial gate poly |
US5462888A (en) * | 1994-06-06 | 1995-10-31 | At&T Ipm Corp. | Process for manufacturing semiconductor BICMOS device |
US5496750A (en) * | 1994-09-19 | 1996-03-05 | Texas Instruments Incorporated | Elevated source/drain junction metal oxide semiconductor field-effect transistor using blanket silicon deposition |
US5432105A (en) * | 1994-09-19 | 1995-07-11 | United Microelectronics Corporation | Method for fabricating self-aligned polysilicon contacts on FET source/drain areas |
US5527273A (en) * | 1994-10-06 | 1996-06-18 | Misonix, Inc. | Ultrasonic lipectomy probe and method for manufacture |
US5656510A (en) | 1994-11-22 | 1997-08-12 | Lucent Technologies Inc. | Method for manufacturing gate oxide capacitors including wafer backside dielectric and implantation electron flood gun current control |
US5656519A (en) * | 1995-02-14 | 1997-08-12 | Nec Corporation | Method for manufacturing salicide semiconductor device |
US5571733A (en) * | 1995-05-12 | 1996-11-05 | Micron Technology, Inc. | Method of forming CMOS integrated circuitry |
JP3472401B2 (ja) * | 1996-01-17 | 2003-12-02 | 三菱電機株式会社 | 半導体装置の製造方法 |
JP2924763B2 (ja) * | 1996-02-28 | 1999-07-26 | 日本電気株式会社 | 半導体装置の製造方法 |
US6114209A (en) * | 1998-03-19 | 2000-09-05 | Mosel Vitelic Inc. | Method of fabricating semiconductor devices with raised doped region structures |
US6211026B1 (en) | 1998-12-01 | 2001-04-03 | Micron Technology, Inc. | Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors |
JP2000340684A (ja) * | 1999-05-31 | 2000-12-08 | Sony Corp | 半導体装置の製造方法 |
US6495401B1 (en) * | 2000-10-12 | 2002-12-17 | Sharp Laboratories Of America, Inc. | Method of forming an ultra-thin SOI MOS transistor |
US6660600B2 (en) | 2001-01-26 | 2003-12-09 | Micron Technology, Inc. | Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors |
US6506650B1 (en) * | 2001-04-27 | 2003-01-14 | Advanced Micro Devices, Inc. | Method of fabrication based on solid-phase epitaxy for a MOSFET transistor with a controlled dopant profile |
US7772653B1 (en) * | 2004-02-11 | 2010-08-10 | National Semiconductor Corporation | Semiconductor apparatus comprising bipolar transistors and metal oxide semiconductor transistors |
US7271453B2 (en) * | 2004-09-20 | 2007-09-18 | International Business Machines Corporation | Buried biasing wells in FETS |
CN101621030B (zh) * | 2008-07-02 | 2011-01-12 | 中芯国际集成电路制造(上海)有限公司 | 具有多晶硅接触的自对准mos结构 |
US9368599B2 (en) * | 2010-06-22 | 2016-06-14 | International Business Machines Corporation | Graphene/nanostructure FET with self-aligned contact and gate |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5235983A (en) * | 1975-09-17 | 1977-03-18 | Hitachi Ltd | Manufacturing method of field effective transistor |
US4157269A (en) * | 1978-06-06 | 1979-06-05 | International Business Machines Corporation | Utilizing polysilicon diffusion sources and special masking techniques |
JPS5544701A (en) * | 1978-09-25 | 1980-03-29 | Hitachi Ltd | Manufacturing transistor |
US4329706A (en) * | 1979-03-01 | 1982-05-11 | International Business Machines Corporation | Doped polysilicon silicide semiconductor integrated circuit interconnections |
IE52971B1 (en) * | 1979-07-23 | 1988-04-27 | Fujitsu Ltd | Method of manufacturing a semiconductor device wherein first and second layers are formed |
JPS5656676A (en) * | 1979-10-15 | 1981-05-18 | Seiko Epson Corp | Manufacture of mos integrated circuit of mutual compensation type |
IE52791B1 (en) * | 1980-11-05 | 1988-03-02 | Fujitsu Ltd | Semiconductor devices |
US4455738A (en) * | 1981-12-24 | 1984-06-26 | Texas Instruments Incorporated | Self-aligned gate method for making MESFET semiconductor |
US4419810A (en) * | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Self-aligned field effect transistor process |
JPS58175846A (ja) * | 1982-04-08 | 1983-10-15 | Toshiba Corp | 半導体装置の製造方法 |
JPS58225663A (ja) * | 1982-06-23 | 1983-12-27 | Toshiba Corp | 半導体装置の製造方法 |
US4536944A (en) * | 1982-12-29 | 1985-08-27 | International Business Machines Corporation | Method of making ROM/PLA semiconductor device by late stage personalization |
DE3304588A1 (de) * | 1983-02-10 | 1984-08-16 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von mos-transistoren mit flachen source/drain-gebieten, kurzen kanallaengen und einer selbstjustierten, aus einem metallsilizid bestehenden kontaktierungsebene |
US4453306A (en) * | 1983-05-27 | 1984-06-12 | At&T Bell Laboratories | Fabrication of FETs |
JPS6024059A (ja) * | 1983-07-19 | 1985-02-06 | Sony Corp | 半導体装置の製造方法 |
US4536945A (en) * | 1983-11-02 | 1985-08-27 | National Semiconductor Corporation | Process for producing CMOS structures with Schottky bipolar transistors |
US4599789A (en) * | 1984-06-15 | 1986-07-15 | Harris Corporation | Process of making twin well VLSI CMOS |
US4577392A (en) * | 1984-08-03 | 1986-03-25 | Advanced Micro Devices, Inc. | Fabrication technique for integrated circuits |
JPS6063962A (ja) * | 1984-08-06 | 1985-04-12 | Fujitsu Ltd | バイポ−ラトランジスタの製造方法 |
US4621412A (en) * | 1984-09-17 | 1986-11-11 | Sony Corporation | Manufacturing a complementary MOSFET |
US4603468A (en) * | 1984-09-28 | 1986-08-05 | Texas Instruments Incorporated | Method for source/drain self-alignment in stacked CMOS |
US4604790A (en) * | 1985-04-01 | 1986-08-12 | Advanced Micro Devices, Inc. | Method of fabricating integrated circuit structure having CMOS and bipolar devices |
US4735911A (en) * | 1985-12-17 | 1988-04-05 | Siemens Aktiengesellschaft | Process for the simultaneous production of bipolar and complementary MOS transistors on a common silicon substrate |
-
1987
- 1987-03-31 DE DE8787903050T patent/DE3767431D1/de not_active Expired - Fee Related
- 1987-03-31 KR KR1019870701212A patent/KR910002831B1/ko not_active IP Right Cessation
- 1987-03-31 WO PCT/US1987/000766 patent/WO1987006764A1/en active IP Right Grant
- 1987-03-31 JP JP62502887A patent/JP2537936B2/ja not_active Expired - Fee Related
- 1987-03-31 EP EP87903050A patent/EP0265489B1/de not_active Expired - Lifetime
- 1987-04-22 ES ES8701169A patent/ES2004607A6/es not_active Expired
- 1987-04-22 CA CA000535287A patent/CA1271566A1/en active Granted
- 1987-05-08 US US07/047,946 patent/US4784971A/en not_active Expired - Lifetime
- 1987-07-10 US US07/077,953 patent/US4824796A/en not_active Expired - Lifetime
-
1989
- 1989-09-05 CA CA000610374A patent/CA1273128A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
ES2004607A6 (es) | 1989-01-16 |
US4824796A (en) | 1989-04-25 |
CA1271566A1 (en) | 1990-07-10 |
WO1987006764A1 (en) | 1987-11-05 |
CA1273128C (de) | 1990-08-21 |
EP0265489B1 (de) | 1991-01-16 |
KR910002831B1 (ko) | 1991-05-06 |
JP2537936B2 (ja) | 1996-09-25 |
JPS63503185A (ja) | 1988-11-17 |
KR880701461A (ko) | 1988-07-27 |
EP0265489A1 (de) | 1988-05-04 |
US4784971A (en) | 1988-11-15 |
CA1273128A (en) | 1990-08-21 |
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