DE3787671T2 - Halbleiterpackung mit Eingang/Ausgang-Verbindungen hoher Dichte. - Google Patents

Halbleiterpackung mit Eingang/Ausgang-Verbindungen hoher Dichte.

Info

Publication number
DE3787671T2
DE3787671T2 DE87304417T DE3787671T DE3787671T2 DE 3787671 T2 DE3787671 T2 DE 3787671T2 DE 87304417 T DE87304417 T DE 87304417T DE 3787671 T DE3787671 T DE 3787671T DE 3787671 T2 DE3787671 T2 DE 3787671T2
Authority
DE
Germany
Prior art keywords
high density
semiconductor package
fingers
output connections
tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE87304417T
Other languages
English (en)
Other versions
DE3787671D1 (de
Inventor
Lawrence Arnold Greenberg
David Jacob Lando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of DE3787671D1 publication Critical patent/DE3787671D1/de
Application granted granted Critical
Publication of DE3787671T2 publication Critical patent/DE3787671T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
DE87304417T 1986-05-27 1987-05-19 Halbleiterpackung mit Eingang/Ausgang-Verbindungen hoher Dichte. Expired - Fee Related DE3787671T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/866,931 US4774635A (en) 1986-05-27 1986-05-27 Semiconductor package with high density I/O lead connection

Publications (2)

Publication Number Publication Date
DE3787671D1 DE3787671D1 (de) 1993-11-11
DE3787671T2 true DE3787671T2 (de) 1994-02-03

Family

ID=25348753

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87304417T Expired - Fee Related DE3787671T2 (de) 1986-05-27 1987-05-19 Halbleiterpackung mit Eingang/Ausgang-Verbindungen hoher Dichte.

Country Status (7)

Country Link
US (1) US4774635A (de)
EP (1) EP0247775B1 (de)
JP (1) JP2671922B2 (de)
KR (1) KR960004562B1 (de)
AT (1) ATE95631T1 (de)
CA (1) CA1252912A (de)
DE (1) DE3787671T2 (de)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2582013B2 (ja) * 1991-02-08 1997-02-19 株式会社東芝 樹脂封止型半導体装置及びその製造方法
US4974057A (en) * 1986-10-31 1990-11-27 Texas Instruments Incorporated Semiconductor device package with circuit board and resin
US4903113A (en) * 1988-01-15 1990-02-20 International Business Machines Corporation Enhanced tab package
US4987475A (en) * 1988-02-29 1991-01-22 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
JP2786209B2 (ja) * 1988-10-07 1998-08-13 株式会社日立製作所 忘却機能を有する知識データ管理方法
DE3834361A1 (de) * 1988-10-10 1990-04-12 Lsi Logic Products Gmbh Anschlussrahmen fuer eine vielzahl von anschluessen
US5466967A (en) * 1988-10-10 1995-11-14 Lsi Logic Products Gmbh Lead frame for a multiplicity of terminals
US4924291A (en) * 1988-10-24 1990-05-08 Motorola Inc. Flagless semiconductor package
JP2687152B2 (ja) * 1988-12-13 1997-12-08 新光電気工業株式会社 高周波半導体デバイス用のｔａｂテープ
US5183711A (en) * 1988-12-13 1993-02-02 Shinko Electric Industries Co., Ltd. Automatic bonding tape used in semiconductor device
DE3942843A1 (de) * 1989-12-23 1991-06-27 Itt Ind Gmbh Deutsche Verkapselte monolithisch integrierte schaltung
JPH02201948A (ja) * 1989-01-30 1990-08-10 Toshiba Corp 半導体装置パッケージ
US5255156A (en) * 1989-02-22 1993-10-19 The Boeing Company Bonding pad interconnection on a multiple chip module having minimum channel width
US5432127A (en) * 1989-06-30 1995-07-11 Texas Instruments Incorporated Method for making a balanced capacitance lead frame for integrated circuits having a power bus and dummy leads
US5233220A (en) * 1989-06-30 1993-08-03 Texas Instruments Incorporated Balanced capacitance lead frame for integrated circuits and integrated circuit device with separate conductive layer
JPH0336614A (ja) * 1989-07-03 1991-02-18 Mitsumi Electric Co Ltd 回路モジュール
DE68905475T2 (de) * 1989-07-18 1993-09-16 Ibm Halbleiter-speichermodul hoeher dichte.
JPH0777256B2 (ja) * 1989-08-25 1995-08-16 株式会社東芝 樹脂封止型半導体装置
JPH0363774U (de) * 1989-10-23 1991-06-21
US5355017A (en) * 1990-04-06 1994-10-11 Sumitomo Special Metal Co. Ltd. Lead frame having a die pad with metal foil layers attached to the surfaces
EP0458469A1 (de) * 1990-05-24 1991-11-27 Nippon Steel Corporation Verbundleiterrahmen und ihn verwendende Halbleitervorrichtung
US5227662A (en) * 1990-05-24 1993-07-13 Nippon Steel Corporation Composite lead frame and semiconductor device using the same
US5173766A (en) * 1990-06-25 1992-12-22 Lsi Logic Corporation Semiconductor device package and method of making such a package
JP2744685B2 (ja) * 1990-08-08 1998-04-28 三菱電機株式会社 半導体装置
US5233131A (en) * 1990-12-19 1993-08-03 Vlsi Technology, Inc. Integrated circuit die-to-leadframe interconnect assembly system
JPH04280462A (ja) * 1991-03-08 1992-10-06 Mitsubishi Electric Corp リードフレームおよびこのリードフレームを使用した半導体装置
KR940007649B1 (ko) * 1991-04-03 1994-08-22 삼성전자 주식회사 반도체 패키지
US5177591A (en) * 1991-08-20 1993-01-05 Emanuel Norbert T Multi-layered fluid soluble alignment bars
US5231755A (en) * 1991-08-20 1993-08-03 Emanuel Technology, Inc. Method of forming soluble alignment bars
KR930006868A (ko) * 1991-09-11 1993-04-22 문정환 반도체 패키지
KR940006083B1 (ko) * 1991-09-11 1994-07-06 금성일렉트론 주식회사 Loc 패키지 및 그 제조방법
US5249354A (en) * 1991-09-25 1993-10-05 American Telephone & Telegraph Co. Method of making electronic component packages
JP2691799B2 (ja) * 1992-02-20 1997-12-17 ブイ・エル・エス・アイ・テクノロジー・インコーポレイテッド リードフレームに接合された介在ダイ取付基板を有する集積回路パッケージ設計
US5266833A (en) * 1992-03-30 1993-11-30 Capps David F Integrated circuit bus structure
US5365409A (en) * 1993-02-20 1994-11-15 Vlsi Technology, Inc. Integrated circuit package design having an intermediate die-attach substrate bonded to a leadframe
US5384487A (en) * 1993-05-05 1995-01-24 Lsi Logic Corporation Off-axis power branches for interior bond pad arrangements
US5567655A (en) * 1993-05-05 1996-10-22 Lsi Logic Corporation Method for forming interior bond pads having zig-zag linear arrangement
US5424492A (en) * 1994-01-06 1995-06-13 Dell Usa, L.P. Optimal PCB routing methodology for high I/O density interconnect devices
US5455387A (en) * 1994-07-18 1995-10-03 Olin Corporation Semiconductor package with chip redistribution interposer
US5939775A (en) * 1996-11-05 1999-08-17 Gcb Technologies, Llc Leadframe structure and process for packaging intergrated circuits
US6201292B1 (en) * 1997-04-02 2001-03-13 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member used therefor
US6342731B1 (en) * 1997-12-31 2002-01-29 Micron Technology, Inc. Vertically mountable semiconductor device, assembly, and methods
JP3914651B2 (ja) * 1999-02-26 2007-05-16 エルピーダメモリ株式会社 メモリモジュールおよびその製造方法
JP2004253706A (ja) * 2003-02-21 2004-09-09 Seiko Epson Corp リードフレーム、半導体チップのパッケージング部材、半導体装置の製造方法、及び、半導体装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US31967A (en) * 1861-04-09 Improvement in cotton-presses
USRE31967E (en) 1975-07-07 1985-08-13 National Semiconductor Corporation Gang bonding interconnect tape for semiconductive devices and method of making same
JPS56100436A (en) * 1980-01-17 1981-08-12 Toshiba Corp Manufacture of semiconductor element
US4371912A (en) * 1980-10-01 1983-02-01 Motorola, Inc. Method of mounting interrelated components
JPS57207356A (en) * 1981-06-15 1982-12-20 Fujitsu Ltd Semiconductor device
JPS5815241A (ja) * 1981-07-20 1983-01-28 Sumitomo Electric Ind Ltd 半導体装置用基板
JPS58107659A (ja) * 1981-12-21 1983-06-27 Seiko Keiyo Kogyo Kk Ｉｃの実装装置
JPS58122763A (ja) * 1982-01-14 1983-07-21 Toshiba Corp 樹脂封止型半導体装置
DE3219055A1 (de) * 1982-05-21 1983-11-24 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Verfahren zur herstellung eines filmtraegers mit leiterstrukturen
US4498122A (en) * 1982-12-29 1985-02-05 At&T Bell Laboratories High-speed, high pin-out LSI chip package
JPS60227454A (ja) * 1984-04-26 1985-11-12 Nec Corp 半導体素子用リ−ドフレ−ム
DE3516954A1 (de) * 1984-05-14 1985-11-14 Gigabit Logic, Inc., Newbury Park, Calif. Montierte integrierte schaltung
US4631820A (en) * 1984-08-23 1986-12-30 Canon Kabushiki Kaisha Mounting assembly and mounting method for an electronic component
JPS61183936A (ja) * 1985-02-08 1986-08-16 Toshiba Corp 半導体装置
JPS622628A (ja) * 1985-06-28 1987-01-08 Toshiba Corp 半導体装置
US4754317A (en) * 1986-04-28 1988-06-28 Monolithic Memories, Inc. Integrated circuit die-to-lead frame interconnection assembly and method

Also Published As

Publication number Publication date
DE3787671D1 (de) 1993-11-11
EP0247775A3 (en) 1988-01-20
EP0247775A2 (de) 1987-12-02
EP0247775B1 (de) 1993-10-06
KR960004562B1 (ko) 1996-04-09
KR870011692A (ko) 1987-12-26
JPS6324647A (ja) 1988-02-02
JP2671922B2 (ja) 1997-11-05
CA1252912A (en) 1989-04-18
US4774635A (en) 1988-09-27
ATE95631T1 (de) 1993-10-15

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Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN

8339 Ceased/non-payment of the annual fee