DE3851741T2 - Drahtverbindungen und elektrische kontakte einer integrierten schaltungsanordnung. - Google Patents

Drahtverbindungen und elektrische kontakte einer integrierten schaltungsanordnung.

Info

Publication number
DE3851741T2
DE3851741T2 DE3851741T DE3851741T DE3851741T2 DE 3851741 T2 DE3851741 T2 DE 3851741T2 DE 3851741 T DE3851741 T DE 3851741T DE 3851741 T DE3851741 T DE 3851741T DE 3851741 T2 DE3851741 T2 DE 3851741T2
Authority
DE
Germany
Prior art keywords
integrated circuit
electrical contacts
circuit arrangement
wire connections
connections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3851741T
Other languages
English (en)
Other versions
DE3851741D1 (de
Inventor
Jon Long
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Publication of DE3851741D1 publication Critical patent/DE3851741D1/de
Application granted granted Critical
Publication of DE3851741T2 publication Critical patent/DE3851741T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/49524Additional leads the additional leads being a tape carrier or flat leads
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861Lead-frames fixed on or encapsulated in insulating substrates
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    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2924/19101Disposition of discrete passive components
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DE3851741T 1987-05-13 1988-01-26 Drahtverbindungen und elektrische kontakte einer integrierten schaltungsanordnung. Expired - Fee Related DE3851741T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/049,641 US4771330A (en) 1987-05-13 1987-05-13 Wire bonds and electrical contacts of an integrated circuit device
PCT/US1988/000235 WO1988009056A1 (en) 1987-05-13 1988-01-26 Wire bonds and electrical contacts of an integrated circuit device

Publications (2)

Publication Number Publication Date
DE3851741D1 DE3851741D1 (de) 1994-11-10
DE3851741T2 true DE3851741T2 (de) 1995-02-02

Family

ID=21960900

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3851741T Expired - Fee Related DE3851741T2 (de) 1987-05-13 1988-01-26 Drahtverbindungen und elektrische kontakte einer integrierten schaltungsanordnung.

Country Status (8)

Country Link
US (1) US4771330A (de)
EP (1) EP0314707B1 (de)
JP (2) JPH01190102A (de)
KR (1) KR890700925A (de)
AU (1) AU606386B2 (de)
CA (1) CA1300282C (de)
DE (1) DE3851741T2 (de)
WO (1) WO1988009056A1 (de)

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US4987475A (en) * 1988-02-29 1991-01-22 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
US5184207A (en) * 1988-12-07 1993-02-02 Tribotech Semiconductor die packages having lead support frame
US4916519A (en) * 1989-05-30 1990-04-10 International Business Machines Corporation Semiconductor package
US5299730A (en) * 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5227663A (en) * 1989-12-19 1993-07-13 Lsi Logic Corporation Integral dam and heat sink for semiconductor device assembly
US5175612A (en) * 1989-12-19 1992-12-29 Lsi Logic Corporation Heat sink for semiconductor device assembly
JP2527828B2 (ja) * 1990-02-27 1996-08-28 三菱電機株式会社 半導体パッケ―ジ
US5173766A (en) * 1990-06-25 1992-12-22 Lsi Logic Corporation Semiconductor device package and method of making such a package
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5168345A (en) * 1990-08-15 1992-12-01 Lsi Logic Corporation Semiconductor device having a universal die size inner lead layout
US5142450A (en) * 1991-04-12 1992-08-25 Motorola, Inc. Non-contact lead design and package
GB2257827B (en) * 1991-07-17 1995-05-03 Lsi Logic Europ Support for semiconductor bond wires
US5451813A (en) * 1991-09-05 1995-09-19 Rohm Co., Ltd. Semiconductor device with lead frame having different thicknesses
JP2970111B2 (ja) * 1991-09-19 1999-11-02 日本電気株式会社 リードフレーム、半導体装置及びその製造方法
US5434750A (en) * 1992-02-07 1995-07-18 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
JPH0653277A (ja) * 1992-06-04 1994-02-25 Lsi Logic Corp 半導体装置アセンブリおよびその組立方法
US5854085A (en) * 1992-06-04 1998-12-29 Lsi Logic Corporation Multi-layer tab tape having distinct signal, power and ground planes, semiconductor device assembly employing same, apparatus for and method of assembling same
US5801432A (en) * 1992-06-04 1998-09-01 Lsi Logic Corporation Electronic system using multi-layer tab tape semiconductor device having distinct signal, power and ground planes
US5340772A (en) * 1992-07-17 1994-08-23 Lsi Logic Corporation Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die
US5532934A (en) * 1992-07-17 1996-07-02 Lsi Logic Corporation Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions
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KR890700925A (ko) 1989-04-28
WO1988009056A1 (en) 1988-11-17
EP0314707A4 (en) 1990-09-19
JP2583597B2 (ja) 1997-02-19
DE3851741D1 (de) 1994-11-10
EP0314707B1 (de) 1994-10-05
AU1187488A (en) 1988-12-06
JPH01190102A (ja) 1989-07-31
EP0314707A1 (de) 1989-05-10
JPH01503184A (ja) 1989-10-26
CA1300282C (en) 1992-05-05
US4771330A (en) 1988-09-13
AU606386B2 (en) 1991-02-07

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