DE3851928T2 - Steuerung von asynchron arbeitenden Peripheriegeräten. - Google Patents

Steuerung von asynchron arbeitenden Peripheriegeräten.

Info

Publication number
DE3851928T2
DE3851928T2 DE3851928T DE3851928T DE3851928T2 DE 3851928 T2 DE3851928 T2 DE 3851928T2 DE 3851928 T DE3851928 T DE 3851928T DE 3851928 T DE3851928 T DE 3851928T DE 3851928 T2 DE3851928 T2 DE 3851928T2
Authority
DE
Germany
Prior art keywords
control
peripheral devices
asynchronous peripheral
asynchronous
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3851928T
Other languages
English (en)
Other versions
DE3851928D1 (de
Inventor
Robert Nelson Crockett
Robert Frederick Kern
Arnold Grant Miller
Richard Ernest Norris
Michael William Pousson
Robert E Wagner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE3851928D1 publication Critical patent/DE3851928D1/de
Application granted granted Critical
Publication of DE3851928T2 publication Critical patent/DE3851928T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media
    • G06F11/201—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media between storage system components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
DE3851928T 1987-08-28 1988-08-04 Steuerung von asynchron arbeitenden Peripheriegeräten. Expired - Fee Related DE3851928T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/090,722 US4837680A (en) 1987-08-28 1987-08-28 Controlling asynchronously operating peripherals

Publications (2)

Publication Number Publication Date
DE3851928D1 DE3851928D1 (de) 1994-12-01
DE3851928T2 true DE3851928T2 (de) 1995-04-20

Family

ID=22224003

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3851928T Expired - Fee Related DE3851928T2 (de) 1987-08-28 1988-08-04 Steuerung von asynchron arbeitenden Peripheriegeräten.

Country Status (4)

Country Link
US (1) US4837680A (de)
EP (1) EP0305068B1 (de)
JP (1) JPH0661073B2 (de)
DE (1) DE3851928T2 (de)

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US8402346B2 (en) * 2001-12-28 2013-03-19 Netapp, Inc. N-way parity technique for enabling recovery from up to N storage device failures
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Also Published As

Publication number Publication date
JPH0661073B2 (ja) 1994-08-10
DE3851928D1 (de) 1994-12-01
EP0305068A3 (en) 1990-06-27
EP0305068B1 (de) 1994-10-26
EP0305068A2 (de) 1989-03-01
US4837680A (en) 1989-06-06
JPS6462749A (en) 1989-03-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee