DE3856178D1 - Quotient-Phasenverschiebungs-Prozessor für digitale Phasenregelschleife - Google Patents

Quotient-Phasenverschiebungs-Prozessor für digitale Phasenregelschleife

Info

Publication number
DE3856178D1
DE3856178D1 DE3856178T DE3856178T DE3856178D1 DE 3856178 D1 DE3856178 D1 DE 3856178D1 DE 3856178 T DE3856178 T DE 3856178T DE 3856178 T DE3856178 T DE 3856178T DE 3856178 D1 DE3856178 D1 DE 3856178D1
Authority
DE
Germany
Prior art keywords
locked loop
quotient
phase shift
shift processor
phase locked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3856178T
Other languages
English (en)
Other versions
DE3856178T2 (de
Inventor
Jesus Guinea
Hee Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Application granted granted Critical
Publication of DE3856178D1 publication Critical patent/DE3856178D1/de
Publication of DE3856178T2 publication Critical patent/DE3856178T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
DE3856178T 1987-10-14 1988-10-11 Quotient-Phasenverschiebungs-Prozessor für digitale Phasenregelschleife Expired - Lifetime DE3856178T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/108,371 US4862485A (en) 1987-10-14 1987-10-14 Quotient phase-shift processor for digital phase-locked-loops

Publications (2)

Publication Number Publication Date
DE3856178D1 true DE3856178D1 (de) 1998-06-18
DE3856178T2 DE3856178T2 (de) 1998-12-17

Family

ID=22321834

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3856178T Expired - Lifetime DE3856178T2 (de) 1987-10-14 1988-10-11 Quotient-Phasenverschiebungs-Prozessor für digitale Phasenregelschleife

Country Status (5)

Country Link
US (1) US4862485A (de)
EP (1) EP0311973B1 (de)
JP (1) JPH021621A (de)
CA (1) CA1291539C (de)
DE (1) DE3856178T2 (de)

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JP2693784B2 (ja) * 1988-07-05 1997-12-24 株式会社リコー 画像形成装置
US5341405A (en) * 1991-06-11 1994-08-23 Digital Equipment Corporation Data recovery apparatus and methods
US5255287A (en) * 1991-06-28 1993-10-19 Digital Equipment Corporation Transceiver apparatus and methods
US5412691A (en) * 1991-06-28 1995-05-02 Digital Equipment Corporation Method and apparatus for equalization for transmission over a band-limited channel
US5241285A (en) * 1991-10-03 1993-08-31 Apogee Electronics Corporation Phase locked loop reference slaving circuit
JP3241079B2 (ja) * 1992-02-24 2001-12-25 株式会社日立製作所 ディジタル位相同期回路
US5408473A (en) * 1992-03-03 1995-04-18 Digital Equipment Corporation Method and apparatus for transmission of communication signals over two parallel channels
JPH0795056A (ja) * 1993-05-10 1995-04-07 Internatl Business Mach Corp <Ibm> 可変周波数基準クロック生成装置
US5832048A (en) * 1993-12-30 1998-11-03 International Business Machines Corporation Digital phase-lock loop control system
US5493243A (en) * 1994-01-04 1996-02-20 Level One Communications, Inc. Digitally controlled first order jitter attentuator using a digital frequency synthesizer
US5581585A (en) * 1994-10-21 1996-12-03 Level One Communications, Inc. Phase-locked loop timing recovery circuit
US5561660A (en) * 1995-04-05 1996-10-01 Silicon Systems, Inc. Offset and phase correction for delta-sigma modulators
US5701099A (en) * 1995-11-27 1997-12-23 Level One Communications, Inc. Transconductor-C filter element with coarse and fine adjustment
US6249557B1 (en) 1997-03-04 2001-06-19 Level One Communications, Inc. Apparatus and method for performing timing recovery
US6229863B1 (en) 1998-11-02 2001-05-08 Adc Telecommunications, Inc. Reducing waiting time jitter
US6696828B2 (en) 1999-11-30 2004-02-24 Kabushiki Kaisha Toshiba Integrated circuit and lot selection system therefor
WO2002084967A2 (en) * 2001-04-16 2002-10-24 Thomson Licensing S.A. A phase tracking system
US7031687B2 (en) 2001-04-18 2006-04-18 Nokia Corporation Balanced circuit arrangement and method for linearizing such an arrangement
US6704329B2 (en) * 2001-05-08 2004-03-09 Path 1 Network Technologies Inc. Minimizing the effect of jitter upon the quality of service operation of networked gateway devices
US6633185B2 (en) * 2001-10-16 2003-10-14 Altera Corporation PLL/DLL circuitry programmable for high bandwidth and low bandwidth applications
DE10245556B3 (de) * 2002-09-30 2004-04-22 Siemens Audiologische Technik Gmbh Hörhilfegerät oder Hörgerätesystem mit einem Taktgenerator und Verfahren zu deren Betrieb
US7768981B1 (en) 2005-06-14 2010-08-03 Marvell International Ltd. Bluetooth coexistence timing synchronization
JP5243042B2 (ja) * 2005-12-09 2013-07-24 ソニー株式会社 音楽編集装置及び音楽編集方法
DE102006011285B4 (de) * 2006-03-10 2019-09-05 Intel Deutschland Gmbh Schwingkreisanordnung mit digitaler Steuerung, Verfahren zur Erzeugung eines Schwingungssignals und digitaler Phasenregelkreis mit der Schwingkreisanordnung
KR101284943B1 (ko) * 2006-06-30 2013-07-10 엘지디스플레이 주식회사 몰드의 제조방법
US8509371B2 (en) * 2009-09-29 2013-08-13 Analog Devices, Inc. Continuous-rate clock recovery circuit
US8681917B2 (en) 2010-03-31 2014-03-25 Andrew Llc Synchronous transfer of streaming data in a distributed antenna system
US9495285B2 (en) 2014-09-16 2016-11-15 Integrated Device Technology, Inc. Initiating operation of a timing device using a read only memory (ROM) or a one time programmable non volatile memory (OTP NVM)
US9553570B1 (en) 2014-12-10 2017-01-24 Integrated Device Technology, Inc. Crystal-less jitter attenuator
US9369139B1 (en) 2015-02-14 2016-06-14 Integrated Device Technology, Inc. Fractional reference-injection PLL
US9336896B1 (en) 2015-03-23 2016-05-10 Integrated Device Technology, Inc. System and method for voltage regulation of one-time-programmable (OTP) memory programming voltage
US9455045B1 (en) 2015-04-20 2016-09-27 Integrated Device Technology, Inc. Controlling operation of a timing device using an OTP NVM to store timing device configurations in a RAM
US9362928B1 (en) * 2015-07-08 2016-06-07 Integrated Device Technology, Inc. Low-spurious fractional N-frequency divider and method of use
US9954516B1 (en) 2015-08-19 2018-04-24 Integrated Device Technology, Inc. Timing device having multi-purpose pin with proactive function
US9590637B1 (en) 2015-08-28 2017-03-07 Integrated Device Technology, Inc. High-speed programmable frequency divider with 50% output duty cycle
US9847869B1 (en) 2015-10-23 2017-12-19 Integrated Device Technology, Inc. Frequency synthesizer with microcode control
US9614508B1 (en) 2015-12-03 2017-04-04 Integrated Device Technology, Inc. System and method for deskewing output clock signals
US10075284B1 (en) 2016-01-21 2018-09-11 Integrated Device Technology, Inc. Pulse width modulation (PWM) to align clocks across multiple separated cards within a communication system
US9852039B1 (en) 2016-02-03 2017-12-26 Integrated Device Technology, Inc Phase locked loop (PLL) timing device evaluation system and method for evaluating PLL timing devices
US9859901B1 (en) 2016-03-08 2018-01-02 Integrated Device Technology, Inc. Buffer with programmable input/output phase relationship
US9692394B1 (en) 2016-03-25 2017-06-27 Integrated Device Technology, Inc. Programmable low power high-speed current steering logic (LPHCSL) driver and method of use
US9698787B1 (en) 2016-03-28 2017-07-04 Integrated Device Technology, Inc. Integrated low voltage differential signaling (LVDS) and high-speed current steering logic (HCSL) circuit and method of use
US9581973B1 (en) 2016-03-29 2017-02-28 Integrated Device Technology, Inc. Dual mode clock using a common resonator and associated method of use
US9954541B1 (en) 2016-03-29 2018-04-24 Integrated Device Technology, Inc. Bulk acoustic wave resonator based fractional frequency synthesizer and method of use
US9654121B1 (en) 2016-06-01 2017-05-16 Integrated Device Technology, Inc. Calibration method and apparatus for phase locked loop circuit
CN107508596B (zh) * 2017-09-04 2020-06-23 中国电子科技集团公司第四十一研究所 一种带有辅助捕获装置的多环锁相电路及频率预置方法

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DE2413604A1 (de) * 1974-03-21 1975-09-25 Blaupunkt Werke Gmbh Phasenverriegelte regelschleife
US3983498A (en) * 1975-11-13 1976-09-28 Motorola, Inc. Digital phase lock loop
US4400817A (en) * 1980-12-30 1983-08-23 Motorola, Inc. Method and means of clock recovery in a received stream of digital data
US4385396A (en) * 1981-06-05 1983-05-24 Phillips Petroleum Company NRZ Digital data recovery
US4534044A (en) * 1983-05-02 1985-08-06 Honeywell Information Systems Inc. Diskette read data recovery system
US4577163A (en) * 1984-07-09 1986-03-18 Honeywell Inc. Digital phase locked loop
US4633193A (en) * 1985-12-02 1986-12-30 At&T Bell Laboratories Clock circuit synchronizer using a frequency synthesizer controlled by a frequency estimator
US4713630A (en) * 1986-07-29 1987-12-15 Communications Satellite Corporation BPSK Costas-type PLL circuit having false lock prevention

Also Published As

Publication number Publication date
EP0311973A2 (de) 1989-04-19
US4862485A (en) 1989-08-29
EP0311973A3 (de) 1991-03-27
DE3856178T2 (de) 1998-12-17
JPH021621A (ja) 1990-01-05
CA1291539C (en) 1991-10-29
EP0311973B1 (de) 1998-05-13

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