DE3884101T2 - Abholung von Operanden in Unordnung. - Google Patents

Abholung von Operanden in Unordnung.

Info

Publication number
DE3884101T2
DE3884101T2 DE88106390T DE3884101T DE3884101T2 DE 3884101 T2 DE3884101 T2 DE 3884101T2 DE 88106390 T DE88106390 T DE 88106390T DE 3884101 T DE3884101 T DE 3884101T DE 3884101 T2 DE3884101 T2 DE 3884101T2
Authority
DE
Germany
Prior art keywords
disarray
operands
picking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88106390T
Other languages
English (en)
Other versions
DE3884101D1 (de
Inventor
Philip George Emma
Iii Joshua Wilson Knight
James Herbert Pomerene
Rudolph Nathan Rechtschaffen
Frank John Sparacio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3884101D1 publication Critical patent/DE3884101D1/de
Publication of DE3884101T2 publication Critical patent/DE3884101T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
DE88106390T 1987-05-18 1988-04-21 Abholung von Operanden in Unordnung. Expired - Fee Related DE3884101T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/051,792 US4991090A (en) 1987-05-18 1987-05-18 Posting out-of-sequence fetches

Publications (2)

Publication Number Publication Date
DE3884101D1 DE3884101D1 (de) 1993-10-21
DE3884101T2 true DE3884101T2 (de) 1994-04-21

Family

ID=21973404

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88106390T Expired - Fee Related DE3884101T2 (de) 1987-05-18 1988-04-21 Abholung von Operanden in Unordnung.

Country Status (4)

Country Link
US (1) US4991090A (de)
EP (1) EP0302999B1 (de)
JP (1) JPS63293639A (de)
DE (1) DE3884101T2 (de)

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US5197139A (en) * 1990-04-05 1993-03-23 International Business Machines Corporation Cache management for multi-processor systems utilizing bulk cross-invalidate
US5151981A (en) * 1990-07-13 1992-09-29 International Business Machines Corporation Instruction sampling instrumentation
US5446850A (en) * 1991-01-15 1995-08-29 International Business Machines Corporation Cross-cache-line compounding algorithm for scism processors
US5257354A (en) * 1991-01-16 1993-10-26 International Business Machines Corporation System for monitoring and undoing execution of instructions beyond a serialization point upon occurrence of in-correct results
US5261071A (en) * 1991-03-21 1993-11-09 Control Data System, Inc. Dual pipe cache memory with out-of-order issue capability
US5630157A (en) * 1991-06-13 1997-05-13 International Business Machines Corporation Computer organization for multiple and out-of-order execution of condition code testing and setting instructions
US5636363A (en) * 1991-06-14 1997-06-03 Integrated Device Technology, Inc. Hardware control structure and method for off-chip monitoring entries of an on-chip cache
US5317711A (en) * 1991-06-14 1994-05-31 Integrated Device Technology, Inc. Structure and method for monitoring an internal cache
JP2786574B2 (ja) * 1992-05-06 1998-08-13 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュータ・システムにおける順不同ロード動作の性能を改善する方法と装置
US5355471A (en) * 1992-08-14 1994-10-11 Pyramid Technology Corporation Multiprocessor cache coherency tester that exercises the coherency logic exhaustively and also detects errors in a processor using an automatic CPU sort
JP3644959B2 (ja) * 1992-09-29 2005-05-11 セイコーエプソン株式会社 マイクロプロセッサシステム
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US5488706A (en) * 1992-12-18 1996-01-30 Amdahl Corporation Retry request system in a pipeline data processing system where each requesting unit preserves the order of requests
US5467473A (en) * 1993-01-08 1995-11-14 International Business Machines Corporation Out of order instruction load and store comparison
US5493669A (en) * 1993-03-03 1996-02-20 Motorola, Inc. Data processor for simultaneously searching two fields of the rename buffer having first and second most recently allogated bits
JP2560988B2 (ja) * 1993-07-16 1996-12-04 日本電気株式会社 情報処理装置および処理方法
US6138230A (en) * 1993-10-18 2000-10-24 Via-Cyrix, Inc. Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline
US5463745A (en) * 1993-12-22 1995-10-31 Intel Corporation Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system
US5535358A (en) * 1993-12-27 1996-07-09 Matsushita Electric Industrial Co., Ltd. Cache memory control circuit and method for controlling reading and writing requests
US5588126A (en) * 1993-12-30 1996-12-24 Intel Corporation Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system
US5627985A (en) * 1994-01-04 1997-05-06 Intel Corporation Speculative and committed resource files in an out-of-order processor
US5898854A (en) * 1994-01-04 1999-04-27 Intel Corporation Apparatus for indicating an oldest non-retired load operation in an array
US5452426A (en) * 1994-01-04 1995-09-19 Intel Corporation Coordinating speculative and committed state register source data and immediate source data in a processor
US5577200A (en) * 1994-02-28 1996-11-19 Intel Corporation Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system
US5465336A (en) * 1994-06-30 1995-11-07 International Business Machines Corporation Fetch and store buffer that enables out-of-order execution of memory instructions in a data processing system
US5699538A (en) * 1994-12-09 1997-12-16 International Business Machines Corporation Efficient firm consistency support mechanisms in an out-of-order execution superscaler multiprocessor
TW295646B (de) * 1995-01-25 1997-01-11 Ibm
US5649155A (en) * 1995-03-31 1997-07-15 International Business Machines Corporation Cache memory accessed by continuation requests
US5751946A (en) * 1996-01-18 1998-05-12 International Business Machines Corporation Method and system for detecting bypass error conditions in a load/store unit of a superscalar processor
US5737636A (en) * 1996-01-18 1998-04-07 International Business Machines Corporation Method and system for detecting bypass errors in a load/store unit of a superscalar processor
JP2806359B2 (ja) * 1996-04-30 1998-09-30 日本電気株式会社 命令処理方法及び命令処理装置
JP2783259B2 (ja) * 1996-07-18 1998-08-06 日本電気株式会社 半導体パッケージとその製造方法
US6021261A (en) * 1996-12-05 2000-02-01 International Business Machines Corporation Method and system for testing a multiprocessor data processing system utilizing a plurality of event tracers
US5909698A (en) * 1997-03-17 1999-06-01 International Business Machines Corporation Cache block store instruction operations where cache coherency is achieved without writing all the way back to main memory
US6289437B1 (en) * 1997-08-27 2001-09-11 International Business Machines Corporation Data processing system and method for implementing an efficient out-of-order issue mechanism
JP2004094533A (ja) * 2002-08-30 2004-03-25 Hajime Seki 計算機システム
US9483409B2 (en) 2015-02-05 2016-11-01 International Business Machines Corporation Store forwarding cache

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US3553655A (en) * 1969-03-28 1971-01-05 Ibm Short forward conditional skip hardware
US4092713A (en) * 1977-06-13 1978-05-30 Sperry Rand Corporation Post-write address word correction in cache memory system
US4354232A (en) * 1977-12-16 1982-10-12 Honeywell Information Systems Inc. Cache memory command buffer circuit
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US4189772A (en) * 1978-03-16 1980-02-19 International Business Machines Corporation Operand alignment controls for VFL instructions
US4197580A (en) * 1978-06-08 1980-04-08 Bell Telephone Laboratories, Incorporated Data processing system including a cache memory
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JPS56149646A (en) * 1980-04-21 1981-11-19 Toshiba Corp Operation controller
US4438492A (en) * 1980-08-01 1984-03-20 Advanced Micro Devices, Inc. Interruptable microprogram controller for microcomputer systems
US4399507A (en) * 1981-06-30 1983-08-16 Ibm Corporation Instruction address stack in the data memory of an instruction-pipelined processor
US4484267A (en) * 1981-12-30 1984-11-20 International Business Machines Corporation Cache sharing control in a multiprocessor
US4594660A (en) * 1982-10-13 1986-06-10 Honeywell Information Systems Inc. Collector
US4594659A (en) * 1982-10-13 1986-06-10 Honeywell Information Systems Inc. Method and apparatus for prefetching instructions for a central execution pipeline unit
JPS59160899A (ja) * 1982-12-09 1984-09-11 セコイア・システムス・インコ−ポレ−テツド メモリ−・バツク・アツプ・システム
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US4648030A (en) * 1983-09-22 1987-03-03 Digital Equipment Corporation Cache invalidation mechanism for multiprocessor systems
JPH0827718B2 (ja) * 1983-10-05 1996-03-21 株式会社日立製作所 情報処理装置
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US4637024A (en) * 1984-11-02 1987-01-13 International Business Machines Corporation Redundant page identification for a catalogued memory
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Also Published As

Publication number Publication date
US4991090A (en) 1991-02-05
EP0302999A3 (de) 1991-11-06
EP0302999A2 (de) 1989-02-15
JPH0552968B2 (de) 1993-08-06
JPS63293639A (ja) 1988-11-30
DE3884101D1 (de) 1993-10-21
EP0302999B1 (de) 1993-09-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee