DE3888184D1 - Verfahren zur Herstellung von Masken mit Strukturen im Submikrometerbereich. - Google Patents
Verfahren zur Herstellung von Masken mit Strukturen im Submikrometerbereich.Info
- Publication number
- DE3888184D1 DE3888184D1 DE88119094T DE3888184T DE3888184D1 DE 3888184 D1 DE3888184 D1 DE 3888184D1 DE 88119094 T DE88119094 T DE 88119094T DE 3888184 T DE3888184 T DE 3888184T DE 3888184 D1 DE3888184 D1 DE 3888184D1
- Authority
- DE
- Germany
- Prior art keywords
- masks
- structures
- production
- submicrometer range
- submicrometer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/094—Multilayer resist systems, e.g. planarising layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30608—Anisotropic liquid etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Architecture (AREA)
- Structural Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP88119094A EP0369053B1 (de) | 1988-11-17 | 1988-11-17 | Verfahren zur Herstellung von Masken mit Strukturen im Submikrometerbereich |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3888184D1 true DE3888184D1 (de) | 1994-04-07 |
Family
ID=8199575
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE88119094T Expired - Fee Related DE3888184D1 (de) | 1988-11-17 | 1988-11-17 | Verfahren zur Herstellung von Masken mit Strukturen im Submikrometerbereich. |
Country Status (4)
Country | Link |
---|---|
US (1) | US5055383A (de) |
EP (1) | EP0369053B1 (de) |
JP (1) | JPH0827533B2 (de) |
DE (1) | DE3888184D1 (de) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1248534B (it) * | 1991-06-24 | 1995-01-19 | Sgs Thomson Microelectronics | Procedimento per la realizzazione di strutture di calibrazione particolarmente per la taratura di macchine di misura del disallineamento in circuiti integrati in genere. |
KR940010315B1 (ko) * | 1991-10-10 | 1994-10-22 | 금성 일렉트론 주식회사 | 반도체 소자의 미세 패턴 형성 방법 |
US5348619A (en) * | 1992-09-03 | 1994-09-20 | Texas Instruments Incorporated | Metal selective polymer removal |
US6139483A (en) * | 1993-07-27 | 2000-10-31 | Texas Instruments Incorporated | Method of forming lateral resonant tunneling devices |
KR100303279B1 (ko) * | 1994-08-27 | 2001-12-01 | 윤종용 | 반도체레이저다이오드와그제조방법 |
US5652163A (en) * | 1994-12-13 | 1997-07-29 | Lsi Logic Corporation | Use of reticle stitching to provide design flexibility |
AU3222397A (en) | 1996-06-10 | 1998-01-07 | Holographic Lithography Systems | Process for modulating interferometric lithography patterns to record selected discrete patterns in photoresist |
US6088505A (en) * | 1996-06-10 | 2000-07-11 | Holographic Lithography Systems, Inc. | Holographic patterning method and tool for production environments |
CA2233096C (en) | 1997-03-26 | 2003-01-07 | Canon Kabushiki Kaisha | Substrate and production method thereof |
US6077560A (en) * | 1997-12-29 | 2000-06-20 | 3M Innovative Properties Company | Method for continuous and maskless patterning of structured substrates |
TW460758B (en) | 1998-05-14 | 2001-10-21 | Holographic Lithography System | A holographic lithography system for generating an interference pattern suitable for selectively exposing a photosensitive material |
US6744909B1 (en) | 1999-08-19 | 2004-06-01 | Physical Optics Corporation | Authentication system and method |
US7167615B1 (en) | 1999-11-05 | 2007-01-23 | Board Of Regents, The University Of Texas System | Resonant waveguide-grating filters and sensors and methods for making and using same |
US6255147B1 (en) * | 2000-01-31 | 2001-07-03 | Advanced Micro Devices, Inc. | Silicon on insulator circuit structure with extra narrow field transistors and method of forming same |
US6790782B1 (en) | 2001-12-28 | 2004-09-14 | Advanced Micro Devices, Inc. | Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal |
US20030173648A1 (en) * | 2002-03-16 | 2003-09-18 | Sniegowski Jeffry Joseph | Multi-die chip and method for making the same |
US6579809B1 (en) | 2002-05-16 | 2003-06-17 | Advanced Micro Devices, Inc. | In-situ gate etch process for fabrication of a narrow gate transistor structure with a high-k gate dielectric |
US6982135B2 (en) | 2003-03-28 | 2006-01-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Pattern compensation for stitching |
US6835262B1 (en) * | 2003-06-19 | 2004-12-28 | Northrop Grumman Corporation | Positive pressure hot bonder |
KR100710200B1 (ko) * | 2005-06-27 | 2007-04-20 | 동부일렉트로닉스 주식회사 | 씨모스 이미지 센서의 제조방법 |
DE102013212173B4 (de) * | 2013-06-26 | 2016-06-02 | Robert Bosch Gmbh | MEMS-Bauelement mit einer auslenkbaren Membran und einem feststehenden Gegenelement sowie Verfahren zu dessen Herstellung |
US10049875B2 (en) * | 2016-03-04 | 2018-08-14 | Tokyo Electron Limited | Trim method for patterning during various stages of an integration scheme |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL130926C (de) * | 1959-09-04 | |||
US3700433A (en) * | 1971-07-12 | 1972-10-24 | United Aircraft Corp | Enhancement of transverse properties of directionally solidified superalloys |
US4209349A (en) * | 1978-11-03 | 1980-06-24 | International Business Machines Corporation | Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching |
US4354896A (en) * | 1980-08-05 | 1982-10-19 | Texas Instruments Incorporated | Formation of submicron substrate element |
US4331708A (en) * | 1980-11-04 | 1982-05-25 | Texas Instruments Incorporated | Method of fabricating narrow deep grooves in silicon |
US4397937A (en) * | 1982-02-10 | 1983-08-09 | International Business Machines Corporation | Positive resist compositions |
DE3242113A1 (de) * | 1982-11-13 | 1984-05-24 | Ibm Deutschland Gmbh, 7000 Stuttgart | Verfahren zur herstellung einer duennen dielektrischen isolation in einem siliciumhalbleiterkoerper |
US4648937A (en) * | 1985-10-30 | 1987-03-10 | International Business Machines Corporation | Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer |
US4654119A (en) * | 1985-11-18 | 1987-03-31 | International Business Machines Corporation | Method for making submicron mask openings using sidewall and lift-off techniques |
EP0280587A1 (de) * | 1987-01-20 | 1988-08-31 | Thomson Components-Mostek Corporation | VLSI-Verfahren unter Verwendung einer Maske mit Distanzstücken |
-
1988
- 1988-11-17 EP EP88119094A patent/EP0369053B1/de not_active Expired - Lifetime
- 1988-11-17 DE DE88119094T patent/DE3888184D1/de not_active Expired - Fee Related
-
1989
- 1989-10-12 US US07/420,870 patent/US5055383A/en not_active Expired - Fee Related
- 1989-11-17 JP JP29781589A patent/JPH0827533B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH02251849A (ja) | 1990-10-09 |
JPH0827533B2 (ja) | 1996-03-21 |
EP0369053B1 (de) | 1994-03-02 |
US5055383A (en) | 1991-10-08 |
EP0369053A1 (de) | 1990-05-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |