DE4204383A1 - Distributed controlled data communication system for industrial automation - has network with mixed structure with processor modules interconnected via bus simplifying local configuration needs - Google Patents

Abstract

The reliable data communication system for use in real time automation systems in industry has a modular structure based upon standardised components. The network is flexible and has a mixed structure enabling ease configuring to meet specific requirements. The system uses processor modules that forms nodes and can be locked with different operating software. Each process has a microcontroller together with a range of memories. Multiple I/O parts are provided. USE/ADVANTAGE - For real time automation system. High reliability. Flexibility in configuration.

Description

1.1 Description

Decentralized, highly reliable data transport system, especially for use in industrial automation technology.

It is known that today in industrial automation technology used data transport systems (fieldbus systems) only meet high reliability requirements can, if bidirectional ring structures are used / KRGI90 /.

With the increasing complexity of technical systems, the ever greater spatial expansion and the increasing number of sensors / actuators to be controlled by the automation system, a single, ring-shaped data transport system can no longer meet the requirements. Comprehensive structures that also have real-time properties can only be built up today using hierarchically organized systems from coupled ring structures ( Figure 1.1).

This creates data transport systems that are overall high Reliability requirements, but due to the complicated nationwide structure and the resulting high number of components in the system quickly very high costs let arise and thus become uneconomical.

Provided that those to be fulfilled by the automation system Reliability requirements vary locally and Real-time properties only required for certain subsystems only a data transport system with one flexibly adaptable structure especially with large technical Enable investments to be economical.

The invention specified in the claim is based on the problem a flexibly different requirements in the area reliability and transmission speed (real-time properties) customizable data transport system as the basis for to design an industrial automation system.

The advantages achieved with the invention are in particular in that instead of a complicated one, made up of many components existing area-wide structure of rigidly coupled Ring systems now a comparatively simple, flexibly adaptable Structure is realized within which the actually existing requirements in the technical system with regard to Reliability and transmission speed through special Substructures are met.

This object is achieved in that for the connection structure of the data transport system as a whole meshed structure is permitted. The participants of this Data transport system, designed as intelligent functional units (Processing nodes) each with up to four independent  Connections for transmission lines enable the construction of exactly the requirements in the area of reliability and substructures corresponding to the transmission speed.

The following are permitted as substructures of the data transport system:

• - point-to-point connections of individual participants,
• - bus and tree-shaped structures,
• unidirectional and bidirectional ring structures,
• - Combinations of all the structures mentioned, supplemented by additional redundant transmission lines.

The complexity of these substructures is limited by the number of the connections provided for each participant for Transmission lines. Each processing node can have at least one and a maximum of four lines of data with other participants change.

All substructures then form the data transport system.

For the first time, comprehensive data transport systems can be realized from an economic point of view, which locally meet at least the same reliability and real-time requirements as an overall bidirectional ring structure ( Figure 1.1).

The actual connection structure may vary depending on the actual requirements can be varied:

• - Are for data exchange between two functional units to meet high reliability requirements redundant structures provided.
• - Real time properties are through direct connections or through parallel transmission paths on which the data volume is distributed, realized. Redundant connections are made in the trouble-free case also used for data transmission.

An optical fiber (LWL) is used as the transmission medium. Starting from the regularly low number at the field level Distances (100 m) can preferably be used with plastic fiber optic cables will.

Are all the requirements placed on the automation system known, so substructures with computer-aided methods optimized. Sufficiently powerful processing nodes provided that the intelligence distributed in the data transport system also a dynamic, based on failures and failures Ensure subsystem responsive optimization.

At the core of the data transport system are intelligent processing nodes,  the data from the automation system Detect sensors and control actuators or the interface industrial fieldbus systems:

Each processing node is made up of standardized components, the overall a mutually monitoring multi-computer structure form, built. Every computer is a powerful one Microcontroller module constructed, only executable Minimal system that uses exactly one interface to the Data transport system has. This calculator, hereinafter referred to as Processor module called, provides the required in large numbers Standard building block of known reliability that the Basis for the reliability calculation of the substructures forms.

Due to the modular structure, each processing node can do this the requirements of one to four processor modules being constructed.

The demand for the relocation of hardware functions in the software to increase the flexibility of the overall system, leads to special software architectures: starting from one standardized, permanently stored in each processing node The bootstrapping routine is the additional software required downloaded via the data transport system.

The software architecture takes into account that the provision of reliability parameters for software systems not is possible.

Today software is already considered reliable, when the time from fixing one error to the next is still accepted as tolerable or errors that have occurred Restrict function little.

To the software used at all when considering the To consider the overall reliability of a technical system the unchangeable portion of the software must be as low as be kept possible. This part must then be reliable P (B, t) = 1 are included in the calculation. This requirement can only do simple, as diversified as possible Load routines that then meet the required section Load from the software system as required (bootstrap loader). In this software that can be changed at any time is at least central controlled error correction possible.  

2. Structure of the data transport system

The data transport system is made up of processing nodes, that as part of a flexibly structured connection structure exchange data with each other decentrally.

The actuation of the actuators and the data acquisition from the sensors takes place via these processing nodes, which do this spatially are closely linked to the technical system. Here too Already, if necessary, the preparation of the raw data recorded:

• - characteristic curves of sensors are linearized,
• - the influence of disturbance variables is minimized,
• - Compliance with specified limit values is monitored and
• - statistical values are calculated.

The number of data to be transferred to another participant is minimized by these measures. This directly on the sensor intelligent data preprocessing thus relieves the data transport system and makes it easier to implement Control systems already at the level of a single processing node.

Each processing node is also part of the data transport system. Up to four independent connections for data transmission lines form the basis for a nationwide data transport system that can be flexibly structured within wide limits:
Starting from a simple point-to-point connection of two individual participants, the prerequisites for an almost arbitrary combination of bus, ring and partially meshed structures are given. The switching control is also carried out decentrally via the processing nodes.

The computing power required in a special processing node is oriented on the one hand to that for data preprocessing required capacity and on the other hand at the Mediation control complexity.

The required multi-computer structure offers the possibility here distribute different requirements on individual computers, or the actual number of computers in the processing node to determine accordingly.

The processing node is made up of at least one and a maximum of four computers, the processor modules. Every processor module is a built around a microcontroller, for standalone minimal system with exactly one interface  to the data transport system, designed as an optical fiber connection.

The processor modules ( Figure 2.1), which are linked locally in a processing node and form a non-reactive basis, form the essential basis for solving the apparent contradiction between the highly flexible design of the system structure and the requirement to build it from standardized components of known reliability:
Each processing node now consists of

• - A component made up of one to four processor modules, hereinafter referred to as the central module. In addition to the number of processor modules that meet the requirements, this contains all the components that are always required for communication and control on a common carrier card. The processor modules initially contain only a minimum of software:
  The bootloader. The actual function of individual processor modules and thus that of the entire central module is only determined by additional operating software that is downloaded via the data transport system.
• - The variable variable that is usually to be added to the central module Contains (interface), based on that of the Processor modules provided input / output lines, all components necessary for electrical and mechanical adjustment. The interface identifies itself via a characteristic data record automatically opposite the central module, in which then the special operating software is downloaded.

The requirement that the automation system as much as possible with standardized components to be manufactured in large quantities Known reliability can build up for Data transport system can already be met. In this area In terms of reliability, only the processor modules that Data transmission lines and those for switching control necessary software to consider.

The flexible structure of the data transport system forms the basis corresponding to the different requirements Automation system:

1. For the overall system, as well as for any extracts from it, can determine quantitative reliability parameters will. This means that redundancy can only be provided where it is needed is actually required and does not necessarily always have to the entire system can be transferred.

In a data transport system to which overall only low reliability requirements are local  to flexibly implement limited "islands of high reliability".

2. According to the requirements for the transmission speed (Real-time property) can use parallel transmission paths or, if extremely short reaction times are required, also direct point-to-point connections are provided. Redundant transmission channels are also in the error-free case usable for data transmission.

According to the locally different in the automation system Modeling is now possible, which, corresponding to that for structuring transputer networks introduced mathematical procedures, the optimization of the entire System structure enables. Basically, it can be assumed that this optimization, since quantitative parameters for describing the components of the Systems are available with computer-aided procedures too is to be realized.

In contrast to solutions from the area of microsystem technology ( Figure 2.2), which integrate parts from the fields of sensors, actuators, integrated circuits, micromechanics, optoelectronics and assembly / connection technology into a system tailored to special applications / REIC89 /, the processing node can be adapted to a multitude of different tasks using a hardware structure which is standardized, but still flexible, using remote-downloadable software.

Control functions, the provision of interfaces commercial industrial automation systems and a A large number of simple interface circuits are essential for this Requirement. With processor modules that are self-contained and capable of running alone Represent microcontroller systems with high computing power, can the dynamic behavior of standardized interfaces be replicated.

The hardware structure shown enables, regardless of already planned fulfillment of different reliability requirements, also a completely new approach to that Organization, construction and operation of decentralized automation systems:

• - Each new processing node identifies itself and its interface, as soon as it is integrated in the data transport system to be set up step by step, in relation to a control station contained somewhere in the system. The software required for this is included in the bootstrap loader. The control station initializes the processing node on the basis of this data, ie the subscriber address is determined and the required operating software is downloaded.
  Finally, the entire data transport system that has been set up up to this point is reconfigured, in which each subscriber takes the new processing node and the associated data lines into account in its switching control.

Assuming a sufficiently powerful switching control, can do so at any time

• - new participants are added.
• - Processing node a new interface with changed Get function.
• - And new data lines the structure of the data transport system to change.

The downloadable software enables the variation of all functional elements within a processing node. As part of an automatic reconfiguration after failure / removal of a Tasks can be relocated or changed. If sensors / actuators are replaced, this will solve in any case automatically new identification the adaptation of the Operating software from e.g. B. to take into account a changed Adjustment range.

2.1 The processing node

Each processing node consists of the central module, made up of one to four processor modules on a common carrier card, and the interface ( Figure 2.3)

The number of processor modules contained in a processing node initially depends only on the number of required Connections for data transmission lines. Every processor module has exactly one connection.

The internal data exchange of all in one processing node summarized processor modules takes place via a local, non-reactive Computer coupling. All free input / output lines of the microcontroller Processor modules are collected on the carrier card and in a system-specific interface (transfer point) for provided the interface.

The carrier card mechanically accommodates up to four processor modules. It contains a power supply unit used by all modules (voltage monitoring and a backup battery are part of the processor module), a real-time clock and the components required for computer coupling. A special version enables the installation of a processing node in an AT-compatible industrial computer. In this case, the number of processor modules is reduced to three:
The fourth module is emulated by the industrial computer.

The function of the processing node is only enabled by the the data transport system downloaded operating software. Before the initialization, which is also carried out in this way of a new node are only elementary in a bootloader Routines for checking your own hardware (self-test) and a simple attendant control saved. This software part is not taken into account in the reliability calculation.

The entire processing node is supplied with power via the one built on the carrier card of the central module Power adapter. The demand for an overall redundant power supply is the own existing in each processor module 5 volt regulation with voltage monitoring and backup battery fulfilled.

2.1.1 Processor module

The processor module required in large numbers provides the Basis for the to be built in each processing node mutually function-monitoring multi-computer structure. For this purpose, two to four modules are feedback-free computer coupling and can thus receive data and exchange status information.

In each processor module, a microcontroller is added Components complements that one from the other modules Operation is guaranteed.

For each processor module, this is at least the following scope to provide:

• - Microcontroller with serial and parallel input / output lines. Most commercially available building blocks already contain these functional parts, so that additional hardware is not required.
• - Own voltage control with monitoring module and backup battery.
• - Components for internal address decoding.
• - Random access memory. Each module requires at least one non-volatile memory for the bootstrap loader and another, as large as possible area for the operating program and for the temporary storage of data. Modules are expediently used for both tasks, which in any case guarantee data retention even after the operating voltage fails: EPROM, EEPROM or battery-backed CMOS RAM modules.
  The range of commercially available microcontrollers ranges from modules without memory to integrated combinations of ROM and RAM modules, with the non-volatile memory in some cases already having to be mask-programmed by the manufacturer.
• - Driver blocks for coupling the processor module to the Data transport system. For connecting the plastic fiber optic cables separate transmit / receive modules are to be provided in addition to the optoelectric component, expediently also the interface adaptation required for the microcontroller or contain the driver stage.

Each processor module thus provides a self-contained, functional unit that has its own interface to the data transport system and with an independent Power supply works. Additional I / O lines become the internal computer link and provided to build the interface to the interface.

The reliability parameters of this module thus form a basis for the reliability calculation of the overall system.

The mechanical structure of the processor module is similar to that of a multi-pole integrated circuit in a DIL housing: All components are mounted on a small, rectangular circuit board that provides all the connections required for the carrier card on two pin strips arranged on the long sides ( Figure 2.4).

The entire processor module can be miniaturized accordingly Assembled like an integrated circuit be inserted into a socket on the carrier card. The connection for the optical fiber takes place on one of the two Narrow sides.

The complete circuit documentation for the processor module are in the appendix.

2.1.1.1 microcontroller

There is a highly integrated microcontroller module for the processor module high computing power required. The use of today still widespread designs based on an 8-bit processor (HD64 180, SAB80C535 and others) is forbidden.

To enable sufficiently short reaction times, is as In any case, the core is a module with an internal processing capacity of at least 16 bits: For use  comes a microcontroller from the HPC family (HPC = High Performance microController. According to: National Semiconductor Microcontrollers Databook, 1988) from National Semiconductor. These inexpensive 16-bit CMOS controllers offer high computing power and a variety of different complex input / output structures in one block.

National Semiconductor's HPC microcontroller family

The microcontrollers from the 16-bit HPC family also help a z. A clock frequency currently limited to 30 MHz (40 MHz version expected to be available in early 1993) from 134 ns. With fast, often coded in one byte Commands that trigger complex functions is a very effective one Program code possible.

The most important data at a glance:

• - 16-bit CMOS microcontroller
• - Clock frequency up to 30 MHz
• - Fast one-byte commands
• - 16 × 16 bit multiplication, 32/16 bit division commands
• - 8 interrupt sources
• - Watchdog
• - 16-bit timer
• - Up to 52 freely configurable I / O lines
• - Up to 8 KB mask-programmed ROM on the chip (execution with EEPROM has been announced)
• - Up to 256 bytes of RAM on the chip
• - Serial MICROWIRE / PLUS interface
• - Wide range of peripherals integrated depending on the controller type:
  + DMA
  + HDLC interface
  + A / D converter
  + additional storage
  + fast SRAM
• - Permissible operating voltage 3. . . 5.5 volts
• - current consumption:
  in operation: max. 60 mA (VCC = 5.5 V, f = 30 MHz)
  IDLE mode: 3 mA
• - MTBF <0.3 _* 10³ h

The microcontroller from the HPC family always contains one central core (core CPU), around which one depending on the controller type different periphery is arranged.

The core, based on a Von Neumann architecture, contains a total of seven functional elements:

• 1. Arithmetic Logic Unit (ALU)
• 2. 6 16 bit registers
• 3. 8 interrupt channels
• 4. 3 timers
• 5. Sequence control
• 6. Watchdog
• 7. MICROWIRE / PLUS interface.

All internal data lines, the registers, timers and the ALU work with a word length of 16 bits. This allows 64 kbytes external memory can be addressed. The external data bus can designed with 8 or 16 bit word length depending on requirements will.

The microcontroller used in the processor module HPC46 003 (Figure 2.5) contains no internal ROM. This means that almost the entire address space is available for external storage.

The peripherals contained in the HPC46 003 include:

• - a freely programmable serial interface (UART),
• - 4 additional TIMERS
• - 4 "Interrupt Capture" registers
• - 52 freely configurable I / O lines
• - 256 bytes of RAM

With part of the 52 I / O lines, which have a secondary function be configured as address, data and control lines the control of the external memory is realized. The address space of a total of 64 kbytes is divided in the processor module so that 32 KB RAM, 16 KB EPROM (EEPROM) and several freely available Blocks with 4 kByte each are available. The external Data bus is operated with a word length of 8 bits to enable the use of standard components.

Figure 2.6 shows the resulting block diagram for a processor module:

• - The external data bus is connected via the input / output lines from Port A and parts of port B realized. Because the data and the Addresses A0. . . A7 must be multiplexed, a buffer (Latch) can be provided.
• - Redundant power supply (PSU). Each module has its own backup battery, which either allows continued operation for a limited time after the power supply fails or at least maintains the current database.
  A special monitoring circuit ensures, if necessary, the gradual shutdown and restarting of the processor module.
• - The address decoding (SELECT) generates control signals for the internal and external control of memory modules. Each Processor module has 16 kByte EPROM (EEPROM) and 32 kByte battery-backed CMOS RAM.
• - The interface to the data transport system (LWL) with the Send / receive modules and the plug connection.

All free input / output lines of the microcontroller that Control signals, as well as address and data lines are brought out and are available on the carrier card.

2.1.1.2 Voltage control with monitoring module and Backup battery

The processor module comes with an unregulated DC voltage operated by approx. 9 volts (current consumption max. 220 mA) (max .: 17.5 V). The operating voltage drops off, the CMOS-RAM is buffered by a battery.

The integrated components IC8 and IC9 form the core of the power supply.

Voltage regulator 7805 (IC8) generates the operating voltage of +5 volts. The "Micro Manager Chip" (Dallas Semidonductor Product Data Book, 1990-1991) DS1236-5 (IC9) monitors the Operating voltage and derives control signals for the processor from:

• - If the operating voltage is outside the specified tolerance of ± 5%, the processor is stopped. A non-maskable interrupt request (NMI) is generated in good time, which announces the voltage drop (power fail).
  The data retention in the CMOS-RAM is ensured by a buffer battery (3 volts).
• - The processor is clogged when the operating voltage is switched on and started as soon as +5 V are reached. The manual Resetting is possible at any time.

The DS1236-5 also includes a time monitoring (Watching Timer Function) that always generates a reset signal when the processor is not within max. A predetermined trigger signal is triggered 400 ms Has.

This time monitoring is not wired in the processor module.  

2.1.1.3 Components for internal address decoding

The microcontroller HPC46 003 (IC1) is connected to an external Address space of 64 kB, organized in 8-bit words, operated.

All address and data lines are multiplexed over the Port A output: The address lines A8-A15 and the data lines D0-D7 are wired directly. A0-A7 are at the exit of the provided via buffer 74LS373 (IC4).

The address and data lines are supplemented by those from the port B generated control signals for write and read accesses, for control related to memory chips and, with the exception of A11-A15, provided for the carrier card.

I / O lines from port A and port I have a dual function also the control signals for two serial interfaces Available.

MICROWIRE / PLUS, some interrupt lines and free port lines are handed over to the carrier card. I0 and I7 will be used by the bootstrap loader to code the module number (this 2-bit card number (0... 3) is used to identify a processor module within a multi-computer structure formed from up to four cards).

With the decoder built from 74LS139 (IC5) and 74LS08 (IC6) are within the address space of 64 kB control signals (chip Select) for a total of six blocks:

CSHPC: 0000-0FFF (reserved)
CSUHR: 1000-1FFF (real time clock)
CSKL1: 2000-2FFF (free)
CSKL2: 3000-3FFF (free)
CSRAM: 4000-BFFF (32 kB RAM)
CSROM: C000-FFFF (16 kB EPROM / EEPROM).

CSUHR, CSKL1 and CSKL2 are available for expansion purposes. Additional memory modules with up to up to 4 kB. With CSUHR the first processor module (module number 0) controls the Access to the real-time clock of the carrier card.

2.1.1.4 Memory blocks

Each processor module has its own memory chips a word length of 8 bits.

The 16 kbyte EPROM / EEPROM contains up to the initialization of the Module only the bootloader. The operating program is carried out via the  Data transport system downloaded and stored in EEPROM or RAM. The EPROM / EEPROM is the only socketed component of the processor module.

The battery-buffered read / write memory for data and parts the operating program has a size of 32 kByte.

The 32 kB CMOS RAM 62 256 (IC2) is via CSRAM, the 16 kB EPROM 27C128 (IC3) selected via CSROM.

The access time of the memory modules must not exceed 150 ns.

2.1.1.5 Optical fiber connection

The serial data transmission takes place via a plastic fiber optic system from the HFBR-0501 series from Hewlett Packard ( Fig. 2.8).

The full interface is provided by the 75452N driver (IC10) and the transmit / receive modules HFBR-1522 (IC12) and HFBR-2522 (IC11) formed. IC11 and IC12 also contain the mechanical part of the connector (socket) for the finished Assembled duplex fiber optic cables.

This is a reliable, inexpensive transmission medium available that the basis for high transmission speeds forms:

• - transfer speed up to 5 MBd,
• - Transmitter / receiver module TTL / CMOS compatible,
• - length of the optical fiber up to 65 m (1 MBd),
• - MTBF <3 _* 10⁶ h.

The connection cables with one (Simplex) or two (Duplex) Optical fibers, starting from material by the meter, can be assembled on site with simple tools.

2.1.2 Carrier card

The carrier card takes one to four processor modules in sockets mechanically on. It contains:

• - All components required for computer coupling,  
• - the power supply for all modules,
• - A real time clock in the address space of the processor module 0 and
• - The transfer point to the interface as a multi-pin connector.

The processor number 0. . . 3 will have appropriate wiring of the frames set automatically. A hardwired For this purpose, 2-bit information is sent from the processor module via port lines (I0, I7) evaluated.

A special version enables the installation of a processing node into an AT-compatible industrial computer. In this In this case, the number of processor modules is reduced to three: That fourth module is emulated by the industrial computer.

2.1.2.1 Non-reactive computer coupling

The multi-computer structure of the central module is based on a non-reactive, own data transmission system coupled. All Processor modules can use it without going through the data transport system Exchange data and monitor each other.

Commercial microcontrollers offer here through the integrated I / O interfaces various possibilities that essentially by the achievable transmission speed differentiate.

In order to meet the requirement for non-retroactivity, the Failure (including bus errors) of a module has no effect have the other modules of the module. Simple serial transmission systems with bus structure are therefore excluded as well a shared one set up in the address space of all computers Random access memory.

In principle, the computer connection can be made via:

• - serial interfaces
• - parallel interfaces and
• - Special, shared memory (multiport RAM).

Computer coupling with serial / parallel interfaces

The coupling via serial or parallel interfaces requires since bus-shaped structures are excluded, always special ones Point-to-point connections as part of bidirectional Ring systems or a multi-channel bus system, as is the case in research-oriented System FUTURE was realized.  

Common to all of the processes is the large number required serial or parallel interfaces. Apart from the wiring effort is always an extensive additional Hardware required because interfaces don't count in this number more will be provided by the microcontrollers or then fully utilize the hardware.

A feedback-free computer coupling via serial or parallel Interfaces are therefore from an economic point of view not justifiable and is in the processing node not provided.

Computer coupling with multiport RAM

Shared memory can be used with a multiport RAM set up for up to four computers. The data exchange takes place over a serial or parallel interface (port) over the memory contained in the block. The status Access organized so that simultaneous write access to a memory cell are excluded. In parallel Access to the lake is generally permitted. The comparison of data and the evaluation of status information can be carried out optimally because this data in one shared memory / FREN87 /. Because the comparative Computers that can read data directly can transmit and Program times are minimized.

There are very different building blocks available on the market, Two of which are presented below:

The "High-Speed 2 k × 8 Four-Port Static RAM" IDT7052L (Integrated Device Technology Inc., Advance Information 1989) couples up to four computers via a shared memory of 2 Kbytes ( Figure 2.9).

The block has four parallel interfaces with Address, data and control lines. In the address space of a computer it behaves like a read / write memory. For access control you only need to evaluate an additional BUSY signal. In detail:

• - Fast memory chip: access time less than 50 ns.
• - Every computer can access every memory cell. Simultaneously Write access is prevented via a BUSY signal.
• - Current consumption up to 400 mA (VCC = 5 V). Will the block not selected (-CE₁.. -CE₄), is automatically in one "Standby mode" switched (ICC = 1.5 mA).
• - Housing: 108 p PGA or 132 p Quad Platpack.  
• - High price: over DM 200 per module.

This multiport RAM represents a very fast and as it is externally behaves like any read / write memory, also represent a simple method for computer coupling. The high Current consumption of the module and above all economic Considerations do not allow use in the processing node to.

The inexpensive "Quad Port Serial RAM Chip" DS2015 from Dallas Semiconductor (Dallas Semiconductor Product Data Book, 1990-1991) ( Fig. 2.10) also couples several computers via a shared memory:

• - Connection option for up to four processor modules.
• - The data transmission is serial via a 4-wire interface. Maximum clock frequency 4 MHz.
• - Each computer can read in its private memory (64-bit) and write. The three remaining memories can only be read will.
• - Simultaneous read access to all ports via one Storage cell is possible.
• - If data is waiting in its own memory, the "Message waiting "(MSG).
• - Low current consumption: 6 mA (VCC = 5 V).
• - Housing: 18 p DIL.
• - Unit price under 10 DM.

The required exchange of status information within the Multi-computer structure can be realized with this inexpensive module. This stands, despite the comparatively very small private storage area and the transport delay serial data transmission, a sufficiently powerful Module for computer coupling available.

The feedback-free computer coupling is on the carrier card realized with a multiport RAM DS2015. Via the four-wire interface can all four processor modules in their private Write memory and read data from all memory areas.

The one intended for installation in an AT-compatible industrial computer Carrier card couples only three processor modules via the Multiport RAM. Data exchange takes place via the fourth interface with the industrial computer.  

2.1.2.2 Power supply

The operating voltage for all processor modules is indicated by a Power supply provided with an output voltage of 9 volts. The output current is max. 2 amps.

The operating voltage is controlled by a 78S09 controller stabilized.

2.1.2.3 Real time clock

For synchronization of all processor modules within a processing node is a battery-backed on the carrier card Standard real-time clock module RTC72 421A included. This Module is arranged in the address space of processor module 0 and is selected via CSUHR.

The processor module 0 can thus read data from the real-time clock or write to the block. The date / time information will then via the local computer link to the other processor modules passed on.

2.1.2.4 Transfer point

For each processor module, the free input / output lines, the address lines A0. . . A11, the data lines D0. . . D7 and some control signals collected on the carrier card and on the connector of the transfer point for the interface.

All processor modules and the transfer point are on the carrier card additionally via the serial interface MICROWIRE / PLUS connected with each other.

2.2 Interface

As a link between the standardized central module and the technical process is a task-specific I / O system provided that in its structure from the automation task is shaped.

At hardware level, the I / O system provides all for connecting the signals common to automation technology for sensors / actuators ready. The transfer location of these signals is referred to as the terminal block.

Each interface has a key data record that is in one serial EEPROM (256 × 16-bit) is stored. The data can from every processor module via the MICROWIRE / PLUS interface to be read.

The interface identifies itself with this key data record  Processing node, which is then the special operating software via the data transport system.

An interface for RS-485 with an operating program is initially planned for the DIN measurement bus.

2.3 The data transport system

Data is transported between the processing nodes via a part that can be freely structured within the specified limits meshed data transport system based on plastic optical fibers. For this purpose, each processing node has up to four connections for transmission lines.

Every node within the data transport system is tracked its initialization uniquely through its 16-bit address identified. The initialization as well as the transfer of the Operating software is always carried out via the data transport system. The data transport is controlled via a packet switch. Data will, according to the given requirement and Length of the respective transmission line, with up to 5 Mbit / s transfer. An efficient data backup procedure forms the basis for a constant, dynamic optimization of the transmission speed in response to detected transmission errors.

2.3.1 Operator control

For all processing nodes integrated in the automation system, the data transport system as a whole presents itself as a storage-mediating structure, into which data is delivered in packets in the form of telegrams ( Figure 2.11).

Everyone has access to this partially meshed packet switching network Processing node via a unique address. Data are based on the procedure standardized in DIN 19 245 T1 transmitted in data telegrams, the address length is expediently increased so that even in large systems there are still unique addresses to be assigned.

The time it takes for this data transport system to deliver the data transferred from a processing node to the addressee, unlike with the bus or ring system (token ring), cannot be clearly determined for each participant ( Figure 2.12).

To define defined reaction times for selected connections and above all real time properties at least locally To allow limited, the data telegrams are also around Add parameters to make certain data a priority in the data transport system  give. In conjunction with these requirements flexibly adaptable system structure, powerful Processing nodes and a fast transmission medium (Optical fibers) are thus, at least locally limited, predetermined ones Adhere to response times.

Figure 2.12 shows once again that the processing time in all components involved in the data transport must be minimized in order to keep the transport delay as small as possible.

On the theoretical basics of memory-switching systems should not be discussed further here, especially this topic is already very detailed in the literature found (SCHN82, FRAN86, KAUF87 and others).

Within the following considerations for the realization of the partially meshed data transport systems are said to be the different Requirements for different substructures necessary switching controls are shown.

2.3.2 Connection structures

Within the approved partially meshed connection structure five different connection types different complexity (substructures) agreed. Detecting the for a processing node or just for a processor module valid substructure, classified by type 1 to type 5, forms an essential basis for the application Switch control:

Type 1: point-to-point connection
Type 2: unidirectional ring
Type 3: bidirectional ring
Type 4: Unidirectional bus
Type 5: Partly meshed. Combinations of types 1 to 4 and additional cross connections are permitted.

A processing node has more than one interface to the data transport system, there are different classifications according to the actual partial structure intended.

A substructure of type 5 is always present if a Nodes with more than two wired connections for data lines or if the classification according to type 1 to 4 is not possible.  

2.3.2.1 Point-to-point connection

The processing node has only one connection to the data transport system ( Figure 2.13). A simple switching control is used for this connection structure (type 1):

• - All data telegrams that use their own address as the destination address are evaluated and, if necessary, acknowledged.
• - Telegrams for foreign nodes are not forwarded.
• - Own telegrams, regardless of the target address, always sent to the neighbors.

2.3.2.2 Unidirectional ring

Each processing node can receive data telegrams from its left neighbor and send data to its right neighbor ( Figure 2.14). Overall, there is a closed ring structure with directional data transmission (type 2).

The following applies to the switching control of any node now:

• - All data telegrams that use their own address as the destination address are evaluated and, if necessary, acknowledged.
• - Every telegram that uses its own address as the sender address contains, must be removed from the ring, since the addressee is not was reached (participant not in the ring; error condition).
• - Telegrams with foreign destination addresses are forwarded.

A data telegram that is the destination address of all processing nodes contains comprehensive group address, circles in the ring. For A data acquisition system will be a snippet of each node assigned to this telegram, which is always updated when the processing node concerned processes the telegram. A selected node provides the data collected in this way then available for further editing.

2.3.2.3 Bidirectional ring

Each processing node has exactly two connections for data transmission lines ( Figure 2.15). Data telegrams can be transmitted to both neighbors or received by both neighbors (type 3).

The same initially applies to switching control Principles as for the unidirectional ring. In addition, too consider:

• - Each processing node maintains a connection table (In the centrally controlled, packet-switching data transport system, each processing node carries a weighted one Connection table (route map) / SCHN82, KAUF87 /), the for a given destination address the selection of the shortest in each case Connection enabled. Running times are minimized.
• - After a line break, the data transport system reconfigured according to type 1 or 2.

2.3.2.4 Unidirectional bus

The unidirectional bus (type 4) synchronizes all processing nodes connected as receivers with a data telegram received at the same time ( Fig. 2.16).

The mechanical structure of this substructure requires special decoupling modules (AM), in each of which a part of the energy transmitted in the plastic optical fiber is decoupled and fed to a processing node ( Figure 2.17).

The following applies to switching control:

• - The node switched as transmitter leads in a special Table of the addresses of all participants ready to receive.
• - Each node evaluates data telegrams that are its own Address.
• - Each node can have a special synchronization character evaluate.
• - Acknowledgments are only generated if the node still has a additional transmission path (type 1, 2, 3 or 5) available stands.

2.3.2.5 Partially meshed structure

Each processing node with more than two wired connections for data lines is part of a substructure type 5.

The switching control is based on one in this case too Connection table. Compared to the bidirectional ring but now up to four different ones for each destination Leading and evaluating connection paths weighted.  

In the selected example ( Figure 2.18), partial structures of type 5 apply to the processing nodes VK1, VK3 and VK4. The switching control of VK2 requires type 3, that of VK5 type 1. In this data transport system, differently complex switching controls are used mixed.

If one or more connections fail, the data transport system reconfigured according to the then valid substructures.

2.3.3 Data transfer 2.3.3.1 Procedure for data backup

In addition to the block backup already carried out in the UART Cross parity increases the risk of undetected transmission errors via an additional software-implemented one Cyclic redundancy check (CRC) procedure minimized.

A 1-byte CRC backup procedure was implemented that simultaneously also a basis for an automatic adjustment of the Forms transmission speed.

2.3.3.2 Single characters

The transfer of single characters represents in the memory switching Data transport system is an exception. Since neither sender destination address are still included, can only be an undirected one Communication between two neighbors in the data transport system respectively.

Individual characters are agreed for:

• - Test pattern: 8-bit, code: 1 B _H.
• - Synchronization characters: 8-bit, code: 2E _H.

Test samples are always sent when in a period no other data transport took place after 50 ms. With this cyclically generated signal is achieved that line breaks be recognized after 50 ms at the latest. The Testing for transmission errors creates the prerequisite for a possible adaptation of the transmission speed at any time.

Synchronization characters are used within a substructure of Type 4 for simultaneous triggering of special functions for all processing nodes switched as receivers.

No other single characters are allowed.  

2.3.3.3 Data telegram

The data is transported in accordance with DIN 19 245 T1 in telegram form ( Figure 2.19). Each data telegram has a sender and a destination address. Each address (16-bit) contains an 8-bit long group and individual part as a prerequisite for "collective telegrams" to all or a selected part of the processing nodes in the data transport system.

The maximum length of a data telegram is 512 characters.

Each telegram also has 8 characters for synchronization prepended.

The function of the data fields within a telegram is in Table 2.1 shown.

The structure of the data transmitted in a telegram is purposeful. The number of dates determines the actual one Telegram length: 12 to 512 bytes, plus 8 in front Sign for synchronization.

The structure and function of those agreed in the telegram format Detailed fields:

SC With the eight SC characters (code: D3 _H ) preceding each data telegram, the current transmission rate is updated by evaluating transmission errors.
If an error condition is met during reception, all permitted transmission rates are switched in succession. If the transmission errors cannot be eliminated, reception is aborted and an error message is generated with the last valid transmission rate.
If the current transmission rate could be recognized and set, it will no longer be varied, at least for the subsequent telegram.
SD start character of the data telegram (code: 68 _H ). The receiving route must have recognized this character after eight SC characters at the latest.
SA sender address (16-bit, 0.. FFFF _H ).
DA destination address (16-bit, 0.. FFFF _H ).

Addresses are always 8-bit long Group and individual address formed:

The permitted range of values for the group address is 01 _H. . FF _H. Within each group there are also individual addresses of 01 _H. . FF _H possible. This can address up to 65025 participants.

All individual addresses in group 00 _H are reserved for special tax tasks:

• - With the target address 0000 _H all participants are addressed.
• - If the address 00FF _H and DT = 00 _H , the data contained in the telegram are taken up by the next new node as initialization.

MN module number (8-bit, 0.. FF _H ). the module number is an extension of the target address. Up to 256 devices can be addressed in one processing node:

• - The module numbers 00 _H. . 03 _H are the addresses of the processor modules
• - With MN 04 _H. . FF _H , up to 252 devices managed via the interface can be directly addressed per processing node.

DT The content of the DT field (8-bit, 0.. FF _H ) identifies the type of data that follows. DT can be a shortcut:

DT = 00 _H This is followed by initialization data for the node with address DA, module MN.
The next new node is initialized with DA = 00FF _H.
= 01 _H, it follows a part of the operating program for the node DA, MN module.
= 02 _H there follows a short command or parameter set for node DA, module MN.
= 13 _H Send parameter set 1 from node DA, module MN to processing node SA.
= 14 _H Send parameter set 2 from node DA, module MN to processing node SA.
= 80 _H This telegram is a short acknowledgment from the recipient to the sender: Data telegram received without errors.
= 81 _H. . . 8F _H This telegram is a short acknowledgment from the recipient to the sender: data telegram received. Error 81 _H. . 8F _H recognized.
FF _H The neighbor in the data transport system requires identification: The first node that receives this telegram sends its parameter set 1 to node SA. The destination address DA is always 00FE _H.
PR priority of this data telegram (8-bit, 0.. FF _H ).
LE Length of this data telegram (1 bit, 0 ... FFFF _H ). The minimum length (shortcut) is 12, the maximum is 512 characters. The eight characters preceding the synchronization are not counted.
D₁. . D _n zero (short command) up to 500 data bytes (8-bit, 0 ... FF _H ).
FC checksum of this data telegram (8-bit, 0 ... FF _H ). FC includes all characters of the telegram. The preceding SC characters are not taken into account.
ED end character of the data telegram. Code: 8E _H.

2.3.3.3.1 Initialization data

1. Initialization of a new participant

A processing node that receives its initialization telegram has received, sends its parameter set 1 as an acknowledgment specified control station.  

2.3.3.3.2 Operating program

3. Examples

The following examples show the actual flexibility of the presented data transport system. Starting from a real one Automation task is shown how the connection structure varies according to different requirements becomes.

Automation task

100 textile machines are operated in a workshop. Each The machine has its own control unit that records the operating data on a V24 interface for further processing.

The operating data of all 100 machines are to be Data transport systems collected and, graphically prepared, on a central control room (LS).

The following are available for setting up the data transport system:

• - Processor modules with:
  MTBF <6.8 _* 10⁵ h and
  average program duration t _P <5 _* 10 ^-7 s
• - transmission lines:
  MTBF <3 _* 10⁶ h and
  Transmission time¹¹) t _Ü <4.3 _* 10 ^-3 s.

The probability of the system operating state P (B, t 1) for t 1 = 1 year is calculated as the reliability parameter. The calculation process is shown in the appendix.
¹¹) The transmission time is calculated for a data telegram with a total length of 8 + 512 characters.

In the examples below, the processing nodes shown as a dashed frame in which one to four processor modules (hatched) are installed. The connecting lines between the processor modules are drawn in as vectors. You specify the direction of transmission.

3.1 Example 1

The operating data of all textile machines should have a ring shape structured, simply structured data transport system be recorded.

Special reliability requirements: none.

Predefined response times:
The control center should update the display every 1-2 s.

The data transport system is structured as a unidirectional ring (type 2), in which a separate processing node (VK1 ... VK100) is set up for each textile machine ( Figure 3.1).

An AT-compatible industrial computer with its own is used as the control center Processing node (LS) used.

The data acquisition takes place via a cyclically circling in the ring Data telegram that updates every processing node. in the This telegram is evaluated in the control center.

The cycle time t _Z for the data telegram results

t _Z = 101 _* (t _P + t _Ü ) = 0.43 s

The control center can evaluate a data telegram every 0.43 s for all 100 textile machines the representation of the operating data To update. The response time is significantly better than required.

The probability of the operating state is calculated

P (B, t₁) = 0.2036

Because in this case no special reliability requirements the simple connection structure shown can are used. It is accepted that each Interruption of a transmission line always leads to a system failure leads.

3.2 Example 2

The data transport system is now locally different Adjust requirements:

Special reliability requirements:
P (B, t₁) <0.7 for those from LS, VK1. . VK3 and VK98. . VK100 formed substructure.
Predefined response times:
For connection VK3 to VK98 maximum 100 ms. For LS again 1-2 s for overall presentation.

The data transport system is in turn structured as unidirectional Ring (type 2), with the following requirements now to take into account:

• - The reliability requirement for the specified substructure is only to be fulfilled if no more than 22 in total Processing nodes and transmission lines are included. An additional cross connection is therefore required.
• - At the given reaction time, a maximum of 22 knots is allowed with their transmission lines at the data exchange between VK3 and VK98 are involved.

Based on the given structure, both requirements can already be met by an additional, bidirectional connection between VK3 and VK98 ( Figure 3.2).

Both processing nodes receive a second processor module, with which a point-to-point connection (type 1) is then established becomes.

The operating data of all textile machines can continue with a cycle time of 0.43 s. For those from the Node LS, VK1. . VK3 and VK98. . VK100 formed substructure applies:

Data transmission in approx. 30 ms and
P (B, t₁) = 0.8955.

The data transport between VK3 and VK98 takes place in maximum 9 ms.

The substructure thus fulfills significantly higher requirements than the rest of the data transport system. Locally different Requirements are met.

3.2 Example 3

Here, too, the data transport system has different requirements are enough:

Special reliability requirements:
P (B, t₁) <0.85 for the substructure formed from LS and VK4.
Predefined response times:
For connection LS to VK1. . VK4 and for VK98 to VK100 maximum 25 ms. For LS again 1-2 s for overall presentation.

The data transport system is in turn structured as unidirectional Ring (type 2), with the following requirements now  to take into account:

• - The reliability requirement for the specified substructure is only to be fulfilled if a total of no more than 10 Processing nodes and transmission lines are included.
• - At the given reaction time, a maximum of 5 knots are allowed your transmission lines at the data exchange between the specified Participants.

Are the data lines between LS and VK1 within the proposed connection structure. . VK4 bidirectional, the required response times must already be observed here. An additional bidirectional point-to-point connection is required for data exchange between VK98 and VK100 ( Figure 3.3).

For each of the seven processing nodes specified, one is used second processor module required.

The operating data of all textile machines are also in this Case recorded with a cycle time of 0.43 s. For those from the Node LS, VK1. . VK4 substructure applies:

Data transmission in max. 25 ms (LS ↔ VK4) and P (B, t₁) = 0.9162

The data transport between VK98 and VK100 takes place in maximum 9 ms.

In this example, too, substructures essentially fulfill higher requirements than the rest of the data transport system. Local different requirements are met without additional Cross connections are required.  

4. Appendix 4.1 Mathematical description of reliability

The considered non-repairable systems can be described by a two-stage homogeneous Markoff process ( Figure 4.1) with the two states operation (B) and failure (A):

State B: Operating state between commissioning and failure or shutdown due to faults and
State A: Inoperative state after failure.

These complementary states are called system state pairs below referred to, where appropriate for large systems can be to set multiple system state pairs.

A failure causes the transition from B to A to take place. This transition is characterized by the failure rate $, which is the mean operating time from start-up to failure MTBF (Mean Time Between Failures) over the mean operating time (T (B). For the non-repairable components under consideration, this is equal to the average lifespan, in in literature as MTTFF (Mean Time To First Failure) T _{(B) is} calculated. There is no transition from state A to state B.

In technical systems, the failure rate often takes a course over time, which because of its characteristic shape is referred to as the "bathtub curve" ( Fig. 4.2). The failure rate initially drops from an increased initial value (early failures), then remains almost constant for a relatively long time and finally increases again at the end of the system's service life (wear failures).

If you limit your modeling to the middle phase with a constant, time-independent failure rate there is an exponential distribution of survival.

This gives you the following time histories for the failure rate λ, probability of survival P (B, t) and probability of failure P (A, t):

The assumption of constant failure rates is reliable, since only random ones Failures of aging-free components considered will. Deterministic or systematic failures due to of wear, material fatigue, overload, incorrect handling, external influences etc. are not included. In the considered Systems are therefore only mutually (statistically) consider independent components.

The workability of a system now depends in more or less complicated way depending on whether subsystems are still without Work or whether they fail individually or in groups. A distinction must be made between subsystems whose failure always occurs cause the system failure and groups of subsystems, all of which have to fail to lead to total failure. There are a number of to illustrate these dependencies graphical representations (ROSE81, KOCH84 and others) showing the functional structure as a combination of series and parallel connections play.

In the state block diagrams used here (often referred to in the literature as a (reliability) block diagram or simply as a reliability diagram), the states of subsystems (hereinafter also referred to as components) are identified by state block systems ( Figure 4.3) and corresponding to the logical link ( Figure 4.4) interconnected.

In this work, only status Block diagrams used in operational logic representation, d. H. the structures are only formed from operating states.

There is always a logical series structure regarding the operation then, if only the operation of all components to operate the Systems leads. Apply to stochastically independent components following relationships:

Probability of the system operating state

P (B _S ) + P (B₁) P (B₂). . . P (B _n ) (4-4)

Probability of the system failure state

P (A _S ) + 1 - P (B _S ) (4-5)

Average failure-free system operating time

There is a logical parallel structure with regard to the operation always before if the operation of at least one component for Operation of the system leads.

This results in the probability of the system operating state for a parallel structure of n components to:

P (B _S ) + P (B₁) v P (B₂) v. . . v P (B _n ) (4-7)

For stochastically independent components, the calculation can be made in in this case using a recursive calculation rule (ROSE81):

P₁ + P _i-1 + (P (B₁) - P _i-1 P (B₁) (4-8)

With P₁ = P (B₁)
and for i = 2, 3, 4,. . ., n

the probability (P (B _S ) for the system operating state follows with P _n . (4-5) applies accordingly.

With (4-4) to (4-8) all arrangements can be calculated that into a hierarchical sequence of series and parallel structures can be broken down.

4.2 Reliability of automation systems

The automation system is a technical system that in is able to perform a technical process as specified Setpoints to be managed automatically by certain state variables be detected by measuring devices (sensors) and that according to the control specifications and control algorithms with the help of control devices (Actuators) in turn affect certain state variables (ENDL88).

In contrast to this definition, sensors and Actuators formed interface to the process in this Work not considered. The IT aspect is of interest here of the automation system, i.e. process data processing.

The reliability of an automation system is shown in one Reliability analysis is determined for which it is both qualitative as well as quantitative assessment criteria.

The qualitative assessment of reliability includes e.g. B. Criteria such as the use of tried and tested components, good ones Documentation and extensive diagnostic tools (Qualitative evaluation criteria (quality conditions) for the integrated software systems are included in DIN 66 285, among others) (KOCH84).  

The quantitative assessment is based on the presented probabilistic approach. That is the systematic Processing a large number of failure combinations possible, the course of the reliability analysis being independent always following from the actually used procedure Process oriented (PROT87):

• a) Definition of meaningful default criteria (qualitative problem),
• b) Specification of numerical values for these parameters as boundary conditions to be observed (quantitative problem),
• c) Application of these parameters to specific system architectures with the help of the mathematical model (analytical problem).

As a criterion for evaluating the reliability of an automation system can be sensitivity or vulnerability against failure or malfunction of subsystems or system functions (KOHL87).  

4.3 Bibliography

Books

(FRAN86) Frank, R .: Computer Networks and Data Communication.
Berlin, Heidelberg, New York, Tokyo: Springer 1986.
(KAUF87) Kauffels, F.-J .: Computer network system architectures and data communication. Computer Science Series; Volume 54.
Mannheim, Vienna, Zurich: Bibliographical Institute 1987.
(KOCH84) Kochs, H.-D .: Reliability of electrical engineering systems.
Berlin, Heidelberg, New York, Tokyo: Springer 1984.
(SCHN82) Schnupp, P .: Computer networks - design and implementation.
Berlin, New York: de Gruyter 1982.

Publications, scientific reports and manuscripts to meetings and seminars

(ENDL89) Endl, H .: Process coupling in fault-tolerant systems.
Dissertation Technical University of Munich 1989.
(KRGI91) Kriesel, W .; Gibas, P .: Generation change in automation systems: Orientations for future development.
Automation technology practice, No. 1, 1991.

Standards and recommendations

DIN 19 239: measuring, controlling, regulating; Control technology; Programmable logic controllers; Programming.
DIN standard, May 1983.
DIN 19 244: Telecontrol devices and telecontrol systems.
Part 10: Telegram formats.
DIN draft, March 1988.
DIN 19 245: measuring, controlling, regulating; PROFIBUS.
Part 1; Transmission technology, bus access and transmission protocol, service interface to the application layer, management.
DIN draft, August 1990.
Part 2: Communication model, services for the application, protocol, syntax, coding, interface to layer 2, management.
DIN draft, August 1990.
DIN 31 000: General principles for the safe design of technical products.
DIN standard, March 1979.
DIN 40 041: reliability; Terms.
DIN standard, December 1990.
DIN 40 700: circuit symbol.
Part 23: Clocks and electrical time devices.
DIN standard, June 1979.
Part 24: Assemblies for precision engineering devices, especially clocks.
DIN standard, June 1976.
DIN 40 719: circuit documents.
Part 6: Rules and graphic symbols for function plans.
DIN standard, March 1977.
DIN 66 259: Electrical properties of the interface cables.
Part 4: Double flow, symmetrical for multipoint connections.
DIN draft, June 1989.
DIN 66 264: Industrial automation.
Part 1: Multi-processor control system for work machines (MPST); Parallel bus.
DIN standard, January 1983.
Part 2: multiprocessor control system for work machines (MPST); Rules for the exchange of information.
DIN standard, August 1988.
DIN 66 285: Information processing; Application software: quality conditions and test regulations.
DIN standard, August 1990.
DIN 66 348: Interfaces and control methods for serial measurement data transmission.
Part 1: start-stop transmission, point-to-point connection.
DIN standard, September 1986.
Part 2: start-stop transmission, 4-wire measurement bus.
DIN standard, September 1989.
DIN V 19 250: measuring, controlling, regulating; Basic safety considerations for MSR protective devices.
DIN pre-standard, January 1989.
NTG 3004: Reliability terms with regard to complex software and hardware.
NTG recommendation 3004; Draft 1982. In: Nachrichtenentechnische Z. 35, 1982.

Table 2.1

Function of the data fields in the data telegram

Claims (1)

Decentrally controlled, highly reliable data transport system, in particular for use in industrial automation technology, characterized in that the connection structure of the data transport system can be flexibly adapted to locally different reliability requirements at any time. Structurally, real-time properties are only provided where they are actually required.
The overall modular structure with standardized components of known reliability, the function of which is essentially determined only by remote-downloadable operating software, enables the resources to be used economically, particularly in the case of nationwide data transport systems.