DE4225154A1 - Chip module - Google Patents

Chip module

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Publication number
DE4225154A1
DE4225154A1 DE4225154A DE4225154A DE4225154A1 DE 4225154 A1 DE4225154 A1 DE 4225154A1 DE 4225154 A DE4225154 A DE 4225154A DE 4225154 A DE4225154 A DE 4225154A DE 4225154 A1 DE4225154 A1 DE 4225154A1
Authority
DE
Germany
Prior art keywords
chip
circuit board
chip module
module according
bond
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE4225154A
Other languages
German (de)
Inventor
Wolfgang Knoblauch
Gisela Jahn
Roland Sander
Ronald Klemm
Dieter Albin
Siegfried Pahl
Dieter Baake
Stephan Perschke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MEYERHOFF DIETER
Original Assignee
MEYERHOFF DIETER
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MEYERHOFF DIETER filed Critical MEYERHOFF DIETER
Priority to DE4225154A priority Critical patent/DE4225154A1/en
Priority to PCT/DE1993/000085 priority patent/WO1994003924A1/en
Priority to CA002141458A priority patent/CA2141458A1/en
Priority to CZ95219A priority patent/CZ21995A3/en
Priority to EP93903146A priority patent/EP0653104A1/en
Priority to SK181-95A priority patent/SK18195A3/en
Priority to JP6504869A priority patent/JPH08501413A/en
Publication of DE4225154A1 publication Critical patent/DE4225154A1/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48233—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a potential ring of the item
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

The aim of the invention is to design a chip module which largely avoids edge shorting of the chip (2). The invention achieves this aim by virtue of the fact that bond islands are disposed on the chip away from the edge, the bond islands being connected by bond leads (4) to conductor tracks (5) on the circuit board (1). The invention concerns a chip module comprising at least one chip, preferably a store or processor, located on a circuit board.

Description

Die Erfindung bezieht sich auf ein Chip-Modul, bei dem mindestens ein Chip, vorzugsweise ein Speicher oder ein Prozessor, auf einer Leiterplatte angeord­ net ist.The invention relates to a chip module, at the at least one chip, preferably a memory or a processor, arranged on a circuit board is not.

Nach dem Stand der Technik sind verschiedene Bau­ formen bekannt, Halbleiterbauelemente auf Leiter­ platten oder in speziellen Gehäuseformen anzuord­ nen. Bei der Anordnung der Chips auf Leiterplatten ist es üblich, daß an den Seitenrändern der Chips Bondinseln angebracht sind, an denen Bonddrähte zur Herstellung der elektrischen Verbindung mit den Leiterbahnen der Leiterplatte angeschlossen werden.According to the state of the art are different construction known form semiconductor devices on conductors plates or to be arranged in special housing shapes nen. When placing the chips on circuit boards it is common that on the side edges of the chips Bonding islands are attached to which bonding wires for Establish the electrical connection with the PCB conductor tracks can be connected.

Den bekannten Bauformen haftet der Nachteil an, daß bei Verwendung von Chips mit Bondinseln außerhalb des Randes beim Bondvorgang ein Kantenschluß an den Rändern des Chips auftreten kann, was zur Funktionsuntüchtigkeit des Moduls führt.The known designs have the disadvantage that when using chips with bond pads outside of the edge during the bonding process  the edges of the chip can occur, resulting in Inoperability of the module leads.

Der Erfindung liegt deshalb die Aufgabe zugrunde, ein Chip-Modul der eingangs genannten Art anzuge­ ben, das weitgehend einen Kantenschluß am Chip vermeidet.The invention is therefore based on the object to suit a chip module of the type mentioned ben that largely an edge closure on the chip avoids.

Erfindungsgemäß gelingt die Lösung der Aufgabe da­ durch, daß sich auf dem Chip außerhalb des Randbe­ reiches Bondinseln (sogenannte Center-point-bond­ pads) befinden, die durch Bonddrähte mit Leiter­ bahnen der Leiterplatte verbunden sind.According to the invention, the problem is solved there through that on the chip outside the Randbe rich bond islands (so-called center-point bond pads) located by bond wires with conductors tracks of the circuit board are connected.

Zweckmäßigerweise wird dabei die Oberfläche in be­ kannter Weise passiviert. Es ist auch möglich, die erfindungsgemäße Anordnung mehrfach auf einer Lei­ terplatte, vorzugsweise in einer Reihe als Mehr­ fach-Chip-Anordnung auszubilden.The surface is expediently in be known passivated. It is also possible that arrangement according to the invention multiple times on a lei terplatte, preferably in a row as more Train chip arrangement.

Eine vorteilhafte Ausgestaltung der Erfindung sieht vor, daß sich in der Leiterplatte mindestens ein Durchbruch oder eine Ausfräsung befindet und daß das Chip versenkt in dem Durchbruch oder der Aus­ fräsung angeordnet ist.An advantageous embodiment of the invention provides before that in the circuit board at least one Breakthrough or a cutout and that the chip sunk in the breakthrough or out milling is arranged.

Eine weitere Ausführung der Erfindung besteht darin, daß auf der Leiterplatte um das Chip Schutz­ streifen, vorzugsweise in Form eines Kunststoff­ rahmens, angeordnet sind. Dabei kann das Chip auch ohne daß sich in der Leiterplatte eine Ausfräsung oder ein Durchbruch befindet, auf die Leiterplatte aufgesetzt werden. Another embodiment of the invention exists in that on the circuit board around the chip protection strip, preferably in the form of a plastic frame, are arranged. The chip can do that too without milling in the circuit board or a breakthrough is on the circuit board be put on.  

Ferner ist es möglich, daß die Bonddrähte bogen­ förmig angeordnet sind.It is also possible for the bond wires to bend are arranged in a shape.

Eine weitere Ausführungsform der Erfindung sieht vor, daß als Bonddrähte Aluminiumdrähte verwendet werden.Another embodiment of the invention provides before that used as bond wires aluminum wires become.

Bei einer vorteilhaften Weiterbildung der Erfindung ist vorgesehen, daß das Chip ein DRAM mit einer Speicherkapazität von 3 Mb oder ein ganzzahliges Vielfaches davon enthält.In an advantageous development of the invention it is provided that the chip is a DRAM with a Storage capacity of 3 Mb or an integer Contains multiples of it.

Ferner ist es möglich, daß das Chip mindesten ein DRAM mit einer Speicherkapazität 4 Mb oder ein ganzzahliges Vielfaches davon enthält, das in glei­ che Bereiche aufgeteilt ist, von denen einige mit der Leiterplatte verbunden sind. Auf diese Weise gelingt es, auch Chips einzusetzen, die ursprüng­ lich für andere Einsatzzwecke vorgesehen waren und beispielsweise aus fertigungstechnischen Gründen nicht die volle Kapazität erreichen.It is also possible that the chip is at least one DRAM with a memory capacity of 4 Mb or one contains integer multiples of it, in the same areas, some with the circuit board are connected. In this way succeeds in using chips that originally were intended for other purposes and for example for manufacturing reasons do not reach full capacity.

Eine zweckmäßige Ausführungsform des erfindungsge­ mäßen Chip-Moduls entsteht dadurch, daß auf dem Chip die PQ- und PD-Signale sowie die PCAS- und CAS-Signale miteinander verbunden sind.An expedient embodiment of the fiction moderate chip module arises from the fact that on the Chip the PQ and PD signals as well as the PCAS and CAS signals are interconnected.

Von besonderem Vorteil bei der Erfindung ist, daß durch die erfindungsgemäße Anordnung der Bonddrähte ein Kantenschluß zwischen Chip und Leiterplatte vermieden wird. A particular advantage of the invention is that by the arrangement of the bond wires according to the invention an edge connection between the chip and the circuit board is avoided.  

Durch die Möglichkeit der Versenkung der Chips in der Leiterplatte ist außerdem ein geringer Platzbe­ darf gewährleistet, wodurch eine große Packungs­ dichte erzielt wird. Weiterhin ergeben sich gün­ stige Möglichkeiten für die Wärmeabfuhr und geringe Leiterzugwege. Dadurch werden wiederum geringe Taktzeiten und eine geringe kapazitive Belastung erreicht.Due to the possibility of sinking the chips in the circuit board is also a small space allowed to ensure a large pack density is achieved. Furthermore, there are good results Opportunities for heat dissipation and low Ladder paths. This in turn will be minor Cycle times and a low capacitive load reached.

Die Erfindung soll im folgenden anhand eines Aus­ führungsbeispieles näher erläutert werden. In der zugehörigen Zeichnung zeigen:The invention is based on an off management example are explained in more detail. In the associated drawing show:

Fig. 1 Eine Schnittdarstellung des erfindungs­ gemäßen Chip-Moduls in Mehrfachanordnung. Fig. 1 is a sectional view of the chip module according to the Invention in multiple arrangement.

Fig. 2 Die Draufsicht auf ein erfindungsgemäßes Chip-Modul, auf dem sich unterschiedliche Formen von Schutzstreifen befinden. Fig. 2 The top view of an inventive chip module on which there are different forms of protective strips.

Fig. 3 Ein Schaltungsbeispiel für die Anwendung der Erfindung bei einem SIMM mit 3 Mb- Drams. Fig. 3 shows a circuit example for the application of the invention in a SIMM with 3 Mb drams.

Wie aus Fig. 1 ersichtlich ist, ist das erfin­ dungsgemäße Modul auf einer Leiterplatte 1 angeord­ net. In der Leiterplatte 1 sind in diesem Beispiel drei Ausfräsungen eingebracht, in denen die Chips 2.1 bis 2.3 angeordnet sind. Die Chips sind über Bonddrähte 4 mit den auf der Leiterplatte 1 ange­ ordneten Leiterbahnen 3 verbunden. Die Bonddrähte 4 sind in diesem Beispiel bogenförmig angeordnet. As can be seen from FIG. 1, the module according to the invention is arranged on a printed circuit board 1 . In this example, three cutouts are made in the printed circuit board 1 , in which the chips 2.1 to 2.3 are arranged. The chips are connected via bonding wires 4 to the conductor tracks 3 arranged on the printed circuit board 1 . The bonding wires 4 are arranged in an arc shape in this example.

Bei der in Fig. 2 dargestellten Anordnung ist das Chip 2 auf eine Leiterplatte 1 aufgesetzt, die nicht mit einer Ausfräsung oder einem Durchbruch versehen ist. Um das Chip 2 herum sind Schutz­ streifen 5 angebracht. Die Schutzstreifen 5 können in vielfältigen Formen ausgebildet sein, beispiels­ weise in Form von Längsstreifen oder als Kunst­ stoffrahmen 5.1.In the arrangement shown in Fig. 2, the chip 2 is placed on a circuit board 1 , which is not provided with a cutout or an opening. Around the chip 2 protective strips 5 are attached. The protective strips 5 can be designed in various forms, for example in the form of longitudinal strips or as a plastic frame 5.1 .

Eine bevorzugte Anwendungsmöglichkeit der Erfin­ dung besteht in der Verwendung als SIMM (Singel In­ line Memory Modul) für Speicher in PCs. Die nach dem Stand der Technik bekannten SIMMs haben eine Datenstruktur von 9, 18 oder 36 Bit. Eine vorteil­ hafte Ausgestaltung des erfindungsgemäßen SIMM hat, wie in Fig. 3 dargestellt, Leitungen für die Si­ gnale PCAS und CAS sowie PQ und PT zusammengefaßt. Diese sogenannte Security-Circiut-Schaltung hat den Vorteil, daß bei schlechter Kontaktierung oder Stö­ rungen von den PCAS-, PQ- oder PT-Signalen trotz­ dem fehlerfreies Arbeiten möglich ist.A preferred application of the inven tion is the use as SIMM (single in line memory module) for memory in PCs. The SIMMs known according to the prior art have a data structure of 9, 18 or 36 bits. An advantageous embodiment of the SIMM according to the invention has, as shown in FIG. 3, lines for the signals PCAS and CAS as well as PQ and PT combined. This so-called security circuit circuit has the advantage that in the event of poor contacting or malfunctions of the PCAS, PQ or PT signals, it is possible despite the error-free operation.

Claims (8)

1. Chip-Modul, bei dem mindestens ein Chip, vor­ zugsweise ein Speicher oder ein Prozessor, auf ei­ ner Leiterplatte angeordnet ist, dadurch gekenn­ zeichnet, daß sich auf dem Chip (2) außerhalb des Randes Bondinseln befinden, die durch Bonddrähte (4) mit Leiterbahnen (3) der Leiterplatte (1) verbunden sind.1. Chip module, in which at least one chip, preferably a memory or a processor, is arranged on a printed circuit board, characterized in that there are bond islands on the chip ( 2 ) outside the edge, which are connected by bond wires ( 4 ) are connected to conductor tracks ( 3 ) of the printed circuit board ( 1 ). 2. Chip-Modul nach Anspruch 1, dadurch gekennzeich­ net, daß sich in der Leiterplatte (1) mindestens ein Durchbruch oder eine Ausfräsung befindet und das Chip (2) versenkt in dem Durchbruch oder der Ausfräsung angeordnet ist.2. Chip module according to claim 1, characterized in that there is at least one opening or a cutout in the circuit board ( 1 ) and the chip ( 2 ) is arranged sunk in the cutout or cutout. 3. Chip-Modul nach Anspruch 1, dadurch gekennzeich­ net, daß auf der Leiterplatte (1) um das Chip (2) Schutzstreifen (5), vorzugsweise in Form eines Kunststoffrahmens (5.1), angeordnet sind.3. Chip module according to claim 1, characterized in that on the circuit board ( 1 ) around the chip ( 2 ) protective strips ( 5 ), preferably in the form of a plastic frame ( 5.1 ), are arranged. 4. Chip-Modul nach Anspruch 1, dadurch gekennzeich­ net, daß die Bonddrähte (4) bogenförmig angeordnet sind.4. Chip module according to claim 1, characterized in that the bonding wires ( 4 ) are arranged in an arc. 5. Chip-Modul nach einem der Ansprüche 1 bis 4, da­ durch gekennzeichnet, daß als Bonddrähte (4) Alumi­ niumdrähte verwendet werden. 5. Chip module according to one of claims 1 to 4, characterized in that aluminum wires are used as bonding wires ( 4 ). 6. Chip-Modul nach einem der Ansprüche 1 bis 5, da­ durch gekennzeichnet, daß das Chip (2) ein DRAM mit einer Speicherkapazität von 3 Mb oder ein ganzzah­ liges Vielfaches davon enthält.6. Chip module according to one of claims 1 to 5, characterized in that the chip ( 2 ) contains a DRAM with a memory capacity of 3 Mb or an integer multiple thereof. 7. Chip-Modul nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, daß das Chip (2) mindestens ein DRAM mit einer Speicherkapazität 4 Mb oder ein ganzzahliges Vielfaches davon enthält, das in gleiche Bereiche aufgeteilt ist, von denen einige mit der Leiterplatte (1) verbunden sind.7. Chip module according to one of claims 1 to 5, characterized in that the chip ( 2 ) contains at least one DRAM with a memory capacity of 4 Mb or an integer multiple thereof, which is divided into equal areas, some of which with the circuit board ( 1 ) are connected. 8. Chip-Modul nach Anspruch 6 oder 7, dadurch gekennzeichnet, daß auf dem Chip die PQ- und PD- Signale sowie die PCAS- und CAS-Signale miteinander verbunden sind.8. Chip module according to claim 6 or 7, characterized characterized in that the PQ and PD on the chip Signals as well as the PCAS and CAS signals with each other are connected.
DE4225154A 1992-07-30 1992-07-30 Chip module Withdrawn DE4225154A1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
DE4225154A DE4225154A1 (en) 1992-07-30 1992-07-30 Chip module
PCT/DE1993/000085 WO1994003924A1 (en) 1992-07-30 1993-01-29 Chip module
CA002141458A CA2141458A1 (en) 1992-07-30 1993-01-29 Chip module
CZ95219A CZ21995A3 (en) 1992-07-30 1993-01-29 Chip module
EP93903146A EP0653104A1 (en) 1992-07-30 1993-01-29 Chip module
SK181-95A SK18195A3 (en) 1992-07-30 1993-01-29 Chip module
JP6504869A JPH08501413A (en) 1992-07-30 1993-01-29 Chip module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4225154A DE4225154A1 (en) 1992-07-30 1992-07-30 Chip module

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DE4225154A1 true DE4225154A1 (en) 1994-02-03

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EP (1) EP0653104A1 (en)
JP (1) JPH08501413A (en)
CA (1) CA2141458A1 (en)
CZ (1) CZ21995A3 (en)
DE (1) DE4225154A1 (en)
SK (1) SK18195A3 (en)
WO (1) WO1994003924A1 (en)

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Also Published As

Publication number Publication date
WO1994003924A1 (en) 1994-02-17
SK18195A3 (en) 1995-06-07
JPH08501413A (en) 1996-02-13
EP0653104A1 (en) 1995-05-17
CZ21995A3 (en) 1995-06-14
CA2141458A1 (en) 1994-02-17

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