DE4230039A1 - Semiconductor component with chip embedded in cast plastics material - has electrode protrusions at required height on coupling faces, and numerous leads - Google Patents

Abstract

The plastics embedded semiconductor chip (1) has a circuit surface coated with a passivating layer. On the surface are formed circuits and connecting faces at desired points. These are electrode protrusions (8,9) with required height on the connecting faces. Numerous leads (5) consist each of an inner (5a) and an outer conductor (56). The outer conductor extends away from the inner one, which extends from the chip outer edge over the chip circuit surface (1a) in suitable spacing up to an electrode protrusion for electric coupling. The outer conductor protrudes from the plastics encapsulation. The latter is so formed that the outer conductor is exposed on the outside. USE/ADVANTAGE - For large semiconductor components, with good electric properties, high work velocity, low fault tendency, and large temp. variation tolerance.

Description

The invention relates to cast in plastic Semiconductor devices that are a large-sized semiconductor contain platelets, and especially on their inner Layout.

An example of a conventional semiconductor device in this field is described in JP-OS 61-2 41 959. , Fig. 19 is a partially sectional perspektivi specific view shown of the device according to this example. In this semiconductor device, many pads are formed in the central part of the surface of the semiconductor die, and insulating thin films are attached to both sides thereof. Inner conductors are placed on this insulating layer, the inner ends of which are electrically connected to the connection surfaces by bonding wires. Such a structure is referred to as a chip support conductor structure (lead on chip or LOC structure) and has the advantage that it gives good electrical properties and good suitability for encapsulating the large plate.

A typical process for making the die pad structure is the following: The top surface of a tile is interposed with an insulating layer with the glued bottom surface of a lead frame, after which the Inner conductor and the pads electrically by means of bonds wires are connected and this finally with plastic be shed. These inner conductors also serve as cast iron end surface, so that therefore no special cast connection areas are needed.  

Referring to FIG. 19 is a large plastic semiconductor wafer 1 in casting encapsulated 2 and surface to the center of the plate is formed on a Chen's line in the longitudinal direction of the Plätt a plurality of terminal surfaces 7. On both sides near the pads 7 away, a plurality of inner conductors 5, the ends of which are electrically connected by wires 4 with the Bonde pads 7 extends. Along the row of pads 7 inner busbars (busbars) 6 are formed on both sides, which are generally used for power supply or for mass connection. The two sections of these inner busbars 6 running on both sides of the inner conductor 5 are formed in one piece. On the surface of the semiconductor plate 1 is a polyimide insulating film 3 is applied around the pads 7 for electrical insulation and to keep α-particles. The inner manifold ter 6 and the other inner conductor 5 are fixed to the insulating film 3 with an adhesive (not shown). The insulating film 3 is also fixed to the semiconductor die 1 with an adhesive (not shown).

In another example disclosed in JP-OS 2-2 46 125 for a chip lead structure, the insulating film is rich reduced so that only one end portion of a respective inner conductor in contact with the film surface and the other part of the conductor from the top of the plate area is separated.

In the conventional semiconductors described above devices have the following problems:

• 1) Between the inner conductors and the semiconductor die  there is a considerable spreading capacity, because the Inner conductor over a thin insulating layer on the plate are glued on. This stray capacity causes a ver reduction in signal transmission speed and results also stronger electrical disturbances.
• 2) The insulating film material has high moisture absorption ability and the water absorbed during a High temperature treatment like a counter current process evaporates (in which the completed semiconductor device soldered to a circuit board under high temperature becomes). This could break the encapsulation housing or bite.
• 3) With regard to the coefficient of thermal expansion a considerably large deviation between the insulating film made of polyimide resin and the other materials used. As a result, problems arise when the devices Are exposed to temperature fluctuations.
• 4) For connecting the semiconductor die and the insulation films as well as the insulating film and the inner conductor Adhesive used. When occurring during operation cause deterioration of the adhesive Contamination contained Leakage currents between the conductors and also corrosion of the aluminum pads. As a result, reliability problems arise on.
• 5) Connections between pads of the semiconductor platelets and the inner conductors or busbars made by bond wires. By a loop height of  However, bond wire is the thickness of an encapsulation package determined, so that therefore no thin housing can be used can.
• 6) The inner conductors and busbars are with adhesive to the insulating film, which is immediately above the effective area of the semiconductor die is applied. Therefore, when connecting this conductor to the bond wires damage the mechanical shock effective range occur.
• 7) The bonds are for the electrical interconnections wires, but their impedance causes one additional signal transmission delay and stronger electrical interference.
• 8) The busbars and the inner conductors become one piece molded from a lead frame plate. This means that the Flexibility with regard to the leadership is restricted is difficult and crossovers or the like len are.

The invention is based, to solve the problem problems mentioned above with semiconductor devices To create chip lead structure, which good electri properties such as high working speed and low susceptibility to failure, large tolerances with regard to Temperature fluctuations, low encapsulation case height and high flexibility with regard to the routing of Connections between inner conductors and connection surfaces have a semiconductor die.  

The object is achieved with a semiconductor direction solved according to claim 1.

Advantageous embodiments of the semi-lead according to the invention Device are listed in the subclaims.

Extend in the semiconductor device according to the invention the inner conductors over the circuit area of the half printed circuit board at a predetermined distance from the circuit surface and are directly on the electrode protrusions Connections connected. This gives both a mechani electrical connection between the Conductors and the semiconductor die. This means that on the circuit area does not require any insulating layer is not necessary and no special cast connection surfaces are, since these inner conductors also as cast connection surfaces Act.

Another advantage of the invention is that elec trical connections between the large number of connecting surfaces chen by collecting electrode protrusions on the semiconductor platelets can be formed without other conductors to be used.

Furthermore, the invention has the advantage that different Electrode protrusions or collecting electrode protrusions simple electrical way through interconnect conductors tracks can be linked together below the passivation layer of the semiconductor die are.

Another advantage of the invention is that  Voltages supplied to the collecting electrode projections are stable are and contain little interference components because of the collection electrode protrusions with the interconnect traces under the passivation layer by a variety of Openings in the passivation layer along the collection electrode projections are connected through.

Another advantage is that the temperature increases the connecting portion of the inner conductor can be quickly increased can, since the one with the electrode projection or the collector part of the inner conductor to be connected is thinner than the other parts of the inner conductor.

Another advantage is that soft beam errors lung caused by α-particles from the inner conductors are avoided by a thin dielectric shield be on the circuit area of the semiconductor die chens with the exception of those areas which the electrode protrusions and the collecting electrodes jumps are formed.

The invention is illustrated below with reference to embodiments play explained with reference to the drawing.

Fig. 1 is a partially sectioned Darge perspective view of a semiconductor device according to a first embodiment of the invention.

Fig. 2 is a partial sectional view showing the configuration of an electrode protrusion on a circuit surface of a semiconductor die in Fig. 1.

Fig. 3 is a partially sectioned Darge perspective view of a semiconductor device according to a second embodiment.

Fig. 4 is a partially sectioned Darge perspective view of a semiconductor device according to a third embodiment.

Fig. 5 is a view of a section through part A of Fig. 4 along a line VV.

Fig. 6 is a partially sectioned Darge perspective view of a semiconductor device according to a fourth embodiment.

Fig. 7 is a view of a section through part B of Fig. 6 along line VII-VII.

, Fig. 8 is a partially sectional perspective view of a set Darge semiconductor device according to a fifth embodiment.

Fig. 9 is a view of a section through part C of Fig. 8 along a line IX-IX.

, Fig. 10 is a partially sectional perspective view of a set Darge semiconductor device according to a sixth embodiment.

, Fig. 11 is a partially sectional perspective view of a set Darge semiconductor device according to a seventh embodiment.

Fig. 12 is a sectional view of a part D of Fig. 11 along a line XII-XII.

, Fig. 13 is a partially sectional perspective view of a set Darge semiconductor device according to an eighth embodiment.

Fig. 14 is a sectional view of a part E of Fig. 13 along a line XIV-XIV.

, Fig. 15 is a partially sectional perspective view of a set Darge semiconductor device according to a ninth embodiment.

Fig. 16 is a sectional view of a part F of Fig. 15 along a line XVII-XVII.

, Fig. 17 is a partially sectional perspective view of a set Darge semiconductor device according to a tenth embodiment.

Fig. 18 is a sectional view of a part G of Fig. 17 along a line XVIII-XVIII.

Fig. 19 is a partially sectioned Darge perspective view of a conventional semiconductor device.

In the figures, parts are the same as those of FIG conventional semiconductor device with the same reference numeral  Chen called.

Fig. 1 is a partially sectioned perspective view of the semiconductor device according to the invention according to a first embodiment. Fig. 2 is a partial sectional view showing a protruding Elektro de or an electrode protrusion 8 and a collecting electrode protrusion 9 on a circuit area provided with a circuit surface 1 a of a semiconductor die 1 of FIG. 1. On the circuit surface 1 a of a silicon substrate 12 of the encapsulated with cast plastic 2 semiconductor wafer 1 , a plurality of pads 10 a is formed, on each of which electrode projections 8 are formed. On the semiconductor wafer 1 , the collecting electrode projections 9 are formed in the longitudinal direction in such a way that a plurality of connection surfaces 10 a of the same type are connected to one another by this. These collecting electrode protrusions 9 are used for supplying current, ground potential and reference voltages. Each pad 10 a is made of aluminum (Al), while the electrode jumps 8 and 9 each consist of gold (Au), these parts being formed by photolithography. The surface of the semiconductor die 1 provided with the circuit, with the exception of the regions on which the electrode projections 8 and 9 are formed, is covered in the usual manner with a passivation layer 11 in order to avoid oxidation, mechanical damage and environmental influences. Such a passivation layer 11 is also used in the conventional semiconductor wafers, but an additional insulating film is applied to them with an adhesive. The passivation layer 11 consists of SiN or SiO ₂ and is formed by photolithography.

The passivation layer 11 is very thin at approximately 0.7 μm. Each conductor 5 consists of an inner conductor 5 a within the cast plastic 2 and an outer conductor 5 b, which protrudes from the encapsulation housing. The end of the inner conductor 5 a is connected to the electrode projection 8 or the collecting electrode projection 9 . Each inner conductor 5 a extends at a suitable distance from the circuit surface 1 a of the semiconductor die 1 from the outside thereof to the respective electrode projection 8 or 9 . The inner conductor 5 a are made of an iron-nickel alloy (Fe-Ni) or an alloy based on copper (Cu). These inner conductors 5 a are placed on the electrode projections 8 or 9 and heated to connect them. To facilitate this process, the parts near the ends of the inner conductor 5 a are made thinner than the other parts for a faster temperature increase. Each inner conductor 5 a is connected to the corresponding electrode protrusion 8 or 9 in order to produce both an electrical and a direct mechanical connection. This means that the inner conductor 5 a also serve as a cast pad. It should be noted that in the casting with plastic, the space between these inner conductors 5 a and the semi-conductor plate 1 is filled with the casting plastic 2 .

In the first embodiment described above no insulating film and no adhesive is used that in the conventional semiconductor devices for connection of the insulating film with the semiconductor chip or the inner conductor is used with the insulating film. Hence yourself the following benefits:

• 1) The stray capacitance between the inner conductors 5 a and the semiconductor wafer 1 is reduced, so that therefore a higher signal transmission speed and less interference are achieved.
• 2) The reduced water absorption results in a lower one Probability of the encapsulation case breaking heating the finished semiconductor device for soldering them onto circuit boards.
• 3) Less pro occurs when the ambient temperature fluctuates open up.
• 4) There occur no leakage currents between the inner conductors 5a and no corrosion of the aluminum pads 10 a, since no adhesive is used, which could be degraded during operation, and may produce impurities, the leakage currents and corrosion would cause.

In addition, since the inner conductors are connected directly to the electrode protrusions 8 or 9 without using bond wires, the following advantages are achieved:

• 5) The thickness of the cast plastic 2 or the entire thickness of the semiconductor device can be reduced.
• 6) No wire bonding process is used, so therefore no mechanical damage caused by the bonding of the effective area of the semiconductor chip arises.
• 7) No bonding wires are used for the electrical connection used so no additional impedance through the wires arises. Furthermore, the contact resistance is less than  that of contacts between wire and pad. As a result, the signal transmission speed and insensitivity to interference or intoxication behavior improved.

While inner common conductors (busbars) are used in conventional semiconductor wafers, the collecting electrode projections 9 on the semiconductor wafer are used in the first embodiment. This gives the following advantages:

• 8) Power supply voltages, ground potential or any other signal level can be obtained with only very little attenuation at any point on the circuit area 1 a of the semiconductor die 1 . Therefore, compared to those in conventional semiconductor devices using the inner bus bars, higher signal transmission speed and less noise can be achieved.
• 9) The electrode protrusions 8 and the collecting electrode protrusions 9 are formed on the circuit surface 1 a of the semiconductor plate 1, for example by photolithography. Therefore, a very high degree of flexibility is achieved with regard to the line pattern design.

Fig. 3 is a partially sectioned perspective view of the semiconductor device according to the invention according to a second embodiment. In this embodiment, the collecting electrode protrusions 9 have taper portions 90 which extend to the inner conductors 5 a. As shown in this example, the collecting electrode protrusions can be formed in any desired shape. The other components in this embodiment are the same as those in the first embodiment and the same parts can be obtained before.

FIG. 4 is a perspective view, partly in section, of the semiconductor device according to the invention in accordance with a third exemplary embodiment. Fig. 5 is a view of a section through part A of Fig. 4 along a line VV. While in the first and second embodiments according to FIGS. 1 and 3 the collecting electrodes projections 9 surfaces in the longitudinal direction on the Halbleiterplätt are formed 1, in the third execution example collecting electrodes projections 9 a and 9 b, in addition to the longitudinal direction and formed in the transverse direction. Fig. 5 shows in detail the design of part A of FIG. 4, in which two collecting electrode projections 9 a and 9 b cross one another. According to Fig. 5 of the collecting electrode projection 9 is divided a into two parts, which are interconnected by an aluminum conductor track 10, which serves bond wire as Zwischenver, the crack under the Sammelelektrodenvor 9 b is formed to extend under the passivation layer 11. In this way, two collecting electrode projections can cross each other.

In this exemplary embodiment, the aluminum conductor tracks 10 run below the passivation layer 11 along the collecting electrode projections 9 a and 9 b, so that these are electrically connected to the relevant conductor track 10 through openings 11 a which are formed at suitable intervals in the passivation layer 11 . This results in more stable voltages (power supply voltages or ground potentials) and less interference at the collecting electrodes 9 a and 9 b.

It is obvious that the second embodiment shown in FIG. 3 can be combined with the third embodiment shown in FIGS . 4 and 5.

FIG. 6 is a perspective view, partly in section, of the semiconductor device according to the invention in accordance with a fourth exemplary embodiment. FIG. 7 is a view of a section through part B of FIG. 6 along line VII-VII. While in the above-described first embodiment, the collecting electrode projections 9 are formed at inner locations on the semiconductor die 1 and the electrode projections 8 are formed at outer locations, in the fourth embodiment, the collecting electrode projections 9 are formed at the outer locations and the electrode projections 8 at the inner locations det. Further, FIG. 7, according to the thickness of the collecting electrodes projections 9 lower than that of the electrode projections 8 so that the collecting electrodes projections 9 do not come to the inner conductors 5 a in contact. The collecting electrode protrusions 9 are electrically connected to some of the electrode protrusions 8 by aluminum conductor tracks 10 , which are ausgebil det on the circuit surface 1 a of the semiconductor die 1 . Therefore, in this embodiment, each inner conductor 5 a is connected to the corresponding electrode projection 8 , while the electrical connection to the collecting electrodes or collecting electrode projections 9 is brought about via the electrode projection 8 and the aluminum conductor track 10 .

Fig. 8 is a partially sectioned perspective view of the semiconductor device according to the invention according to a fifth embodiment. FIG. 9 is a view of a section through part C of FIG. 8 along line IX-IX. In this exemplary embodiment, in contrast to the fourth exemplary embodiment, the collecting electrode projections 9 are formed at the inner locations and the electrode projections 8 at the outer locations. According to FIG. 9, the collecting electrodes projections 9 are electrically connected to some of the electrode projections 8 through aluminum wirings 10, which are a of the semiconductor wafer 1 formed on the circuit surface 1. In this embodiment, all the inner conductors 5 a are also connected to the electrode projections 8 , while the electrical connection to the collecting electrode projections 9 via the electrode projections 8 and the aluminum conductor track 10 is reached.

Fig. 10 is a partially sectioned perspective view of the semiconductor device according to the invention according to a sixth embodiment. In the exemplary embodiments described above, the parts of the inner conductor 5 a to be connected to the electrode projections 8 or 9 are thinner than the other parts, while in the sixth exemplary embodiment all parts of the inner conductor 5 a have the same dimensions.

Fig. 11 is a partially sectioned perspective view of the semiconductor device according to the invention according to a seventh embodiment. FIG. 12 is a view of a section through part D of FIG. 11 along a line XII-XII. In this embodiment, for example, according to FIG. 11, two collecting electrode projections 9 a and 9 b, each with a U-shape, are formed on the platelet surface. As shown in Fig. 12, this collecting electrodes projections 9 a and 9 b electrically connected to some of the electrode projections 8 through aluminum wirings 10 are connected, which are a of the semiconductor wafer 1 formed on the circuit surface 1. The collecting electrode projections 9 a and 9 b are arranged at the outer locations and the electrode projections 8 are arranged at the inner locations. The height of the collecting electrode projections 9 a and 9 b is less than that of the electrode projections 8 in order to avoid electrical contact with the inner conductors 5 a. All inner conductors 5 a are connected to the electrode projections 8 and the electrical connection to the collecting electrode projections 9 a and 9 b is achieved via the electrode projections 8 and the aluminum conductor tracks 10 .

The Fig. 13 is a partially shown device according to an eighth embodiment of the invention in section Halbleitervor per-perspective view. FIG. 14 is a view of a section through a part E according to FIG. 13 along a line XIV-XIV. In this embodiment, for example, the longitudinally extending on the semiconductor wafer 1 collecting electrode projections 9 are so wide that the inductances of these electrodes are sufficiently small. This collecting electrodes projections 9 are shown in FIG. 14 electrically connected to certain electrode projections 8 through aluminum wirings 10 are connected, which are on the TIC surface 1a of the semiconductor chip 1 is formed. The collecting electrodes projections 9 are formed at the outer bodies and the electrode projections 8 are formed on the internal sites, and therefore, the electrode projections 8 are thicker than the collecting electrodes projections 9 designed in a way so they do not come to the inner conductors 5 a in contact.

Fig. 15 is a partially sectioned perspective view of the semiconductor device according to the invention according to a ninth embodiment. Fig. 16 is a view of a section through part F of Fig. 15 along a line XVI-XVI. In this embodiment, for example, two collecting electrode projections 9 are formed in the longitudinal direction at outer locations on the semiconductor wafer 1 . Electrode protrusions 8 are aligned in a line at inner locations. From both sides of the semiconducting terplättchens extend away in FIG. 15 inner conductor 5 A to the electrode projections 8 out such that comb-toothed compounds. The Sammelelektrodenvor cracks 9 are shown in FIG. 16 electrically connected to certain electrode projections 8 through aluminum wirings 10 are connected, which are formed on the circuit surface 1 a of the semiconductor wafer 1. The collecting electrode projections 9 are formed at the outer locations and the electrode projections 8 are formed at the inner locations, so that therefore the collecting electrode projections 9 are formed to avoid contact with the inner conductors 5 a with a smaller thickness than the electrode extensions 8 .

The second to sixth embodiments result in same advantages as the first embodiment.

Fig. 17 is a partially sectioned perspective view of the semiconductor device according to the invention according to a tenth embodiment. Fig. 18 is a sectional view of a part G of Fig. 17 along a line XVIII-XVIII. While in the previously described embodiments, the electrode projections 8 are aligned on one line or on two lines, the tenth embodiment has electrode projections 8 which are set up at any desired locations. Furthermore, a thin dielectric layer 15 is applied to the circuit area 1 a of the semiconductor die 1, with the exception of the locations at which the connection areas 10 a are formed, in order to prevent the circuit from being caused by α-particles from the inner conductors 5 a by soft errors Protect radiation. This dielectric layer 15 is made of polyimide or the like and, like the passivation layer 11, is formed by photolithography. Therefore, unlike the conventional semiconductor devices, no adhesive is required and the film can be very thin. As a result, no problems arise even when the devices are exposed to heat fluctuations and no corrosion occurs, and better electrical properties are obtained, as in the previously described embodiments.

As described above, in FIGS semiconductor devices according to the invention the inner conductor about the circuit provided with the circuit arrangement area at a suitable distance from this and the ends of the Inner conductors are directly on the protruding electrodes or electrode projections on the pads closed to both electrical and mechanical ver create a bond. Therefore, insulating films, adhesives and bond wires not needed. This results in very high performance  capable semiconductor devices with chip support conductor or LOC structure that have a number of advantages like that Operation at high speed and low interference, the disappearance of heat deterioration, the possible encapsulation in a thin housing, high flexibility bility with regard to the routing for connecting Pads with leads and a high reliability speed.

Semiconductor devices with chip support conductors are Structure described, the high electrical capacity speed, low deterioration due to heat, suitability for Encapsulation in thin housing and great flexibility Lich the design of connections between pads and show feeders. These excellent properties are achieved because no insulating films, adhesives and Binding wires are used that have a deterioration of electrical and other properties. The characteristic feature of these semiconductor devices consists in that from the outer edge of a semiconductor wafer chens forth over its circuit area at a suitable distance from this inner conductor, which also serves as a cast pad act, extend to electrode protrusions on which ever because the end of the inner conductor in question is directly fixed attaches to both electrical and mechanical connections manufacture.

Claims (6)

1. Semiconductor device with a semiconductor wafer which is enclosed with a cast plastic and which has a circuit area covered with a passivation layer, on which circuits and at desired locations including the central part of the circuit area are formed by connecting surfaces, characterized by electrode projections ( 8 , 9 ), which are formed with a desired height on the connection surfaces ( 10 a), and a plurality of feed lines ( 5 ), each consisting of an inner conductor ( 5 a) and an outer conductor ( 5 b), which is different from the The inner conductor extends away from the outer edge of the semiconductor chip ( 1 ) via its circuit surface ( 1 a) at a suitable distance from it to the electrode projection and is fixed to the electrical connection, the outer conductor being made of the cast plastic ( 2 ) protrudes, which encloses the components such that the outer conductor d he exposes cables on the outside. 2. Semiconductor device according to claim 1, characterized in that on the circuit surface ( 1 a) on the passivation layer ( 11 ) at least one collecting electrode jump ( 9 ) is formed with a predetermined height such that it Chen over at least two of the electrode connection surfaces ( 10 a) extends to establish the electrical connection between the collecting electrode projection and the connection pads. 3. Semiconductor device according to claim 2, characterized in that under the passivation layer ( 11 ) on the circuit surface ( 1 a) of the semiconductor chip ( 1 ) between connecting conductor tracks ( 10 ) are formed such that they each have an electrical connection between the electrode projections ( 8 ) with each other, between the collecting electrode projections ( 9 ) with each other or between the electrode projections and the collecting electrode projections. 4. Semiconductor device according to claim 3, characterized in that beneath the passivation layer ( 11 ) circuit tracks ( 10 ) are formed, which jump along the collecting electrode projections ( 9 ), and that in the passivation layer along the conductor tracks, a plurality of openings ( 11 a) are formed, through which the collecting electrode projections are electrically connected to the conductor tracks. 5. Semiconductor device according to one of the preceding claims, characterized in that a part with a respective electrode projection ( 8 , 9 ) to be connected to the inner conductor ( 5 a) of the feed line ( 5 ) is thinner than the other part of the feed line, so that the thin part can be heated more quickly. 6. Semiconductor device according to one of the preceding claims, characterized in that on the circuit surface ( 1 a) of the semiconductor chip ( 1 ), with the exception of the areas where the electrode projections ( 8 , 9 ) are ausgebil det, a thin dielectric layer ( 15 ) is formed, which protects the circuits against α-particles.