DE4323799B4 - Halbleiteranordnung und Verfahren zu ihrer Herstellung - Google Patents

Halbleiteranordnung und Verfahren zu ihrer Herstellung Download PDF

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Publication number
DE4323799B4
DE4323799B4 DE4323799A DE4323799A DE4323799B4 DE 4323799 B4 DE4323799 B4 DE 4323799B4 DE 4323799 A DE4323799 A DE 4323799A DE 4323799 A DE4323799 A DE 4323799A DE 4323799 B4 DE4323799 B4 DE 4323799B4
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production
semiconductor device
semiconductor
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Expired - Fee Related
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DE4323799A
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DE4323799A1 (de
Inventor
You Kondoh
Masayuki Saito
Takasi Togasaki
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Toshiba Corp
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Toshiba Corp
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Publication of DE4323799A1 publication Critical patent/DE4323799A1/de
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Families Citing this family (124)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5712192A (en) * 1994-04-26 1998-01-27 International Business Machines Corporation Process for connecting an electrical device to a circuit substrate
DE4424014A1 (de) * 1994-07-08 1996-01-11 Ant Nachrichtentech Verfahren zur Bildung von Kontaktsockeln an Halbleiterbauelementen
CA2154409C (en) * 1994-07-22 1999-12-14 Yuzo Shimada Connecting member and a connecting method using the same
US5633535A (en) * 1995-01-27 1997-05-27 Chao; Clinton C. Spacing control in electronic device assemblies
JP3484554B2 (ja) * 1995-02-28 2004-01-06 日本テキサス・インスツルメンツ株式会社 半導体装置
DE19507547C2 (de) * 1995-03-03 1997-12-11 Siemens Ag Verfahren zur Montage von Chips
US5801446A (en) * 1995-03-28 1998-09-01 Tessera, Inc. Microelectronic connections with solid core joining units
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
WO1996031905A1 (en) 1995-04-05 1996-10-10 Mcnc A solder bump structure for a microelectronic substrate
US5745985A (en) * 1995-06-23 1998-05-05 Texas Instruments Incorporated Method of attaching a semiconductor microchip to a circuit board
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US5847309A (en) * 1995-08-24 1998-12-08 Auburn University Radio frequency and electrostatic discharge insensitive electro-explosive devices having non-linear resistances
US6097099A (en) * 1995-10-20 2000-08-01 Texas Instruments Incorporated Electro-thermal nested die-attach design
DE19548050A1 (de) * 1995-12-21 1997-06-26 Siemens Matsushita Components Elektronisches Bauelement, insbesondere mit akustischen Oberflächenwellen arbeitendes Bauelement - OFW-Bauelement -
US6111317A (en) * 1996-01-18 2000-08-29 Kabushiki Kaisha Toshiba Flip-chip connection type semiconductor integrated circuit device
US5760479A (en) * 1996-02-29 1998-06-02 Texas Instruments Incorporated Flip-chip die attachment for a high temperature die to substrate bond
JP2891665B2 (ja) 1996-03-22 1999-05-17 株式会社日立製作所 半導体集積回路装置およびその製造方法
US20040061220A1 (en) * 1996-03-22 2004-04-01 Chuichi Miyazaki Semiconductor device and manufacturing method thereof
US6351389B1 (en) 1996-05-07 2002-02-26 Sun Microsystems, Inc. Device and method for packaging an electronic device
FR2748849B1 (fr) * 1996-05-20 1998-06-19 Commissariat Energie Atomique Systeme de composants a hybrider et procede d'hybridation autorisant des dilatations thermiques
US6025767A (en) * 1996-08-05 2000-02-15 Mcnc Encapsulated micro-relay modules and methods of fabricating same
JPH1064956A (ja) * 1996-08-20 1998-03-06 Fujitsu Ltd フェースダウンボンディング半導体装置
EP0899787A3 (de) * 1997-07-25 2001-05-16 Mcnc Knotrolliert geformte Lötreservoirszur Volumenerhöhung von Löthöckern und damit hergestellten Strukturen
JP3644205B2 (ja) * 1997-08-08 2005-04-27 株式会社デンソー 半導体装置及びその製造方法
US6096576A (en) 1997-09-02 2000-08-01 Silicon Light Machines Method of producing an electrical interface to an integrated circuit device having high density I/O count
US6105503A (en) * 1998-03-16 2000-08-22 Auburn University Electro-explosive device with shaped primary charge
US6423623B1 (en) 1998-06-09 2002-07-23 Fairchild Semiconductor Corporation Low Resistance package for semiconductor devices
DE19826426C2 (de) * 1998-06-16 2003-08-21 Elbau Elektronik Bauelemente G Miniaturisiertes elektronisches System und Verfahren zu seiner Herstellung
FR2780200B1 (fr) * 1998-06-22 2003-09-05 Commissariat Energie Atomique Dispositif et procede de formation d'un dispositif presentant une cavite a atmosphere controlee
JP3278055B2 (ja) * 1998-06-30 2002-04-30 セイコーインスツルメンツ株式会社 電子回路装置
US6303986B1 (en) * 1998-07-29 2001-10-16 Silicon Light Machines Method of and apparatus for sealing an hermetic lid to a semiconductor die
US6133634A (en) 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
DE19902450B4 (de) * 1999-01-22 2006-04-20 Festo Ag & Co. Miniaturisiertes elektronisches System und zu dessen Herstellung geeignetes Verfahren
US6724084B1 (en) 1999-02-08 2004-04-20 Rohm Co., Ltd. Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device
US6483190B1 (en) * 1999-10-20 2002-11-19 Fujitsu Limited Semiconductor chip element, semiconductor chip element mounting structure, semiconductor chip element mounting device and mounting method
US6329220B1 (en) 1999-11-23 2001-12-11 Micron Technology, Inc. Packages for semiconductor die
US6864574B1 (en) * 1999-11-29 2005-03-08 Matsushita Electric Industrial Co., Ltd. Semiconductor package
US6214650B1 (en) 2000-02-01 2001-04-10 Lockheed Martin Corporation Method and apparatus for sealing a ball grid array package and circuit card interconnection
US6624522B2 (en) * 2000-04-04 2003-09-23 International Rectifier Corporation Chip scale surface mounted device and process of manufacture
US6772692B2 (en) * 2000-05-24 2004-08-10 Lifesparc, Inc. Electro-explosive device with laminate bridge
EP1168429A1 (de) * 2000-06-28 2002-01-02 Telefonaktiebolaget L M Ericsson (Publ) Integriertes Halbleiterchip und Verfahren, um dieses auf eine Leiterplatte zu montieren
JP4845250B2 (ja) * 2000-07-25 2011-12-28 ソニー株式会社 固体撮像素子収納パッケージ及び固体撮像装置
US6559537B1 (en) * 2000-08-31 2003-05-06 Micron Technology, Inc. Ball grid array packages with thermally conductive containers
US6387723B1 (en) 2001-01-19 2002-05-14 Silicon Light Machines Reduced surface charging in silicon-based devices
KR20020065045A (ko) 2001-02-05 2002-08-13 삼성전자 주식회사 확장 패드들을 포함하는 반도체 칩 패키지
DE10108081B4 (de) * 2001-02-20 2006-01-12 Infineon Technologies Ag Anordnung eines Halbleiterchips auf einem Substrat
US6930397B2 (en) * 2001-03-28 2005-08-16 International Rectifier Corporation Surface mounted package with die bottom spaced from support board
US7119447B2 (en) * 2001-03-28 2006-10-10 International Rectifier Corporation Direct fet device for high frequency application
US6630689B2 (en) * 2001-05-09 2003-10-07 Lumileds Lighting, U.S. Llc Semiconductor LED flip-chip with high reflectivity dielectric coating on the mesa
US6455878B1 (en) 2001-05-15 2002-09-24 Lumileds Lighting U.S., Llc Semiconductor LED flip-chip having low refractive index underfill
US7476964B2 (en) * 2001-06-18 2009-01-13 International Rectifier Corporation High voltage semiconductor device housing with increased clearance between housing can and die for improved flux flushing
JP4105409B2 (ja) * 2001-06-22 2008-06-25 株式会社ルネサステクノロジ マルチチップモジュールの製造方法
US6782205B2 (en) 2001-06-25 2004-08-24 Silicon Light Machines Method and apparatus for dynamic equalization in wavelength division multiplexing
US6646778B2 (en) 2001-08-01 2003-11-11 Silicon Light Machines Grating light valve with encapsulated dampening gas
US6829092B2 (en) 2001-08-15 2004-12-07 Silicon Light Machines, Inc. Blazed grating light valve
US6785001B2 (en) 2001-08-21 2004-08-31 Silicon Light Machines, Inc. Method and apparatus for measuring wavelength jitter of light signal
US6582990B2 (en) * 2001-08-24 2003-06-24 International Rectifier Corporation Wafer level underfill and interconnect process
US6638638B2 (en) * 2001-09-18 2003-10-28 Samsung Electronics Co., Ltd. Hollow solder structure having improved reliability and method of manufacturing same
US6784540B2 (en) 2001-10-10 2004-08-31 International Rectifier Corp. Semiconductor device package with improved cooling
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US6800238B1 (en) 2002-01-15 2004-10-05 Silicon Light Machines, Inc. Method for domain patterning in low coercive field ferroelectrics
US6767751B2 (en) 2002-05-28 2004-07-27 Silicon Light Machines, Inc. Integrated driver process flow
US6839479B2 (en) 2002-05-29 2005-01-04 Silicon Light Machines Corporation Optical switch
DE10227342B4 (de) * 2002-06-19 2008-06-05 Qimonda Ag Verfahren zur Verbindung einer integrierten Schaltung mit einem Substrat und entsprechende Schaltungsanordnung
US7547623B2 (en) 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
US6960828B2 (en) 2002-06-25 2005-11-01 Unitive International Limited Electronic structures including conductive shunt layers
US6813059B2 (en) 2002-06-28 2004-11-02 Silicon Light Machines, Inc. Reduced formation of asperities in contact micro-structures
US7579697B2 (en) 2002-07-15 2009-08-25 International Rectifier Corporation Arrangement for high frequency application
US7397137B2 (en) * 2002-07-15 2008-07-08 International Rectifier Corporation Direct FET device for high frequency application
US6801354B1 (en) 2002-08-20 2004-10-05 Silicon Light Machines, Inc. 2-D diffraction grating for substantially eliminating polarization dependent losses
US6712480B1 (en) 2002-09-27 2004-03-30 Silicon Light Machines Controlled curvature of stressed micro-structures
US6841865B2 (en) * 2002-11-22 2005-01-11 International Rectifier Corporation Semiconductor device having clips for connecting to external elements
US20050161814A1 (en) * 2002-12-27 2005-07-28 Fujitsu Limited Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
JP3905041B2 (ja) * 2003-01-07 2007-04-18 株式会社日立製作所 電子デバイスおよびその製造方法
US20040134680A1 (en) * 2003-01-09 2004-07-15 Xiang Dai Use of perimeter stops to support solder interconnects between integrated circuit assembly components
US6806997B1 (en) 2003-02-28 2004-10-19 Silicon Light Machines, Inc. Patterned diffractive light modulator ribbon for PDL reduction
US7046420B1 (en) 2003-02-28 2006-05-16 Silicon Light Machines Corporation MEM micro-structures and methods of making the same
US6829077B1 (en) 2003-02-28 2004-12-07 Silicon Light Machines, Inc. Diffractive light modulator with dynamically rotatable diffraction plane
US7462942B2 (en) * 2003-10-09 2008-12-09 Advanpack Solutions Pte Ltd Die pillar structures and a method of their formation
US7049216B2 (en) 2003-10-14 2006-05-23 Unitive International Limited Methods of providing solder structures for out plane connections
US20050133933A1 (en) * 2003-12-19 2005-06-23 Advanpack Solutions Pte. Ltd. Various structure/height bumps for wafer level-chip scale package
US20050269677A1 (en) * 2004-05-28 2005-12-08 Martin Standing Preparation of front contact for surface mounting
DE502004009167D1 (de) * 2004-07-19 2009-04-23 Fraunhofer Ges Forschung Videoendoskopievorrichtung
KR100498708B1 (ko) * 2004-11-08 2005-07-01 옵토팩 주식회사 반도체 소자용 전자패키지 및 그 패키징 방법
DE102004055677A1 (de) * 2004-11-18 2006-06-01 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Chipträgerverbund und Verfahren zum Herstellen eines Chipträgerverbunds
US7524701B2 (en) * 2005-04-20 2009-04-28 International Rectifier Corporation Chip-scale package
US7230333B2 (en) 2005-04-21 2007-06-12 International Rectifier Corporation Semiconductor package
US8466546B2 (en) 2005-04-22 2013-06-18 International Rectifier Corporation Chip-scale package
DE102005021653A1 (de) * 2005-05-06 2006-07-13 Infineon Technologies Ag Oberflächenmontierbares Halbleiterbauteil und Schaltungsträger mit oberflächenmontiertem Halbleiterbauteil sowie Verfahren zur Herstellung derselben
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US7932615B2 (en) 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers
DE102006025162B3 (de) * 2006-05-30 2008-01-31 Epcos Ag Flip-Chip-Bauelement und Verfahren zur Herstellung
DE102006053862B4 (de) * 2006-11-14 2008-07-24 Schott Ag Verfahren zum Verpacken von Bauelementen
JP4795883B2 (ja) * 2006-07-21 2011-10-19 株式会社日立ハイテクノロジーズ パターン検査・計測装置
US20080048321A1 (en) * 2006-08-24 2008-02-28 Ati Technologies Inc. Flip chip semiconductor assembly with variable volume solder bumps
KR100762354B1 (ko) * 2006-09-11 2007-10-12 주식회사 네패스 플립칩 반도체 패키지 및 그 제조방법
US7709292B2 (en) * 2006-09-29 2010-05-04 Sadwick Laurence P Processes and packaging for high voltage integrated circuits, electronic devices, and circuits
JP4850029B2 (ja) * 2006-10-31 2012-01-11 セイコーインスツル株式会社 半導体装置
US8618670B2 (en) * 2008-08-15 2013-12-31 Qualcomm Incorporated Corrosion control of stacked integrated circuits
US9524945B2 (en) 2010-05-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with L-shaped non-metal sidewall protection structure
KR101483274B1 (ko) * 2008-10-23 2015-01-16 삼성전자주식회사 반도체 패키징 장치
US8324738B2 (en) * 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
FR2949903A1 (fr) * 2009-09-07 2011-03-11 Soc Fr Detecteurs Infrarouges Sofradir Procede d'hybridation de composants electroniques, notamment de detection
TWI412107B (zh) * 2009-10-02 2013-10-11 Ind Tech Res Inst 凸塊結構、晶片封裝結構及該凸塊結構之製備方法
JP4995883B2 (ja) * 2009-10-19 2012-08-08 力成科技股▲分▼有限公司 半導体フリップチップ構造体
US8659155B2 (en) * 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US20110169158A1 (en) * 2010-01-14 2011-07-14 Qualcomm Incorporated Solder Pillars in Flip Chip Assembly
US8610270B2 (en) 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US8441124B2 (en) * 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US9018758B2 (en) 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
DE102010032506A1 (de) 2010-07-28 2012-02-02 Epcos Ag Modul und Herstellungsverfahren
US8546254B2 (en) 2010-08-19 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
JP5461342B2 (ja) * 2010-08-23 2014-04-02 京セラＳｌｃテクノロジー株式会社 配線基板
US8916969B2 (en) * 2011-07-29 2014-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, packaging methods and structures
US20130299989A1 (en) * 2012-05-10 2013-11-14 International Business Machines Corporation Chip connection structure and method of forming
KR101383002B1 (ko) * 2012-05-25 2014-04-08 엘지이노텍 주식회사 반도체 패키지 기판, 이를 이용한 패키지 시스템 및 이의 제조 방법
US8970035B2 (en) 2012-08-31 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package
US9622356B2 (en) 2013-03-14 2017-04-11 Lockheed Martin Corporation Electronic package mounting
JP6287445B2 (ja) * 2014-03-26 2018-03-07 三菱電機株式会社 半導体装置及びその製造方法
DE102014223862A1 (de) * 2014-11-24 2016-05-25 Robert Bosch Gmbh Anordnung mit einem Trägersubstrat und einem Leistungsbauelement
US9875988B2 (en) * 2015-10-29 2018-01-23 Semtech Corporation Semiconductor device and method of forming DCALGA package using semiconductor die with micro pillars
JP6534700B2 (ja) * 2017-04-28 2019-06-26 アオイ電子株式会社 半導体装置の製造方法
US20240113066A1 (en) * 2021-02-19 2024-04-04 Sony Semiconductor Solutions Corporation Electronic device
DE102021129113A1 (de) * 2021-11-09 2023-05-11 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Halbleiterchip und halbleiterbauteil

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3871015A (en) * 1969-08-14 1975-03-11 Ibm Flip chip module with non-uniform connector joints
JPS5683054A (en) * 1979-12-10 1981-07-07 Fujitsu Ltd Semiconductor device
JPH01161775A (ja) * 1987-12-18 1989-06-26 Toshiba Corp 固体撮像装置
JPH02267942A (ja) * 1989-04-07 1990-11-01 Fuji Electric Co Ltd 半導体チップの実装構造
JPH02270375A (ja) * 1989-04-12 1990-11-05 Toshiba Corp 固体撮像装置
JPH03214629A (ja) * 1990-01-18 1991-09-19 Fujitsu Ltd 半導体装置の製造方法
JPH03222334A (ja) * 1990-01-26 1991-10-01 Shimadzu Corp はんだバンプ構造
JPH056920A (ja) * 1991-06-27 1993-01-14 Toshiba Corp 半導体装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3591839A (en) * 1969-08-27 1971-07-06 Siliconix Inc Micro-electronic circuit with novel hermetic sealing structure and method of manufacture
US4604644A (en) * 1985-01-28 1986-08-05 International Business Machines Corporation Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
CA1226966A (en) * 1985-09-10 1987-09-15 Gabriel Marcantonio Integrated circuit chip package
US4942140A (en) * 1987-03-25 1990-07-17 Mitsubishi Denki Kabushiki Kaisha Method of packaging semiconductor device
US5021888A (en) * 1987-12-18 1991-06-04 Kabushiki Kaisha Toshiba Miniaturized solid state imaging device
US5071787A (en) * 1989-03-14 1991-12-10 Kabushiki Kaisha Toshiba Semiconductor device utilizing a face-down bonding and a method for manufacturing the same
JPH0451057A (ja) * 1990-06-18 1992-02-19 Canon Inc 画像形成装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3871015A (en) * 1969-08-14 1975-03-11 Ibm Flip chip module with non-uniform connector joints
JPS5683054A (en) * 1979-12-10 1981-07-07 Fujitsu Ltd Semiconductor device
JPH01161775A (ja) * 1987-12-18 1989-06-26 Toshiba Corp 固体撮像装置
JPH02267942A (ja) * 1989-04-07 1990-11-01 Fuji Electric Co Ltd 半導体チップの実装構造
JPH02270375A (ja) * 1989-04-12 1990-11-05 Toshiba Corp 固体撮像装置
JPH03214629A (ja) * 1990-01-18 1991-09-19 Fujitsu Ltd 半導体装置の製造方法
JPH03222334A (ja) * 1990-01-26 1991-10-01 Shimadzu Corp はんだバンプ構造
JPH056920A (ja) * 1991-06-27 1993-01-14 Toshiba Corp 半導体装置

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Patent Abstracts of Japan, E-1144, 11.12.1991, Vol. 15, No. 490 & JP 03-214629 A *
Patent Abstracts of Japan, E-1148, 20.12.1991, Vol. 15, No. 506 & JP 03-222334 A *

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