DE4337740A1 - Semiconductor memory for cache and image processing - has DRAM single line and column block selector circuits, SRAM cell block selector circuits, and circuit for transferring data between DRAM column block and selected cell block of SRAM - Google Patents

Abstract

The memory has a DRAM (102) with several dynamic memory cells in a matrix. A control circuit including a line selector (110) selects a line in the DRAM field according to an address. The control circuit also includes a column block selector (112) which is dependent on an external control signal for driving the DRAM. An SRAM (104) has a memory cell selector (118, 120) which is controlled by a third address, which is dependent on an externally-supplied control signal for driving of the SRAM and independent of the first control circuit. Data is transmitted between the selected DRAM and SRAM memory cell blocks. USE/ADVANTAGE - Memory integrated on chip for use in high speed microprocessor. Data read and write takes place at high speed.

Description

The invention relates to a device according to the preamble of Claims 1, 2, 12, 13, 19, 20, 21, 24, 26, 27, 28, 30, 31, 32, 36, 38 or 40 and a method according to the preamble of Claim 15, 16, 18 or 29. The invention relates in particular, a semiconductor memory device that a Main memory with large capacity and a fast cache Has low capacity memory on the same Chip are integrated. The present invention relates more specifically said a semiconductor memory device with a cache that a dynamic random access memory (DRAM) and one  static random access memory (SRAM) that is based on are integrated in the same chip.

i) Use of standard DRAM as main memory

The operating speed of modern microprocessor units (MPU) has risen so much that it becomes an operating frequency of 25 MHz or more. In a data processing system a standard DRAM is often used as main memory with a large Storage capacity used. Although the access time of one Standard DRAM has been decreased MPU operating speed increased much faster than that of the standard DRAM. Hence the increase in waiting cycles in a data processing system with a standard DRAM as Main memory inevitable. The distance in the Operating speed between MPU and standard DRAM is inevitable because the standard DRAM has the following characteristics having.

• 1) Row address and column address are time-multiplexed and are created on the same address connections. The Row address is with the falling edge of a row address Sampling signal / RAS adopted in the device. The Column address becomes one with the falling edge Column address strobe signal / CAS adopted in the device. The row address strobe signal / RAS defines the beginning of a Memory cycle and activates the row selection circuit. The Column address strobe / CAS activates the Column selection circuit. Because a predetermined period of time with the designation "RAS / CAS delay time (tRCD)" between the Time when the signal / RAS is in an active state and the time at which the signal / CAS is activated, there is a limit for the Reduce access time. There is a limit due to address multiplexing.
• 2) When the row address strobe / RAS is raised once to put the DRAM on hold the row address strobe signal / RAS does not fall again to "L",  up to a time period called RAS precharge time (tRP) has passed. The RAS preload time is necessary to different signal lines in the DRAM to predetermined potentials safe to preload. Due to the RAS precharge time tRP, the Cycle time of the DRAM cannot be reduced. If the cycle time of the DRAM is reduced, the number of Charging / discharging of signal lines in the DRAM. The increases the current consumption.
• 3) A higher working speed of the DRAM can be achieved by Circuit technologies are implemented, such as. B. Layout improvements, enlargement of the Circuit integration levels, developments in the Manufacturing technology and through application-oriented Improvements such as improvements in the control method. However, the MPU's operating speed increases much faster than that of the DRAM. The operating speed of Semiconductor storage is hierarchical. For example there is High-speed bipolar RAMs, the bipolar transistors use such. B. ECLRAMs (Emitter Coupled RAMs) and static RAMs and relatively slow DRAMs with MOS Transistors (field effect transistors with insulated gate). It is very difficult to determine operating speeds (cycle times) of several tens of ns (nanoseconds) in a standard DRAM developed by MOS transistors is formed to achieve.

It has several application-oriented improvements given to fill the gap between the operating speeds of Close MPU and standard DRAM. Such improvements mainly include the following two approaches.

• 1) Using high speed modes of the DRAM and Interleave procedure.
• 2) External formation of a high-speed cache (SRAM).

The first access (1) involves using one High speed mode, such as B. a static column mode  or a page mode, and combining the High speed mode and the interleave process. in the Static column mode becomes a word line (one line) selected, and then successively only the Column address changed to memory cells of this row to address one after the other. In page mode there is a word line selected, and then the column addresses are marked with Switching it signals / CAS successively read in Memory cells that are connected to this one word line, to address one after the other. In both modes, the Memory cells can be addressed without the signal / RAS toggle, which means faster access than the Normal access possible using the signals / RAS and / CAS is.

The interleave method uses a plurality of memories formed parallel to a data bus, and by alternating or sequentially addressing the plurality of memories the access time can be reduced. The use of a High speed mode of the DRAM and the combination of High speed mode and interleave process is considered Method known to use a standard DRAM as a high-speed Use DRAM in a simple and relatively effective way.

The second access (2) is to a large extent in the area of Mainframes have been applied. A High speed cache memory is expensive. In the field of Personal computer, where both high performance and low In some areas, this access is costly desired applied regardless of cost. There are three Ways to Use the High Speed Cache form, namely

• a) The high speed cache is in the MPU included itself;
• b) the high speed cache is outside of the MPU formed; and  
• c) the high speed cache is not separate formed, but a high-speed mode in the standard DRAM is used as a cache (the high speed mode is used as Pseudo cache memory used). If a cache hit occurs, so the standard DRAM will be in high speed mode addressed, and in the event of a cache miss, the default DRAM addressed in normal mode).

The above three ways (a) to (c) are in Data processing systems in one way or another been applied. In terms of cost, most are MPU systems that organize memories with a bank structure, and interleaving is bank-wise to Overcoming preload time (tRP), which is inevitable in the DRAM. With this method, the cycle time of the DRAM in the substantially reduced to half the specification value become.

The interleave process is only efficient if the Memory can be addressed sequentially. If the same Memory bank is addressed continuously, it is ineffective. Furthermore, no significant improvement in the Access time of the DRAM itself can be realized. The minimal Storage unit is at least two banks.

If a high-speed mode such. B. the page mode or Static column mode, the access time can only be used can be effectively reduced if the MPU has a certain page (the data of a defined line) responds multiple times. This Procedure is somewhat effective when the number of Banks is comparatively large, e.g. B. two or four because different lines can be addressed in different banks can. If the data of the memory requested by the MPU in the given page does not exist, it is called "Missed hit" (cache missed). Usually it will a group of data on adjacent or sequential Addresses saved. Is already in high speed mode a row address that represents half of the addresses,  has been set, and therefore the probability of a Missed big.

When the number of banks becomes very large, namely 30 to 40 Banks exist, the data of different pages in different banks are stored, and therefore the Missing rate significantly reduced. However, it is not practical, 30 to 40 banks in a data processing system to build. If a miss occurs, the signal will also go off / RAS raised and the DRAM needs to precharge return to reselect the row address. The invalidates the properties of the bank structure.

In the second method (2) described above, the MPU and the standard DRAM a high-speed cache Memory formed. In this case, the standard DRAM can be one have relatively low operating speed. Default- DRAMs with memory capacities of 4 MBit or 16 MBit are in Use. In a small system, such as B. a staff Computer, main memory can be done by just one or a few Standard DRAM chips are formed. The external formation of the High speed cache is in one small system in which the main memory of a standard DRAM cannot be formed as effectively. If the standard DRAM used as main memory is the Data transfer speed between the High-speed cache and main memory the number of data input / output ports of the standard DRAM limited that a bottleneck for increasing the Show system speed.

If the high-speed mode as pseudo-cache is used, its operating speed is lower than that of high speed cache, and it is difficult to implement the desired system management.

The formation of high speed cache memory (SRAM) in the DRAM has been proposed as a method to be a relative to create cheap and small system that the problem of  System performance degradation triggers when the interleave procedure or a high speed mode of operation is used. More specifically, a 1-chip memory is hierarchical Structure of a DRAM serving as main memory and one SRAM, which acts as a cache memory, has been introduced. The 1- Chip memory with such a hierarchical structure is called Cache DRAM (CDRAM).

Usually, a DRAM and an SRAM are on in a CDRAM integrated in the same chip. In the event of a cache hit, the SRAM accessed while DRAM in the event of a cache miss is addressed. The high-speed SRAM namely namely as cache memory and the DRAM with high Storage capacity used as main storage.

The so-called block size of the cache is called that number viewed by bits, their content in a transfer in SRAM to be written. As the block size increases, it generally increases the hit rate. However, if the cache is the same Size, the number of sets becomes inversely proportional to Block size decreases, and therefore the hit rate decreases. If the Cache size e.g. B. is 4 kbit and the block size is equal to 1024 is a set number of four. If the block size however, if the number is 32, the number of sets reaches 128. In a CDRAM The block size is therefore made too large, and the structure Cache hit rate cannot be particularly improved. A Structure that allows the block size to be reduced e.g. B. described in JP 1-146187.

Fig. 217 shows the overall structure of the CDRAM described in the cited document. As shown in Fig. 217, the CDRAM has a memory array 1 with a plurality of dynamic memory cells arranged in a matrix of rows and columns. The memory cell array 1 is divided into a plurality of memory blocks B # 1 to B # 4, each of which has a plurality of columns. The memory blocks B # 1 to B # 4 share word lines.

The CDRAM also has a row address buffer 2 , which accepts externally applied address signals A0 to An in response to an external row address strobe signal / RAS as row address signal RA and generates an internal row address signal, a column address buffer 4 which receives address signals A0 to An in response to an external column address -Sampling signal / CAS as column address signal CA, in order to generate an internal column address signal, adopts a row decoder 6 , which is dependent on the internal row address signal from row address buffer 2 , for generating a signal to select a corresponding row in memory cell array 1 , a word driver 8 , by Row selection signal is dependent on the row decoder 6 , for transmitting a driver signal to the selected row of the memory cell array 1 in order to put a word line corresponding to the specified row into a selected state, a sense amplifier group 10 for detecting, amplifying and locking of the data from the memory cells connected to the selected row in the memory cell array 1 , a data register circuit 14 having a plurality of data registers formed corresponding to each column of the memory cell array 1 , a transfer gate circuit 12 for transferring data between the respective column of the memory cell array and the data register circuit 14 , an IO gate 16 for decoding the internal column address signal from the column address buffer 4 in order to select a corresponding column of the memory cell array 1 or a corresponding data register in the data register circuit 14 , a block decoder 18 which is derived from an externally applied cache hit / miss signal CH is dependent on the selection of a corresponding block in the memory cell array 1 , an input buffer 24 and an output buffer 26 for input / output of data from or to the outside, a column decoder 20 for decoding the internal column address signal from the column address Reßbuffer 4 for generating a signal for selecting and connecting the corresponding column of the memory cell array 1 or the corresponding data register of the data register circuit 14 via the IO gate circuit 16 with the input buffer 24 and the output buffer 26 , and a read / write control circuit 28 for controlling the activation / deactivation of the input buffer 24 and the output buffer 26 in response to an externally applied write activation signal / WE and the column address scanning signal / CAS.

The transfer gate circuit 12 and the data register circuit 14 are each divided into blocks corresponding to blocks B # 1 to B # 4 of the memory cell array.

The CDRAM also has a gate circuit 22 , which is dependent on an externally applied cache hit / miss signal CH, for transmitting a column address signal, e.g. B. consists of the two least significant bits from the column address buffer 4 , as a block selection signal to the block decoder 18th The block decoder 18 is activated when the cache hit / miss signal CH with "L" indicates a cache miss. It decodes the applied block address signal to select a corresponding memory cell block in the memory cell array 1 and drives the transfer gate circuit 12 block by block to transfer data between the selected memory cell array blocks and the data register corresponding to the selected memory cell array block.

Fig. 218 shows the structure of a main portion of the semiconductor memory device of Fig. 217. Fig. 218 shows the structure in the boundary area between the two memory blocks B # 1 and B # 2.

As shown in FIG. 218, the sense amplifier group 10 has sense amplifiers SA # 1, which are each formed in accordance with the respective bit line pair BL, / BL of the memory block B # 1, and sense amplifiers SA # 2, which are each in accordance with the respective bit line pair BL, / BL of the memory block B # 2 are formed on. The sense amplifiers SA # 1 and SA # 2 differentially amplify the signals on the corresponding bit line pairs BL, / BL and lock the signals when they are activated.

The transfer gate circuit 12 has transfer gates DT # 1, which are each formed for the respective bit line pair BL, / BL of the memory block B # 1, and transfer gates DT # 2, which are each formed for the respective bit line pair BL, / BL of the memory block B # 2 , on. The transfer gates DT # 1 for the memory block B # 1 are driven independently of the transfer gates DT # 2 for the memory block B # 2. More specifically, the transfer gates DT # 1 for the memory block B # 1 are driven by a block decoder circuit BD # 1 formed for the memory block B # 1, while the transfer gates DT # 2 for the memory block B # 2 are driven by a block decoder circuit BD # 2 driven, which is formed for the memory block B # 2. Block decoder circuits BD # 1 and BD # 2 decode a block address given by the gate circuit 22 in the event of a cache miss shown in Fig. 217 and drive an associated transfer gate DT (# 1 or # 2) if that Block address indicates a corresponding memory block.

The data register circuit 14 has a register DR # 1 which is formed in accordance with the respective bit line pair BL, / BL of the memory block B # 1 in order to latch data which are applied via the transfer gate DT # 1, and a register DR # 2 which Receives and stores data on the bit line pair BL, / BL of the memory block B # 2 via the transfer gate DT # 2. The data registers DR (# 1 and # 2) have the structure of an inverter latch circuit.

The IO gate 16 has an IO gate TG, which is formed for the respective one of the bit line pairs BL, / BL of the memory blocks B # 1 and B # 2 and is dependent on a column selection signal from the column decoder 20 , for connecting the corresponding bit line pair BL, / BL with an internal data transmission line pair IO. The IO gate TG connects the bit line pair BL, / BL of the memory blocks B # 1 and B # 2 via the transfer gate circuit 12 and the data register circuit 14 to the internal data transmission line pair IO. If the transfer gate circuit is blocked (disconnected state), the IO gate TG connects the data register in the data register circuit 14 to the internal data transmission line pair IO. The operation of the semiconductor memory device shown in FIGS. 217 and 218 will now be described with reference to the signal diagram of FIG. 219.

The semiconductor memory device shown in Fig. 217 is used in a system having a CPU as an external processing unit and a controller for controlling access to the semiconductor memory device according to a request from the CPU. The controller has a tag memory for storing tag addresses of the data stored in the data register circuit, a comparison circuit for determining the match / mismatch between a tag address in the tag memory and a section of the address from the CPU ( CPU address) corresponding to the tag address to generate a signal CH indicating a cache hit / miss miss according to the result of the determination, and a control circuit (a state machine and an address multiplexer) for controlling the address transfer and access to it Semiconductor memory device according to the determination result of the comparison circuit.

An address is supplied from the CPU in synchronism with the system clock signal. When the CPU address determines data stored in the data register circuit 14 , the externally formed controller sets the cache hit signal CH to "H", which corresponds to the active state. At this time, if the row address strobe signal / RAS is actively low at "L", the external controller switches the column address strobe signal / CAS and extracts a column address CA from the CPU address and applies it to the semiconductor memory device.

In the semiconductor memory device, the applied column address signal CA is taken over by the column address buffer 4 , which generates an internal column address signal and applies it to the column decoder 20 . Because the cache hit signal CH is "H", the output from gate circuit 22 is "L", block decoder 18 is disabled (or block address transmission is disabled), and no block selection process is performed. In this case, the column selection process is carried out by the column decoder 20 , the corresponding data register is connected to the internal data line pair IO, and data is written or read into or from the selected data register. Whether data is written or read depends on the write activation signal / WE.

When the data requested by the CPU is stored in the data register circuit 14 , the cache hit signal CH is "H" and the corresponding data register of the data register circuit 14 is selected in accordance with the column address signal CA.

If the CPU address does not determine the data stored in the data register circuit 14 , the cache hit signal CH is in the "L" state. In the event of a cache miss, the external controller raises the / RAS and / CAS signals to "H" once, then lowers the row address strobe signal / RAS to "L", extracts the row address signal RA from the CPU address and applies it the semiconductor memory device.

In the semiconductor memory device, the row selection operation in the memory cell array 1 is carried out by the row address buffer 2 , the row decoder 6 and the word driver 8 in accordance with the row address signal RA applied, and the data of the memory cell connected to the selected row is acquired, amplified and locked by the sense amplifier group . In parallel with these operations, the column address strobe signal / CAS is lowered to "L", and the column address signal CA is extracted from the CPU address and applied to the semiconductor memory device. Because the cache hit signal CH is "L", the block decoder 18 is activated in the semiconductor memory device, and the block address signal of the applied column address signal is applied to the block decoder 18 .

The block decoder 18 decodes the block address and switches through all transfer gates which are formed in accordance with the memory block indicated by the block address. As a result, the data locked by the sense amplifier SA is transferred to the data register DR (# 1 or # 2) in the selected memory block. In parallel, the column decoder 20 carries out a column selection process, switches the transfer gate TG through in the IO gate circuit 16 and connects the data register DR to the internal data transmission line pair IO.

If a cache hit continues to occur, the line in the memory field 1 being kept in the selected state, the data register DR (# 1 or # 2) is then selected and addressed by the column decoder 20 .

By dividing the memory array into blocks and driving the data registers block by block as described above, the data register can be used as a cache. In this case, as shown in Fig. 220, the data registers TR # 1 to TR # 4, which are formed in accordance with the memory array blocks B # 1 to B # 4, can store data of different rows, thereby improving the cache hit rate. Furthermore, the block size of the cache can be made equal to the number of columns contained in the memory block. A suitable size of the cache block can thereby be realized.

In the semiconductor memory device described above, that DRAM field used as main memory, and the Data register circuitry can be used as a cache. Because the Data transfer between the main memory and the cache If blocks are executed, data with high Speed will be passed.

Now an application of the above is described Semiconductor memory device, i. H. of a CDRAM, on a Image data processing discussed.

Fig. 221 shows the structure of a general image data processing system. As shown in FIG. 221, the system includes a CPU 30 as a processing device, a CDRAM 32 , a cathode ray tube 34 as a display, and a CRT controller 36 for controlling data transfer between the CDRAM 32 and the cathode ray tube 34 . CPU 30 , CDRAM 32 and cathode ray tube 34 are connected to an internal data bus 38 . The data transmission is carried out via the internal data bus 38 .

The CDRAM 32 stores both image data to be displayed and data used by the CPU 30 and not displayed. When the image data is to be displayed on the CRT 34 , data transfer between the CDRAM 32 and the CRT 34 is performed under the control of the CRT controller 36 . The data read from the CDRAM 32 are applied to the cathode ray tube 34 via the data bus 38 and displayed on a screen, not shown.

When data stored in the CDRAM 32 is to be processed, the CPU 30 accesses the CDRAM 32 . At the same time, the CPU 30 can address the CDRAM 32 at high speed according to the result of the cache hit / miss determination, and thereby data can be processed at high speed. The data addressed by the CPU 30 should preferably be stored in the cache area of the CDRAM 32 . It is assumed that the CRT controller 36 reads data in the memory array 1 of the CDRAM 32 and transmits it to the cathode ray tube 34 for display.

In such a case, in the CDRAM having the structure described above, it is necessary that the row selection process and the column selection process are carried out under the control of the CRT controller 36 . The data in the memory field 1 are read out via the data register circuit 14 . Therefore, in this case, the data stored in the data register circuit used as the cache can be overwritten by data to be displayed on the CRT 34 . In this case, when image data generated by a video camera or similar device (not shown) or a similar device is to be written in the CDRAM 32 , the cache data stored in the data register circuit 14 is also overwritten by the image data which is to be written into the Main memory of the CDRAM 32 can be created.

Therefore, the CDRAM described above can write and read of main memory data are not executed, except for the Cache data is changed. Accordingly, it is difficult both the graphic data and data of one Application program that should not be shown in Save CDRAM.

In this structure of the CDRAM, block division is used when a DRAM main memory with a large storage capacity is used. In this case, a block structure is used in which the memory array shown in Fig. 218 or 220 is used as a block. In the block division, only the block having a selected word line is activated, and the other blocks are kept in an inactive state. The number of available data registers is therefore correspondingly small. This lowers the cache's efficiency.

If there is only one row of data registers as in the structure of the CDRAM shown in Fig. 218, only direct mapping (Direct Mapped) can be used as an implementable mapping method. In order to implement mapping using the set-associative method, it is necessary to form a plurality of data register lines. The direct mapping method and the set associative method cannot both be fulfilled. Only one of these mapping methods can be implemented.

In the CDRAM with the structure described above, an access can to a bit of data registers parallel to data transfer from DRAM field to data register are executed. In contrast to However, the DRAM section cannot support dual-port video RAM run in parallel with access to the SRAM without the Influence access to the SRAM field by using the DRAM Area and the SRAM area drives independently.  

The object of the invention is a CDRAM with a novel To create structure that includes reading and writing data allowed high speed. A CDRAM is also to be formed be particularly suitable for image data processing is. In addition, a CDRAM is to be formed, the one Data writing and data reading in and out of the DRAM enabled without affecting the cache data.

The object is achieved by the in claims 1, 2, 12, 13, 19, 20, 21, 24, 26, 27, 28, 30, 31, 32, 36, 38 or 40 labeled device. The method is in claim 15, 16, 18 or 29 marked. The invention Semiconductor memory device has a DRAM with a plurality of dynamic memory cells in a matrix of rows and columns are arranged, a SRAM array with a plurality of static memory cells that are in a matrix of rows and columns are arranged, and a data transmission means for simultaneous data transfer between one Plurality of selected memory cells of the DRAM and one A plurality of selected memory cells of the SRAM array. The semiconductor memory device according to the invention also has a control means for independently executing a Operational control related to the DRAM field and one Operational control related to the SRAM field and an agent for external and direct access to the Data transmission means.

Furthermore, the semiconductor memory device according to the invention a new structure to realize different characteristic functions.

In the semiconductor memory device according to the invention, the Data transfer between the DRAM field and the SRAM field by Use a page mode of the DRAM to run the DRAM field and the SRAM field to drive independently. Because direct access to the data transfer medium is possible (in other words, writing data to that and reading data from the data transmission means not executed over the SRAM field), the writing and  Reading data in the DRAM field without influencing that in the SRAM Field stored cache data to be executed. Therefore can both the image data and the cache data in the DRAM field get saved.

Further features and advantages of the invention result from the description of exemplary embodiments with reference to the Characters. From the figures show:

Fig. 1 is a block diagram showing the overall structure of a semiconductor memory device according to an embodiment of the invention;

FIG. 2 shows in table form the correspondence between the states of the control signals of the semiconductor memory device and the operating modes which are being executed at this time;

Fig. 3 is a signal diagram of the operation of Figure 1 semiconductor memory device of Figure in an SRAM power saving mode.

Fig. 4 is a signal chart of the operation of Figure 1 semiconductor memory device of Figure in an SRAM-aside mode.

FIG. 5 shows a structure of the SRAM control area of the semiconductor memory device of FIG. 1;

FIG. 6 shows an example of the structure of a buffer circuit in the semiconductor memory device of FIG. 1 that receives external signals;

FIG. 7 shows the structure of a buffer circuit in the semiconductor memory device of FIG. 1 that receives a chip enable signal;

Fig. 8 shows the signal diagram of a SRAM sense mode of the semiconductor memory device of Fig. 1;

Fig. 9 is the flow of data in the SRAM reading mode;

Fig. 10, the signal diagram of an SRAM write mode;

Fig. 11 shows the flow of data in the SRAM write mode;

Fig. 12, the signal diagram of a buffer read transfer mode;

FIG. 13 is the flow of data in the buffer read transfer mode;

Fig. 14, the signal diagram of a buffer write transfer mode;

FIG. 15 is the flow of data in the buffer write transfer mode;

Fig. 16, the signal diagram of a buffer read transfer / SRAM read mode;

Fig. 17 shows the data flow in Pufferlesetransfer- and SRAM read mode;

Fig. 18, the signal diagram of a Pufferschreibtransfer- and SRAM write mode;

Fig. 19 shows the data flow in Pufferschreibtransfer- and SRAM write mode;

Fig. 20, the signal diagram of a buffer read mode;

FIG. 21 is the flow of data in the buffer read mode;

Fig. 22, the signal diagram of the buffer write mode;

FIG. 23 is the flow of data in the buffer write mode;

Fig. 24 shows in table form the operations corresponding to the DRAM of the semiconductor memory device of Fig. 1 and the states of the control signals for implementing these operations;

Fig. 25, the signal diagram of a DRAM power saving mode;

Fig. 26, the signal diagram of a DRAM NOP mode;

Fig. 27, the signal diagram of a DRAM read transfer mode;

FIG. 28 is the flow of data in the DRAM read transfer mode;

Fig. 29, the signal diagram of the DRAM write transfer mode;

FIG. 30 is the flow of data in the DRAM write transfer mode;

FIG. 31 shows a structure for controlling operations related to the DRAM section in the semiconductor memory device of FIG. 1;

FIG. 32 is a chip layout of the semiconductor memory device according to the first embodiment of the invention;

FIG. 33 is the structure of the SRAM array portion of the semiconductor memory device according to the first embodiment of the invention;

FIG. 34 is the structure of the DRAM array region of the semiconductor memory device according to the first embodiment of the invention;

Fig. 35 shows the basic structure of a bidirectional data transmission circuit;

FIG. 36 is a signal diagram showing the principle of the data transfer process from the DRAM field to the SRAM field in the semiconductor memory device of FIG. 1;

FIG. 37A-37D schematically shows the data transfer operation from the DRAM array to the SRAM array in the semiconductor memory device according to the first embodiment of the invention;

38 shows the data transfer operation from the SRAM array to the DRAM array in the semiconductor memory device according to the first embodiment of the invention.

FIG. 39A-39D schematically shows the data transfer operation from the DRAM array to the SRAM array in the semiconductor memory device according to the first embodiment of the invention;

FIG. 40 is the structure of an IO region of the semiconductor memory device according to the first embodiment of the invention;

41 shows an example of the specific structure of a bi-directional data transfer circuit in the semiconductor memory device according to the first embodiment of the invention.

Fig. 42 is an example of an operation sequence in the semiconductor memory device according to the first embodiment of the invention;

., Which is represented by the signal diagram of Figure 42 Figure 43A and 43B schematically the operation;

Fig. 44 is another operation sequence of the semiconductor memory device according to the first embodiment of the invention;

Fig. 45 to the DRAM array transmits an example of the structure of a mask circuit for masking a transfer gate, the data;

Fig. 46 shows an example of the circuit structure for generating set and reset signals shown in Fig. 45;

Fig. 47 schematically shows the operation of the mask circuit of Fig. 45;

Fig. 48, the signal diagram of a DRAM self-refresh mode;

Fig. 49, the signal diagram of a Befehlsregistereinstellmodus;

Fig. 50 shows in table form the command data set in the command register setting mode of Fig. 49 and the content set at that time;

Fig. 51 shows the signal diagram of the operation of the masking circuit of Fig. 45;

Fig. 52, the signal diagram of the operation of the semiconductor memory device according to the first embodiment of the invention at the time of switching;

FIG. 53 is the structure of a portion which belongs to the Befehlsregistereinstellmodus the semiconductor memory device according to the first embodiment of the invention;

Figure 54 is an example of another structure of the portion that belongs to the Befehlsregistereinstellmodus the semiconductor memory device according to the first embodiment of the invention.

FIG. 55 is an example of an operation sequence of the semiconductor memory device employing the circuit structure of Fig. 54;

56 shows an example of the manner of distribution of address and command data to the command register and the address buffer in the semiconductor memory device according to the first embodiment of the invention.

FIG. 57 is an example of the structure of the data input / output portion in the semiconductor memory device according to the first embodiment of the invention;

Fig. 58 shows an example of the structure of the input circuit and the input control circuit of Fig. 57;

Fig. 59 shows an example of the structure of the output circuit of Fig. 57;

Fig. 60 shows a specific example of the structure of the latch circuit of Fig. 59;

Fig. 61 shows an example of the structure of the output control circuit of Fig. 57;

Fig. 62, the signal diagram of a latch output mode;

Fig. 63 shows the signal diagram of a register output mode;

FIG. 64A and 64B are signal diagrams of a transparent output mode;

FIG. 65A and 65B output timings of the output data in the transparent output mode;

FIG. 66A and 66B output timings of the output data in the register output mode;

FIG. 67A and 67B output timings of the output data in the latch output mode;

FIG. 68 is required conditions of external signals of the semiconductor memory device according to the first embodiment of the invention;

Fig. 69 shape and terminal assembly of a housing which accommodates the semiconductor memory device according to the first embodiment of the invention;

FIG. 70 is the overall structure of a semiconductor memory device according to a second embodiment of the invention;

Fig. 71 shows a structure for the K buffer and masking circuit of Fig. 70;

FIG. 72 is an example of the structure of the DRAM control circuit and the SRAM control circuit of Fig. 70;

Fig. 73 is a structure of the data input / output portion of the semiconductor memory device of Fig. 70;

Fig. 74 is an example of a data output operation sequence of the semiconductor memory device according to the second embodiment of the invention;

Figure 75 is an example of the structure of a memory system in the semiconductor memory device according to the second embodiment of the invention.

Fig. 76 advantages of the DQ controller which is used in the semiconductor memory device according to the second embodiment of the invention;

Figure 77 shows the correspondence between the cache and main memory of the memory system of Figure 76;

FIG. 78 is a structure, when a storage system having a bank structure using the semiconductor memory device according to the second embodiment of the invention is formed;

Fig. 79 shows the correspondence between the cache and the main memory of the memory system of Fig. 78;

Figure 80 is an example of the structure of a memory system in the semiconductor memory device according to the second embodiment of the invention.

Fig. 81 shows the correspondence between the cache and main memory of the memory system of Fig. 80;

Fig. 82 shows a structure for generating the DQ control signal when the memory system shown in Fig. 80 is formed;

Fig. 83, the functional structure of the semiconductor memory device according to the second embodiment of the invention;

Fig. 84 is an example of the structure of the bi-directional data transfer circuit in the semiconductor memory device according to the second embodiment of the invention;

Figure 85 in table form the correspondence between the states of the control signals belonging to the SRAM portion of the semiconductor memory device, and is realized at this time, the operation according to the second embodiment of the invention.

Fig. 86 the flow of data in the SRAM reading mode;

Fig. 87 the flow of data in the SRAM write mode;

Fig. 88 the flow of data in the buffer read transfer mode;

FIG. 89 the flow of data in the buffer write transfer mode;

Fig. 90 the flow of data in Pufferlesetransfer- and read mode;

Fig. 91 the flow of data in Pufferschreibtransfer- and write mode;

Fig. 92 the flow of data in the buffer read mode;

Fig. 93 shows the data flow in the buffer write mode;

Fig. 94 in table form the correspondence between the operations that correspond to the DRAM array, and the control signals for implementing these procedures;

Fig. 95 the flow of data in the DRAM read transfer mode;

Fig. 96, the signal diagram of the operation at the time of determination of the DRAM write transfer mode;

Fig. 97 is an example of the structure of a data processing system using the semiconductor memory device according to the second embodiment of the invention;

Fig. 98 the flow of data in the DRAM write transfer mode 1;

Figure 99 the flow of data in the DRAM write transfer mode 1 / read mode.

FIG. 100, the signal diagram of a DRAM read transfer mode;

FIG. 101, the signal diagram of the DRAM write transfer mode;

Figure 102 is an example of a circuit structure for generating a control signal for controlling the operation of a bi-directional data transfer circuit in a semiconductor memory device according to the second embodiment of the invention.

Figure 103 is an example of an operation sequence of the semiconductor memory device according to the second embodiment of the invention.

Fig. 104A and 104B schematically the flow of data in DWT1 mode and DWT2 mode of Fig.102.

FIG. 105 is a diagram illustrating the effect of DWT2 mode of Fig.104.

Fig. 106 the connection state with a tester, when the semiconductor memory device is tested for its function;

Fig 107 the state of external control signals in a Befehlsregistereinstellmodus in the semiconductor memory device according to the second embodiment of the invention.

Fig. 108 shows a structure of the command data shown in Fig. 107;

Fig. 109 shows in table form the correspondence between the command data shown in Fig. 108 and the operating modes set at that time;

FIG. 110 is a circuit structure of the system that controls the command data shown in FIG 108 in accordance with the internal operation of the semiconductor memory device.

Figure 111 is an example of the structure of a data processing system using the semiconductor memory device according to the second embodiment of the invention.

FIG. 112, the flow chart of a data read sequence under the condition that no allocation in the write-back mode of the semiconductor memory device is carried out according to the second embodiment of the invention;

FIG. 113, the flow chart of a data write sequence under the condition that no allocation in the write-back mode of the semiconductor memory device according to the second embodiment of the invention is carried out;

FIG. 114, the flow chart of a data read sequence under the condition that an assignment in the write-back mode of the semiconductor memory device according to the second embodiment of the invention is carried out;

Fig 115 the flow chart of a data write sequence with an assignment in the write-back mode of the semiconductor memory device according to the second embodiment of the invention.

Fig 116 the flow chart of the data reading order with an assignment in the write through mode of the semiconductor memory device according to the second embodiment of the invention.

FIG. 117, the flow chart of the data write sequence with an assignment in the write through mode of the semiconductor memory device according to the second embodiment of the invention;

FIG. 118, the flow chart of the data reading order with the proviso that no allocation in the write through mode of the semiconductor memory device according to the second embodiment of the invention is carried out;

FIG. 119, the flow chart of the data write sequence under the condition that no allocation in the write through mode of the semiconductor memory device according to the second embodiment of the invention is carried out;

FIG. 120 is an example of the structure of the bi-directional data transfer circuit in the semiconductor memory device according to the second embodiment of the invention;

Fig 121 the flow of data in the buffer write mode of the semiconductor memory device according to the second embodiment of the invention.

Fig. 122 the flow of data in the DRAM write transfer mode of the semiconductor memory device according to the second embodiment of the invention;

Fig. 123 shows a signal diagram of the set and reset operations of the mask register in the semiconductor memory device according to the second embodiment of the invention;

Fig. 124 shows a signal diagram of the set / reset operation, the mask data of the masking register in the semiconductor memory device according to the second embodiment of the invention;

FIG. 125, the special structure of a write data transfer buffer circuit in the bi-directional data transfer circuit, which is used in the semiconductor memory device according to the second embodiment of the invention;

Fig. 126 is a signal diagram of the operation of the write data transfer buffer circuit of Fig. 125;

FIG. 127, the special structure of a read data transfer buffer circuit in the bi-directional data transfer circuit, which is used in the semiconductor memory device according to the second embodiment of the invention;

Figure 128 is a signal diagram of the operation of the read data transfer buffer circuit of Figure 127;

Fig. 129 shows a structure for generating control signals used in the transfer buffer circuits of Figs. 125 and 127;

FIG. 130, the chip arrangement of the CDRAM in accordance with a third embodiment of the invention;

FIG. 131, the internal functional structure of the CDRAM in accordance with the third embodiment of the invention;

FIG. 132 in table form external control signals of the CDRAM from FIG. 131 and correspondingly defined commands;

FIG. 133 in table form external control signals of the CDRAM from FIG. 131 and correspondingly executed operations;

Fig. 134 is a signal diagram of the data read operation of the CDRAM of Fig. 131;

Fig. 135 is a signal diagram of the data read operation of the CDRAM of Fig. 131;

Fig. 136 is a signal diagram of the data read operation of the CDRAM of Fig. 131;

Fig. 137 is a signal diagram of the data read operation of the CDRAM of Fig. 131;

Fig. 138 is a signal diagram of the data read operation of the CDRAM of Fig. 131;

Fig. 139 is a signal diagram of the data read operation of the CDRAM of Fig. 131;

Fig. 140 is a signal diagram of the data read operation of the CDRAM of Fig. 131;

Fig. 141 is a signal diagram of the data read operation of the CDRAM of Fig. 131;

Fig. 142 is a signal diagram of the data read operation of the CDRAM of Fig. 131;

Fig. 143 is a signal diagram of the data write operation of the CDRAM of Fig. 131;

Fig. 144 is a signal diagram of the data write operation of the CDRAM of Fig. 131;

Fig. 145 is a signal diagram of the data write operation of the CDRAM of Fig. 131;

Fig. 146 is a signal diagram of the data write operation of the CDRAM of Fig. 131;

Fig. 147 is a signal diagram of the operation sequence when the CDRAM of Fig. 131 is turned on;

Fig. 148 is a signal diagram of the operation of the CDRAM of Fig. 131 upon a CPU reset;

Fig. 149 is a signal diagram of the operation of the CDRAM of Fig. 131 in sleep mode;

. Fig. 150 is a signal chart of the operation when the CDRAM of Fig 131 is released from the sleep mode;

Fig. 151 is a signal diagram of the instruction register read / write operation of the CDRAM of Fig. 131;

Fig. 152 shows a state transition of the CDRAM of Fig. 131;

Fig. 153A and 153B a truth table of external control signals for executing a command register reading / writing of the CDRAM and the command register reading / writing operation of the CDRAM of Fig 131st;

Fig. 154 Function and structure of the command register 00 h;

Fig. 155 Function and structure of the command register 01 h;

Fig. 156 Function and structure of the command register 02 h and 03 h;

Fig. 157 Function and structure of the command register 04 h and 05 h;

Fig. 158 Function and structure of the command registers 06 h and 07 h;

Fig. 159 Function and structure of the command register 10 h and 16 h;

Fig. 160 Function and structure of the command register 17 h and 18 h;

Fig. 161 in a table latencies in reading / writing the CDRAM of Fig. 131;

Fig. 162 shows various parameters of the input signals to the CDRAM of Fig. 131;

FIG. 163 shows various parameters of the output signals of the CDRAM from FIG. 131;

FIG. 164, the structure of a memory system that is formed from the CDRAM;

Fig. 165A and 165B schematic structure and operation of a data signal output portion of the CDRAM of Fig 164th;

FIG. 166, the structure of an improved signal output portion of the present invention;

Fig. 167 is a signal diagram of the operation of the signal output section of Fig. 166;

Fig. 168 shows a circuit structure for generating the control signals of Fig. 166;

Fig. 169 shows a modification of the circuit of Fig. 168;

FIG. 170 is a signal diagram of the operation of the circuit of Fig 169th;

When a special mode is set Figure 171 is a signal diagram of the operation.

When a special mode is set Figure 172 is a signal diagram of the operation.

FIG. 173, the structure of a test mode setting circuit;

FIG. 174 a further structure for the test mode setting circuit;

Fig. 175 shows an example of the structure of the counter shown in Figs. 173 and 174;

Fig. 176 is a signal diagram of the operation of the counter of Fig. 175;

Fig 177 the structure of a memory system with a synchronous self-refresh function according to the present invention.

Fig. 178 structures of sections related to refreshing the CDRAM of Fig. 177;

Fig. 179 is a signal diagram of the operation of the master section of Fig. 178;

Figure 180 is a signal diagram of the operation of the slave section of Fig 178th.

Fig. 181 shows a structure for generating the precharge completion signal of Fig. 178;

Fig. 182 is a signal diagram of the operation of the circuit of Fig. 181;

Fig. 183 shows a modification of the circuit of Fig. 181;

FIG. 184 is an example of the structure of the first arbiter of Fig 178th;

FIG. 185 is an example of the structure of the second arbiter of Fig 178th;

Fig. 186 shows an example of the structure of the RAS buffer and the refresh control circuit of Fig. 178;

FIG. 187, the structure of another embodiment of the refresh control system;

Figure 188 is another example of the structure of the storage system 99999 00070 552 001000280000000200012000285919988800040 0002004337740 00004 99880 of the synchronous self-refresh function.

Fig. 189 shows an example of the data transfer process between the DRAM field and the SRAM field;

FIG. 190 a second step of data transfer operation between the DRAM array and the SRAM array;

FIG. 191 a third step of the data transfer operation between the DRAM array and the SRAM array;

FIG. 192 a fourth step of the data transfer operation between the DRAM array and the SRAM array;

FIG. 193 a fifth step of the data transfer operation between the DRAM array and the SRAM array;

FIG. 194 a sixth step the data transfer operation between the DRAM array and the SRAM array;

FIG. 195 a seventh step the data transfer operation between the DRAM array and the SRAM array;

FIG. 196 an eighth step of the data transfer operation between the DRAM array and the SRAM array;

FIG. 197 a ninth step of the data transfer operation between the DRAM array and the SRAM array;

FIG. 198 a tenth step of the data transfer operation between the DRAM array and the SRAM array;

FIG. 199 an eleventh step the data transfer operation between the DRAM array and the SRAM array;

FIG. 200 a twelfth step of the data transfer operation between the DRAM array and the SRAM array;

Fig. 201 is a signal diagram of the data transfer sequence between the DRAM field and the SRAM field;

FIG. 202, the data transmission sequence between the DRAM array and the SRAM array;

Fig. 203 is a signal diagram of the data transfer process between the DRAM field and the SRAM field;

Fig. 204 shows a signal diagram of the data transfer operation between the DRAM array and the SRAM array;

Fig. 205 shows an example of the correspondence between the read transfer command and the external control signals;

FIG. 206 is a further example of the structure of the data transfer circuit from the SRAM array to the DRAM array;

Figure 207 is an example of an image processing system using the CDRAM of the present invention.

Fig. 208 schematically illustrates the operation of the image processing system of Fig. 207;

Fig. 209 is a signal diagram of the access sequence of the CDRAM in the image processing system of Fig. 207;

Fig. 210 shows a signal diagram of the access sequence of the CDRAM in the image processing system of FIG 207th;

Figure 211 is a signal diagram of the sequence of operations when writing video data to the CDRAM;

Fig. 212 is a signal diagram of the video data write to CDRAM and DRAM;

Fig. 213 shows a signal diagram of the operation for reading video data from the SRAM and CDRAM;

Fig. 214 is a signal diagram of the operation for writing video data into the SRAM and CDRAM;

Figure 215 is a signal diagram of the read-write Nodify operation for video data for the SRAM and CDRAM.

Fig. 216 is a signal diagram of the operation for writing video data into the SRAM / DRAM and CDRAM;

FIG. 217, the entire structure of a semiconductor memory device having a cache;

Fig. 218 shows a structure of the main portion of the semiconductor memory device of Fig. 217;

Fig. 219 shows a signal diagram of the operation sequence of the semiconductor memory device having a cache;

Figure 220 schematically shows the data transfer in the semiconductor memory device having a cache. and

FIG. 221 is an example of the structure of a data processing system having a display that uses a semiconductor memory device having a cache.

Embodiment 2

Fig. 1 is a block diagram showing the overall structure of a semiconductor memory device according to a first embodiment of the invention. The semiconductor memory device has a DRAM section and an SRAM section, which is used as a cache memory. The semiconductor memory device is therefore referred to in the following description as a semiconductor memory device with a cache (CDRAM).

As shown in FIG. 1, the DRAM 100 has a DRAM array 102 with a plurality of dynamic memory cells arranged in a matrix of rows and columns, an SRAM array 104 with a plurality of static memory cells arranged in one Array of rows and columns are arranged, and a data transfer circuit 106 for transferring data between the DRAM array 102 and the SRAM array 104 . The CDRAM 100 has a structure that enables input / output of data of four bits each. Therefore, the DRAM array 102 comprises four memory levels 102 a, 102 b, 102 c and 102 d. The memory levels 102 a to 102 d of the DRAM field each correspond to different ones of the data bits that are input / output at once.

The SRAM array 104 similarly has four memory levels 104 a, 104 b, 104 c and 104 d. The data transmission circuit 106 also comprises four levels 106 a, 106 b, 106 c and 106 d in order to transfer data level by level between the memory levels 102 a to 102 d of the DRAM field and the memory levels 104 a to 104 d of the SRAM field. The CDRAM 100 has a DRAM address buffer 108 which receives externally applied DRAM addresses Ad0 to Ad11 for generating internal addresses, a row decoder 110 which has internal row addresses ROW1 to ROW11 from the DRAM address buffer 108 for selecting a corresponding row of the DRAM field 100 receives a column decoder 112 that receives predetermined bits of the internal column address signals from the DRAM address buffer, that is, column block addresses Col1 through 9 for simultaneously selecting a plurality of columns (16 bits of memory cells in this embodiment) in the DRAM array, a sense amplifier for detection and amplification of data of the memory cells selected in the DRAM array and a 10 controller for transferring data between the selected memory cell in the DRAM array 102 and the data transfer circuit to drive the DRAM array. In Fig. 1, the sense amplifier 10 and the control are shown as a block 114.

DRAM address buffer 108 receives the row and column addresses in a multiplexed manner. Four data bits of addresses Ad0 to Ad3 are used as commands for setting the data transfer mode in the data transfer circuit and for setting / resetting the masking data when masking is to be carried out.

The CDRAM 100 also has an SRAM address buffer 116 which receives externally applied SRAM address signals As0 to As11 for generating internal addresses, a row decoder 118 which decodes addresses As4 to As11 from the SRAM address buffer 116 , for selecting a corresponding row in the SRAM Field 104 , a column decoder 120 for decoding column addresses As0 to As3 from SRAM address buffer 116 to select a corresponding column in SRAM field 104 and a corresponding transfer gate of data transmission circuit 106 , and a 10 circuit for acquiring and amplifying data of the selected one Memory cell of the SRAM array 104 and for connecting the selected column of the SRAM array 104 and the selected gate to an internal data bus by an output signal from the column decoder 120 .

The sense amplifier and 10 circuitry for the SRAM are shown as a block 122 . One line of SRAM field 104 is 16 bits. The data transfer is performed simultaneously between 16 bits of a selected row of the SRAM array and the data transfer circuit 106 with 16 transfer gates. Namely, in the CDRAM, 16 bits of data are transferred for one memory level, and therefore a total of 64 bits of data can be transferred simultaneously.

The CDRAM also has a K buffer 124 for receiving an externally applied clock signal K which, for. B. represents a system clock signal for generating an internal clock signal, a clock signal masking circuit 126 for providing a masking function for the internal clock signal from the K buffer 124 in accordance with an externally applied masking signal CMd, a DRAM control circuit 128 , the externally applied control signals RAS #, CAS # and DTD # in sync with the clock signal from the clock signal masking circuit 126 takes over a clock signal masking circuit 130 to provide a masking function for the internal clock signal from the K buffer 124 in to generate the necessary control signals according to the states of the respective signals In accordance with an external applied control signal CMs, an SRAM control circuit 132 for taking on externally applied control signals E #, WE #, CC1 # and CC2 # corresponding to the internal clock signal from the clock signal masking circuit 124 , for generating a control signal for controlling the operation of the data transferred Rage circuit 106 , the SRAM array 104 and an input / output section described later according to the combinations of the states of the respective control signals, a main amplifier circuit 130 , which is activated in synchronism with an externally applied control signal G #, for generating an external read value from the value on the internal Data bus 123 , a Din buffer circuit 134 for accepting external write data in synchronism with the clock signal under the control of the SRAM control circuit 132 for generating internal write data, and a mask setting circuit 136 for accepting externally applied mask data for performing a masking function with respect to the transfer of the write data from the Din Buffer circuit 134 to internal data line 123 . The mask setting circuit 136 also accepts the masking data in synchronization with the clock signal under the control of the SRAM control circuit 132 .

The CDRAM 100 can change the structure of the data input / output. It has a DQ separation structure in which input data (write data) D and output data Q are transmitted via different connections, and a masking write mode in which write data D and read data (output data) Q are transmitted via the same connections. Masking of the write data is only possible in masking write mode, in which the data input and the data output are carried out via the same connections. Ports to which write data D0 to D3 are applied in the DQ separation arrangement are used in the mask write mode as ports for receiving mask data (mask activations) M0 to M3. Although this is not shown in the drawings for the sake of simplicity, the setting of the connections is carried out by a command register which will be described later.

[Definition of external control signals]

In the CDRAM 100 shown in FIG. 1, the input of data and the acceptance of the external control signals are carried out synchronously with the external clock signal K. The external control signals are all supplied in the form of pulses. The operating mode is determined as a function of the combinations of the states of the external control signals with the rising edge of the external clock signal. The input of the external control signal G # is carried out asynchronously to the clock signal K. Various external control signals are described below.

Master clock signal K: The master clock signal K defines the basic clocking, ie the clock positions for accepting the input signals, and the operating clock frequency of the CDRAM 100 . The clock signal parameters of the respective necessary external signals (except G #, which will be described later) are defined using the rising or falling edge of the master clock signal K as a reference.

DRAM clock mask signal CMd: The DRAM clock mask signal CMd controls the transfer of the internal DRAM master clock signal generated by the K buffer 124 . If the DRAM clock mask signal is in an active state with the rising edge of the external clock signal K, the generation of the internal DRAM master clock signal is interrupted in the next clock cycle. Accordingly, the operation for taking over the control signals of the DRAM section is interrupted in the next cycle, whereby the power consumption in the DRAM section is reduced.

Row address strobe signal RAS #: The row address strobe signal RAS # is used with the master clock signal K (depending on the states of the signals CMd, CAS # and DTD # at this time) to activate the DRAM section. More specifically, it triggers the latching of the DRAM row address, the selection of a row in DRAM 102 and the start of a precharge cycle to set the DRAM section to the initial state, and it can also be used to transfer data between the DRAM and the data transfer circuit, set the Data in the instruction registers, starting the self-refresh cycle, generating a DRAM-NOP cycle and interrupting the operation (power saving state) of the DRAM section are used. Namely, the row address strobe signal RAS # defines the basic duty cycle in the DRAM section.

Column address strobe signal CAS #: The column address strobe signal CAS # is used to lock together with the master clock signal K. the column address used for the DRAM. If in the DRAM Access cycle previously applied the row address strobe signal RAS # has been created by the successive Column address strobe signal CAS # the data transfer from the Data transmission circuit to the DRAM field or from the DRAM field to the data transmission circuit according to a control signal DTD #, which will be described later.

Data transfer determination signal DTD #: The data transfer determination signal DTD # determines the data transfer and its direction between the DRAM field 102 and the data transfer circuit 106 . If the row address strobe signal RAS # was "L" in the previous cycle, a DRAM write transfer cycle is carried out in which data is transferred from the data transmission circuit to the DRAM array when the column address strobe signal CAS # and the data transmission determination signal DTD # with the rising edge of the master clock signal K both lie at "L". When the data transfer determination signal DTD # is "H", data transfer from the DRAM array to the data transfer circuit is carried out. When the data transfer designation signal DTD # falls to "L" in synchronism with the row address strobe signal RAS #, the DRAM enters the precharge mode and access to the entire DRAM section is blocked until the precharge cycle is completed.

DRAM addresses Ad0 to Ad11: The DRAM field 102 has a memory capacity of 16 MBit (16 MegaBits). A DRAM memory layer has a structure with 4k rows * 64 columns * 16 blocks. The DRAM address bits Ad0 to Ad11 are supplied as DRAM row addresses and DRAM column addresses in a multiplexed manner. When the row address strobe signal RAS # is "L" with the rising edge of the master clock signal K, the DRAM address bits Ad0 to Ad11 are adopted as the row address which determines a row of the DRAM field. When the column address strobe signal CAS # is "L" with the rising edge of the master clock signal K, the DRAM address bits Ad4 through Ad9 are used as the block address for specifying 16 bits of memory cells (one bit of each of the 16 blocks). When the row address strobe signal RAS # is "L" with the rising edge of the master clock signal K, the refresh address can be set when refreshing is instructed.

SRAM clock mask signal CMs: The SRAM clock mask signal CMs controls the transfer of an internal SRAM master clock signal (which is generated by the K buffer 124 ). When the SRAM clock mask signal is in an active state with the rising edge of the master clock signal K, the internal SRAM master clock signal is turned off in the next clock cycle and the SRAM section maintains the state of the previous cycle. The SRAM clock mask signal is also used to continuously hold the same input / output data.

Chip activation signal E #: The chip activation signal E # controls the operation of the SRAM section. If that Chip activation signal E # with the rising edge of the Master clock signal K is at "H", the SRAM section to an unselected state in this cycle (Waiting state) set. If the chip activation signal E # with the rising edge of the master clock signal K (provided the SRAM clock mask signal is in the previous cycle to "L"), the SRAM section in this Cycle activated. If that (described later) Output enable signal G # is at "L" controls that  Chip activation signal E # the output impedance, and it can be a Writing and reading data in a common IO structure be carried out.

Write activation signal WE #: The write activation signal WE # controls the write and read operations in the SRAM section and the Data transmission circuit. If the chip activation signal E # with the rising edge of the master clock signal K at "L" is reading data from the Data transmission circuit executed. It will be a reading of Data from the SRAM field and / or a data transfer from the Data transfer circuit to SRAM field performed if that Write activation signal WE # is at "H" (depending on the States of the control signals CC1 # and CC2 # that later to be discribed). If the write activation signal WE # at this time is on "L", a letter from Data in the data transmission circuits, a write of Data in the selected memory cells of the SRAM field or a transfer of data from the SRAM field to the Data transmission circuit carried out (depending on the Control signals CC1 # and CC2 #).

Control clock signals CC1 # and CC2 #: These control clock signals CC1 # and CC2 # control access to the SRAM section and the Access to the data transmission circuit. If that Chip activation signal E # with the rising edge of the Master clock signal K is at "L", the one to be executed Operating mode by the control clock signals CC1 # and CC2 # certainly. The operating mode is briefly described below. The details will be explained later.

CC1 # = CC2 # = "L": A buffer read / write cycle (WE # = H / L) executed, and reading data from the Data transmission circuit or a writing of data in the Data transmission circuit is performed.

CC1 # = "L" and CC2 # = "H": It becomes a Buffer read / write transfer cycle and an SRAM Read / write cycle (WE # = H / L) executed. In this cycle  a data transmission between the data transmission circuit and the SRAM field and reading or writing data from the or carried out in the SRAM field. The writing operation or Reading operation is determined depending on whether that Write enable signal WE # is at "H" or "L".

CC1 # = "H" and CC2 # = "L": It becomes one Buffer read / write transfer cycle (WE # = H / L) executed. It is a data transfer between the SRAM field and the Data transmission circuit performed.

CC1 # = CC2 # = "H": An SRAM read / write cycle (WE # = H / L) executed. A data read / write operation for the SRAM Field carried out.

SRAM addresses As0 to As11: The SRAM field has four memory levels, each comprising memory cells in 256 rows and 16 columns. When the SRAM field is used as a cache, the block size of the cache is 16 _* 4 (4 bits for input / output). The SRAM address bits As0 to As3 are used as the block address to select a bit in a cache block, while the SRAM address bits As4 to As11 are used as the row address to select a row in the SRAM field.

Output enable signal G #: The output enable signal G # is supplied asynchronously to the master clock signal K. Do that Output enable signal G # level "H", the output both in DQ disconnect mode and in DQ mode high impedance offset.

Input / output data DQO to DQ3: The input / output data DQO to DQ3 represent the data of the CDRAM, if by the Command register the DQ mode is selected. The state of the respective values is determined by the output activation signal G # controlled asynchronously to the master clock signal K. The output of Data is loaded depending on the content of the command register (the will be described later) in a transparent mode, latch Mode or register mode executed.  

Input signals D0 to D3: These are input data if through the Command register the DQ disconnect mode is selected. At the Data writing, such as B. in the write buffer cycle or write SRAM mode, the input data D0 to D3 with the rising edge of the master clock signal K locked.

Mask activation signals M0 to M3: These signals are activated when DQ mode through the command register is set. The mask activation signals M0 to M3 correspond to the input / output data DQ0 to DQ3 and determine whether the corresponding DQ bit should be masked or not. The Setting the masking data is determined by the states of the Mask activation signals M0 to M3 with increasing Edge of the master clock signal K fixed. When writing data into the data transmission circuit or the SRAM field in the SRAM Write cycle or buffer write cycle can be the one you want Input data are masked.

As can be seen from the above description of the control signals, the control of the operations related to the DRAM section and the control of the operations related to the SRAM section of the CDRAM 100 are carried out independently of each other. Direct data writing to and direct data reading from the data transmission circuit is possible. Therefore, the DRAM section and the SRAM section can be driven independently from each other to simplify the control. Data transmission using a high-speed mode, such as e.g. B. the page mode of the DRAM can be implemented, the access time in the event of a cache miss can be reduced and a burst mode (block mode) can be implemented.

Because the data transmission circuit 106 can be directly addressed externally, the data stored in the SRAM field 104 are not influenced at all when the data transmission circuit is accessed directly from the outside. Therefore, both image data and cache data (data used by the CPU that is an external processing unit) can be stored in the DRAM array 102 .

As shown in FIG. 1, the data transmission circuit 106 has 16 transfer gates. Each transfer gate has a read transfer buffer for transferring data from the DRAM array 102 to the SRAM array or an input / output section, an intermediate register 142 for storing write data of the SRAM array 104 or the internal data bus 123 , a write transfer buffer 144 for transferring data, stored in the intermediate register 142 to the DRAM field, and a masking register 146 for masking the data transfer from the write transfer buffer 144 to the DRAM field.

As shown in FIG. 1, the CDRAM 100 receives the ground potential Vss and the supply potential Vcc. The supply potential Vcc or an internally lowered supply potential can be used as the internal operating supply voltage of the CDRAM. Various operations that can be performed by the CDRAM are described below, followed by a detailed description of the structures of various sections of the CDRAM.

Fig. 2 is a table showing the states of the control signals for setting operations relating to the SRAM portion. Fig. 2 shows the states of various control signals for the rising edge of the master clock signal K and operating cycles (operating modes) which are being executed at this time. In Fig. 2, the reference character "X" represents an arbitrary state. As can be seen from Fig. 2, the states of the control signals CMd, RAS #, CAS # and DTD #, which control the processes that affect the DRAM field , not defined, but set arbitrarily if an operation relating to the SRAM field is to be controlled. Control of operations related to the SRAM array is performed by the SRAM control circuit 132 shown in FIG. 1. The SRAM array operating cycles include an SRAM power save cycle to interrupt one cycle of the SRAM master clock signal, an SRAM decommission cycle to put the output section in a high impedance state, an SRAM read cycle to read data from the SRAM array and an SRAM write cycle for writing data to the SRAM array.

The operations related to the SRAM section also include a buffer read transfer cycle, a buffer read transfer and read cycle, and a buffer write transfer and write cycle for transferring data between the SRAM array and the data transfer circuit, a buffer read cycle, and a buffer write cycle for direct access to the data transfer circuit on. Each of the operating cycles shown in Fig. 2 will now be described.

[SRAM system] [SRAM power save mode]

In the SRAM power saving cycle, the SRAM master clock signal is interrupted for the period of a cycle. Control signals are not transferred to the SRAM control circuit 132 in synchronism with the clock signal. The SRAM sense amplifier maintains the state of the previous cycle. The output buffer remains in the state at this time. Data can be output continuously.

For the SRAM power saving cycle, the SRAM clock mask signal CMs with a rising edge of the master clock signal K. "H" set. In the next clock cycle, the SRAM enters the SRAM Energy saving cycle. If the SRAM clock mask signal CMs with the rising edge of the master clock signal K at "L" is located and the chip activation signal E # is set to "L" is, and both the write enable signal WE # and that Control clock signals CC1 # and CC2 # with the rising edge of the Master clock signal K of the following cycle will be "H" the SRAM read mode is set. In this case, the data of the SRAM with the rising edge of the next master Clock signal K read. The data read at this time  are issued continuously if at this point the SRAM power saving mode is active.

More specifically, as shown in FIG. 3, the SRAM power save mode starts from the second cycle of the master clock signal K when the SRAM clock mask signal CMs is "H" in the first cycle of the master clock signal K. In the first cycle of the master clock signal K, the SRAM has not yet entered the power saving mode, and therefore the SRAM read mode is determined at this point in time depending on the combination of the chip activation signal E #, the write activation signal WE # and the control clock signals CC1 # and CC2 #. the selection of the memory cell in the SRAM field is carried out in accordance with the SRAM addresses As0 to As11, which are supplied to the SRAM address buffer 116 at this point in time, and the data of the selected memory cell occur with the rising edge of the master clock signal K. Because the SRAM enters the power saving mode from the second cycle of the master clock signal K and the SRAM master clock signal is not supplied, the internal operation is stopped and its state is maintained. The output buffer (main amplifier) holds this state until the next SRAM master clock signal is applied, and therefore the value Q1, which has set itself on the rising edge of the second cycle of the master clock signal K, is continuously output.

By setting the SRAM clock mask signal CMs to "L" is with the rising edge of the fourth cycle of the master Clock signal K the SRAM from the rising edge of the fifth Cycle of the next master clock signal K again from the Power saving mode enabled.

The SRAM read cycle is determined again by combining the states of the chip activation signal E #, the write activation signal WE # and the control clock signals CC1 # and CC2 # with the rising edge of the fifth cycle of the master clock signal K. Because the SRAM has been released from the power saving mode in the fifth cycle of the master clock signal K, the output buffer (the main amplifier in FIG. 1), which has continuously output the same value Q1 up to now, becomes high once by the application of the clock signal K Impedance offset. The timing for the occurrence of the output data will be described in detail later.

Corresponding to the SRAM addresses As0 to As11, which are in the fifth Cycle of the master clock signal K are applied Memory cells are selected in the SRAM field and data are extracted from the selected memory cells read.

With the rising edge of the sixth cycle of the master Clock signal K, the output value Q becomes a stable state set. With the rising edge of the fifth cycle of the Master clock signal K is the SRAM Clock mask signal CMs at "H", and that through the sixth Cycle of the master clock signal K is defined cycle Subject to power saving mode. The output value Q2 issued continuously. This condition will last maintain how the SRAM clock mask signal CMs at "H" lies. By lowering the SRAM clock mask signal CMs "L" with the rising edge of the 13th cycle of the master Clock signal K is in the 14th cycle of the master clock signal SRAM released from power saving mode. This will be the exit Q placed in a high impedance state.

As described above, by using the SRAM Power saving mode stopped the operation of the SRAM section be, and the power consumption due to the operation in sync with Clock signal K can be reduced in the SRAM section.

[SRAM decommissioning mode]

The SRAM quiescent cycle places the output buffer (main amplifier 138 in FIG. 1) in a high output impedance state. For the SRAM set mode, the SRAM clock mask signal CMs is set to "L" with the rising edge of the master clock signal K, and the chip activation signal E # is set to "H" with the rising edge of the next master clock signal K. With this, it takes the SRAM decommissioning mode from the next cycle, the data transmission and the data input / output of the SRAM field are deactivated, and it assumes a state corresponding to a high output impedance. The SRAM quiesce mode allows the output impedance to be placed in the high output impedance state, with the SRAM region effectively in an unselected state (non-operational state). Therefore, erroneous overwriting of data in the SRAM that was read in the previous cycle can be prevented when switching from data reading to data writing operation, and erroneous data writing due to a collision of newly created write data and the read data can be avoided.

As shown in the signal diagram of FIG. 4, the SRAM clock mask signal CMs is at "L" with the rising edge of the first cycle of the master clock signal K. At this time, the chip activation signal E # is at "L" and the write activation signal WE # and the control clock signals CC1 # and CC2 # are at "H". therefore, the SRAM read mode is set. The SRAM address bits As0 to As11 applied in the first cycle of the master clock signal K are taken over, and the value Q1 of the memory cell corresponding to the address (indicated as C1 in FIG. 4) is read.

If the chip activation signal E # in the second cycle of the master Clock signal K is raised to "H", the SRAM enters the SRAM decommissioning mode. In this state, the SRAM Section is set to the unselected state, and the Output turns into a in the third cycle of the master clock signal K High impedance state offset.

When the chip activation signal E # drops to "L", the SRAM decommissioning mode is released, the SRAM read mode is controlled according to the states of the other control signals WE #, CC1 # and CC2 # at this time, data is changed according to the SRAM currently applied Address (C2 in Fig. 4) read and the output value Q2 is output.

If E # in the sixth cycle of the master clock signal K the level "H" reached, the SRAM occurs from the fifth cycle of the master  Clock signal K in the SRAM set mode. The SRAM Decommissioning mode is maintained as long as that Chip activation signal E # is "H" (provided that SRAM clock mask signal CMs is at "L"), and the State of high output impedance is maintained.

More specifically, in the SRAM decommissioning mode, the SRAM section becomes for the period of one cycle of the master clock signal K in the unselected state.

Fig. 5 shows the structure of the sections relating to the SRAM power save mode and the SRAM set mode. The structure shown in FIG. 5 corresponds to the structure of the SRAM control circuit 132 and the main amplifier 138 of the clock masking circuit 130 in the structure of FIG. 1. As shown in FIG. 5, the SRAM control circuit 132 has a K buffer , which receives the master clock signal K and generates an internal clock signal Ki, and a masking circuit 130 , which is dependent on the internal clock signal Ki and the SRAM clock mask signal CMs, for generating an SRAM master clock signal SK.

The masking circuit 130 has a shift register 152 , since it depends on the internal clock signal Ki, to achieve a delay of one clock cycle period for the SRAM clock masking signal CMs, and a gate circuit 164 , which depends on the clock masking signal CMsR from the shift register 152 , for selectively passing the internal clock signal Ki on. The gate circuit 164 is e.g. B. formed by a transfer gate with a p-channel MOS transistor. When the clock mask signal CMsR is "H", the transmission of the internal clock signal Ki is blocked. Gate circuit 164 may be formed using a logic gate. The SRAM master clock signal SK is generated by the masking circuit 130 .

The SRAM control circuit 132 has an E buffer 154 , which is dependent on the SRAM clock signal SK, for locking the chip activation signal E #, a WE buffer 156 , which is dependent on the SRAM master clock signal SK and the internal chip activation signal E from the E buffer is dependent on locking the write activation signal WE # and generating an internal write activation signal WE and a CC1 buffer 158 and a CC2 buffer 160 , which are dependent on the internal chip activation signal E and the SRAM master clock signal SK, for generating internal control clock signal CC1 and CC2 on.

The SRAM control circuit 132 further comprises a control signal generating circuit 166 which is activated in dependence on the internal chip activation signal E from the E buffer, the clock position of which is defined by the SRAM master clock signal SK, for generating the necessary control signals in accordance with combinations of the States of the write enable signal WE and the control clock signals CC1 and CC2, which are supplied from the buffers 156 , 158 and 160 .

The control signal generating circuit 166 generates a driver control signal for driving the SRAM array and a data transfer control signal for driving the data transfer circuit. In the data transfer between the SRAM array and the data transfer circuit, the time period of the transfer is determined by the master clock signal in order to transfer the data securely.

The CDRAM further includes a G buffer 162 which receives the output enable signal G # for generating an internal output enable signal G and an output control circuit 168 which is dependent on the internal output enable signal G and a control signal from the control signal generating circuit 166 for controlling the main amplifier 138 . In the structure shown in FIG. 1, the output control circuit 168 is formed in the SRAM control circuit. The output control circuit 168 includes a gate circuit 176 which receives the internal output enable signal G from the G buffer 162 and the enable signal E1 from the control signal generating circuit, and a gate circuit 178 which receives the output signal from the gate circuit 176 and the clock mask signal CMsR from the shift register 152 . on. Gate circuit 176 generates a "H" level signal when the signals applied to its two inputs are at "L". Gate circuit 178 generates a "H" level signal when at least one of the input signals reaches "H" level.

The main amplifier 138 has an inverter circuit 172 for inverting the signal on an internal data bus 123 a (1-bit data line of the internal data bus 123 from FIG. 1), a 3-state inverter circuit 170 , which is a function of an output signal of the output control circuit 168 is activated, an inverter circuit 174 and a connection gate 173 for connecting the output of the inverter circuit 170 to the input of the inverter circuit 174 in accordance with the internal clock mask signal CMsR. The output signal from inverter circuit 174 is applied to an input of 3-state inverter circuit 170 . When the clock mask signal CMsR is "H", the inverter circuit 170 and the inverter circuit 174 form a latch circuit.

The operation will now be briefly described. The shift register 152 outputs a clock mask signal CMsR with a delay of one clock cycle. In response to this delayed by one clock cycle clock mask signal CMSR the gate circuit 164 may be by the internal clock signal Ki. Accordingly, if the SRAM clock mask signal CMs is generated externally, the transmission of the SRAM master clock signal SK to the SRAM control circuit 132 is blocked in the next clock cycle. The operating timing of the control signal generating circuit 166 is defined by the SRAM master clock signal SK and generates the necessary internal control signals. The buffer circuits 154 , 156 , 158 and 160 lock out the applied data in accordance with the internal chip activation signal E and the SRAM master clock signal SK. If no SRAM master clock signal SK is supplied, none of the buffers performs a new locking.

Similarly, if the chip activation signal E is not generated, the buffers will not work. If the chip activation signal E is "H", which indicates the unselected state, the buffers 156 , 158 and 160 do not work. At this time, the control signal generating circuit 166 also does not work.

The SRAM master clock signal SK is masked by this SRAM clock masking signal CMs from the next cycle after the generation of the SRAM clock masking signal CMs. Therefore, when the SRAM clock mask signal CMs is externally applied, the internal chip enable signal E and the SRAM master clock signal SK are generated in this cycle, and therefore an operation is carried out in accordance with the applied control signals. No internal control signal is generated in the next cycle and control signal generation circuit 166 maintains the state of the previous cycle. The control signal generation circuit 166 delays the chip activation signal E by a predetermined period of time and generates an internal chip activation signal E1. The output clock can thus be set precisely (because the generation clock position is defined by the SRAM master clock signal SK).

If the clock mask signal CMsR is "H", the 3-state inverter circuit 170 is in the operating state and the connection gate 173 also becomes conductive. As a result, the inverter circuits 170 and 174 form a latch circuit. Although the output signal from G buffer 162 is in the active state, the output value DQ through inverter circuits 170 and 174 remains the same value. When the chip activation signal E # falls to "L", the internal chip activation signal E also falls to "L", the control signal generating circuit 166 initializes the chip activation signal E1 to "H" and lowers it again to "L" after a predetermined period of time. When the clock mask signal CMsR is at "L", the inverter circuit 170 is placed in a high impedance output state, and if the internal output enable signal G is at "L", the inverter circuit 170 is put into the operating state according to the internal chip enable signal E1 after one predetermined period of time has passed. As a result, new output data appear.

As described above, the Output impedance state by the clock mask signal CMsR and the chip activation signal E # can be set.

Fig. 6 shows an example of the structure of the buffer circuit of Fig. 5. Fig. 6 shows a structure of the SRAM address buffer, which is not shown in Fig. 5. Buffers 156 , 158 and 160 have the same structure as the buffer shown in FIG. 6. As shown in Fig. 6, the buffer 116 has a 3-state inverter circuit 7011 whose output state is determined by the master clock signal K, an inverter circuit 7013 which receives an output signal from the inverter circuit 7011 , and a 3-state Inverter circuit 7014 , which is put into an output activation state in response to the internal chip activation signal E. The output of inverter circuit 7013 is connected to an input of inverter circuit 7014 . The output of inverter circuit 7014 is connected to an input of inverter circuit 7013 . The inverter circuit 7013 generates an internal address signal intAs. The operation will now be briefly described.

The 3-state inverter circuit 7011 is brought into the active state when the internal SRAM master clock signal SK is at "L" and inverts an externally applied address As and passes it through. When the SRAM master clock signal SK is "H", the inverter circuit 7011 is put in a high impedance output state. Therefore, with the rising edge of the SRAM master clock signal SK, the inverter circuit 7011 takes over the address As, which has been applied at this time.

The inverter circuit 7014 is put in the active state when the internal chip activation signal E is at "L" and thus indicates the chip selection state, while it is put in a state of high output impedance when the chip activation signal E is at "H" and the unselected one Indicates chip state. When the chip enable signal E is "L" with the rising edge of the internal clock signal SK, the address As applied to the inverter circuit 7011 at this time is latched by the inverter circuits 7013 and 7014 , and becomes an internal SRAM address generated.

Fig. 7 shows a structure for the E-buffer of Fig. 5. As shown in Fig. 7, the E-buffer 154 has a p-channel MOS transistor Tr700, the source of which is connected to the supply potential Vcc and which SRAM master clock signal SK receives at its gate, a p-channel MOS transistor Tr701, the source of which is connected to the drain of the p-channel MOS transistor Tr700 and the gate of which receives the chip activation signal E #, an n-channel MOS transistor Tr702, whose gate receives the chip activation signal E # and whose drain is connected to the drain of the MOS transistor Tr701, and an n-channel MOS transistor Tr703, whose drain is connected to the source of the MOS transistor Tr702, whose source is connected to ground potential Vss is connected and the gate receives an inverted signal / SK of the SRAM master clock signal. E-buffer 154 is placed in a high impedance state when SRAM master clock signal SK is "H" (transistors Tr700 and Tr703 are both blocked) and inverts chip enable signal E # and generates an inverted signal / E of the internal chip activation signal E # when the SRAM master clock signal SK is at "L". Therefore, the chip activation signal E # can be adopted in accordance with the SRAM master clock signal SK.

By using the structures of the SRAM control circuit and the main amplifier circuit 138 as described above, the SRAM power saving mode and the SRAM decommissioning mode can quickly become simple.

[SRAM read mode]

The SRAM read mode is a mode for reading data from the SRAM field. As shown in FIG. 8, in this mode of operation, with the rising edge of the master clock signal K, the chip activation signal E # is set to "L" and the write activation signal WE # and the control clock signals CC1 # and CC2 # are set to "H". In the following description, it is assumed that the SRAM clock mask signal CMs is "L". At this time, under the control of the SRAM control circuit 132 (see Fig. 1) in accordance with the simultaneously adopted SRAM address bits As0 to As1, a memory cell selection process is carried out, and the data of the selected memory cell of the SRAM array is written to the internal data bus 123 (see FIG. 1). If the output activation signal G # is at "L" at this point in time, a stable value is output with the rising edge of the next clock signal. The SRAM works at high speed. Therefore, by setting the SRAM read mode with each rising edge of the master clock signal K, the stable data can be output with the rising edge of the next clock cycle (provided the output enable signal G # is "L").

When the output enable signal G # is set to "H", the main amplifier circuit 138 is placed in a high output impedance state.

Fig. 9 shows the data flow in the SRAM read mode. At this time, a driver 118 a, which corresponds to the SRAM row decoder 118 shown in FIG. 1, decodes the SRAM address bits As4 to As11 and selects a row in the SRAM field 104 . In the SRAM field 104 , 16 bits of memory cells are connected with one row. One of these 16 bits of memory cells is selected by column decoder 120 . Column decoder 120 decodes SRAM address bits As0 to As3 and selects one of the 16 bits of memory cells. An SA / IO control circuit 122 reads the data of the selected memory cell of the SRAM array 104 .

[SRAM write mode)

The SRAM write mode is a mode for writing data into the memory cells of the SRAM array. For the SRAM write mode, with the rising edge of the master clock signal K, the chip activation signal E # and the write activation signal WE # are both set to "L" and the control clock signals CC1 # and CC2 # are both set to "H", as shown in Fig. 10 is shown. In this case, the SRAM clock mask signal CMs is also set to "L" in the previous cycle. This condition applies to the following descriptions, and it is assumed that the SRAM clock mask signal CMs is "L" unless otherwise stated. As shown in Fig. 10, masking data M0 to M3 are used, and the operation signal diagrams in the SRAM read mode and the SRAM write mode are shown with a common DQ connector arrangement.

As shown in FIG. 10, the SRAM read mode is set when, with the rising edge of the first cycle of the master clock signal K, the chip activation signal E # is at "L" and the write activation signal WE # and the control clock signals CC1 # and CC2 # are at " H "are set. If the output enable signal G # is at "L", data is read with the rise of the next clock signal K.

To switch from SRAM read mode to SRAM write mode, the chip activation signal E # with the rising edge of the third cycle of the master clock signal K raised to "H". Consequently, the SRAM decommissioning mode is set, and the in the second cycle of the clock signal K specified SRAM Memory cell data is processed with the rising edge of the third cycle of the master clock signal K stabilized and then in a state corresponding to a high output impedance transferred.

In the fourth cycle of the master clock signal K, when the chip activation signal E # and the write activation signal WE # are both set to "L" and the control clock signals CC1 # and CC2 # are set to "H", the SRAM write mode is set. The SRAM address bits As0 to As11 created at this time are adopted, and the masking data M0 to M3 (referred to as M3 in FIG. 10) and the internal write data are also adopted at this time. A specific bit D3 of the write data is masked with respect to the write process in accordance with the masking data M3. As long as with the rising edge of the master clock signal K the chip activation signal E # and the write activation signal WE # are at "L" and the control clock signals CC1 # and CC2 # are at "H", the SRAM write mode is then repeated, write data D and mask data M become with the rising edge of the clock signal K, and the data is written.

By setting the chip activation signal E # to "L" and the Write activation signal WE # and the control clock signals CC1 # and CC2 # to "H" in the ninth cycle of the master clock signal K, the SRAM read mode is set. Is that Output activation signal G # to "L", the in the SRAM Read mode read values Q8 and Q9 with the rising edges of the tenth or eleventh cycle of the master clock signal K into one stable state. If the output activation signal G # earlier than the rising edge of the master clock signal 12 "H" is set, the input / output terminal DQ is in a High impedance condition, provided that Write enable signal WE # is at "H".

Because access to the SRAM field, as mentioned above, is high Speed is running, data writing is in one cycle of the clock signal K is completed.

As can be seen from Fig. 10, using the SRAM set mode when switching from read to write operation, the writing of data can be performed safely while the reading data (Q2) does not affect the writing data (D3) of the next cycle.

Fig. 11 shows the data flow in the SRAM write mode. As shown in Fig. 11, a word line driver circuit 118a is driven to perform the row selection operation in the SRAM, and the column decoder 120 operates to select a memory cell of the SRAM array 104 . Data is written to the selected memory cell of SRAM array 104 via block 122 .

As shown in Figs. 9 and 11, in the SRAM read mode and the SRAM write mode, the writing of data into the SRAM field and the reading of data from the SRAM field are carried out regardless of the operation of the data transmission circuit and the DRAM field . When accessing the SRAM field, data transfer between the data transmission circuit and the DRAM field can therefore be carried out in parallel. Such an operation is possible because the DRAM control circuit 128 and the SRAM control circuit 132 are formed separately, as shown in FIG. 1.

[Buffer Read Transfer Mode]

The buffer read transfer mode is an operating mode for transferring data from the read transfer buffer to the SRAM. In this mode, 16 bits of data are transferred simultaneously from the data transfer circuit to the SRAM array. As shown in FIG. 12, the buffer read transfer mode is realized by setting the chip activation signal E # and the control clock signal CC2 # to "L" as well as the write activation signal WE # and the control clock signal CC1 # to "H" with the rising edge of the master clock signal K. The other operating modes are also shown in FIG .

In the buffer read transfer mode, data transfer is ensured by setting the SRAM address bits As0 to As3 which are being supplied at this time to "L". By setting the SRAM column address bits As0 to As3 to "L", simultaneous data transfer of 16 bits is carried out. Referring now to Figure 12, the buffer read transfer mode as well as other modes of operation will be described.

As shown in FIG. 12, the SRAM read mode is set with the rising edge of the first cycle of the master clock signal K. The SRAM read operation is performed in accordance with the SRAM address C1 which is applied at this time, and the output data Q1 is stabilized with the rising edge of the second cycle of the master clock signal K. Because the chip activation signal E # is at "H" with the rising edge of the second cycle of the master clock signal K, the second cycle of the master clock signal K is in SRAM quiescent mode, and is with the rise of the third clock of the master clock signal K. the output is in a high impedance state. At this time, with the rising edge of the third cycle of the master clock signal K, the chip activation signal E # and the control clock signal CC2 # are also set to "L" and the write activation signal WE # and the control clock signal CC1 # are set to "H". As a result, the buffer read transfer mode is set. At this time, the SRAM address bits As0 to As3 are at "L". A row selection operation is carried out in the SRAM field in accordance with the SRAM address bits As4 to As11. 16 bits of SRAM memory cells are connected in one row. The data is transferred simultaneously from the read transfer buffer 140 to these 16 bits of the connected SRAM memory cells.

The SRAM field does not require any operations such as B. precharging the bit lines. The SRAM field can be addressed by the read transfer buffer immediately after the data has been transferred. As shown in FIG. 12, with the rising edge of the fourth cycle of the master clock signal K, the chip activation signal E # is set to "L" and the write activation signal WE # and the control clock signals CC1 # and CC2 # are set to "H". This sets the SRAM read mode. Accordingly, data is read from the RAM memory cell with the rising edge of the fifth cycle of the master clock signal K.

Subsequently, by setting the chip activation signal E # to "H" with the rising edge of the fifth cycle of the Master clock signal K set the SRAM decommissioning mode, the SRAM is in a non-selected in the fifth cycle State and after a predetermined period of time has passed the output is placed in a high impedance state.

With the rising edge of the master clock signal K in the sixth cycle, the chip activation signal E # and the control clock signal CC2 # are both set to "L" and the write activation signal WE # and the control clock signal CC1 # are set to "H", which sets the buffer reading mode. As a result, 16 bits of memory cells in the SRAM array are selected and data is transferred from read transfer buffer 140 to the selected 16 bits of SRAM memory cells. Then, in the seventh cycle of the master clock signal K, the chip activation signal E # and the write activation signal WE # are set to "L" and the two control clock signals CC1 # and CC2 # are set to "H", whereby the SRAM write mode is set. The data D5 applied at this time are written into the selected memory cell of the SRAM in accordance with the masking data M5.

In the eighth cycle of the master clock signal K, this becomes Chip activation signal E # set to "L", and that Write activation signal WE # and the two control clock signals CC1 # and CC2 # are all set to "H". The SRAM Reading mode set. Because at that time Output activation signal G # is at "H" results in a State of high output impedance to the outside.

In the ninth cycle of the master clock signal K is on again Buffer read transfer performed, and data is transferred from the Transfer read transfer buffer to SRAM field.

In the tenth cycle of the master clock signal K, the SRAM Write mode is set, and data is in this tenth Cycle into the selected memory cells of the SRAM array written.

By setting the buffer read transfer mode as above it is possible to describe the event of a cache miss Cache block collectively towards the SRAM field at high speed transfer. Therefore, the access time in the case of a cache Misses can be significantly reduced. The reason for this is, that the SRAM field after data transfer to the SRAM field corresponding to the buffer read transfer mode with high Speed can be addressed.

Fig. 13 shows the data flow in the buffer read transfer mode. In the buffer read transfer mode, a word line driver circuit selects 188 a one row of SRAM array 104, and 16 bits of data are transmitted simultaneously from the read transfer buffer 140 to the one selected row (16 bits). The read transfer buffer 140 described later has 16 buffers so that 16 data bits can be transferred simultaneously.

[Buffer Write Transfer Mode]

The buffer write transfer mode is an operating mode for transferring data from the SRAM array to a write data transfer buffer (with an intermediate buffer) formed in the data transfer circuit. The states of the control signals in the buffer write transfer mode are shown in FIG. 14.

The buffer write transfer mode is set by setting the chip enable signal E #, the write enable signal WE # and the control clock signal CC2 # to "L" and the control clock signal CC1 # to "H" with the rising edge of the master clock signal K. In the buffer write transfer mode, the SRAM address bits As0 to As3 must all be set to "L" in order to complete the data transfer process. In the buffer write transfer mode, all of the masking bits (masking data) formed in the masking register 146 are set to the reset state ("0" state). The reason for this is that it is necessary to transfer to the DRAM field all data that has been transferred from the SRAM field to the write transfer buffer 144 .

The operation including the buffer write transfer mode will now be described with reference to FIG. 14. As shown in Fig. 14, the SRAM read mode is determined with the rising edge of the first cycle of the master clock signal K. The selection of a memory cell of the SRAM is carried out, and the data of the selected memory cell are stabilized with the rising edge of the second cycle of the master clock signal K.

With the rising edge of the second cycle of the master Clock signal K, the chip activation signal E # becomes "H" raised, the SRAM decommissioning mode is set, the SRAM  is set to the unselected state and the output set to a high impedance state. In the third cycle of the master clock signal K, the chip activation signal E #, the write activation signal WE # and the control clock signal CC2 # set to "L" and the control clock signal CC1 # to "H", see above that the buffer write transfer mode is set. in the Buffer write transfer mode becomes the SRAM address bits As0 to As3 all set to "L". By using the remaining SRAM Address bits As4 to As11 become a line (16 bits) in the SRAM field selected, and the data of the selected 16 bits of SRAM Memory cells simultaneously become the write transfer buffer transferred (locked in the buffer).

In the fourth cycle of the master clock signal K, the SRAM Read mode set, a memory cell selection process corresponding to the SRAM address bits As0 to As11 is executed and the data of the selected memory cell are read. in the fifth cycle of the master clock signal K is again Decommissioning mode set, the SRAM will be during the fifth Cycle of the master clock signal K in the non-selected state held and the output goes into a high impedance state transferred.

In the seventh cycle of the master clock signal K, the SRAM Write mode set. At the same time it is Output enable signal G # at "H", and a write of Data corresponding to the masking data M5 (masking bits M0 to M3) is executed with respect to the SRAM field.

In the ninth cycle of the master clock signal K, the Buffer write transfer mode set, one line of SRAM Field is selected and the data of the memory cells with which are connected to a selected row, become Transfer write data transfer buffer. In the tenth cycle of the Master clock signal K, the SRAM write mode is set, and data is written into the SRAM field.

Fig. 15 shows the data flow in the buffer write transfer mode. As shown in Fig. 15, the word line driving circuit 118a is driven, a row of SRAM array 104 is selected and the data of the memory cells connected to the selected one row are connected to be transmitted to the write data transfer buffer. Here, the write data transfer buffer has an intermediate buffer for temporarily storing the supplied data, and the data is locked in the intermediate buffer 142 . By this structure in which the data transmitted from the SRAM array 104, data is latched by the intermediate buffer 142 once, data can 104 (a cache miss in the case) to be recovered and, in parallel, the cache data from DRAM from the SRAM array Field are transferred via the read data transfer buffer 140 . Therefore, the data transfer can be carried out at high speed in the case of a cache miss. This reduces the access time. In the following description, the data transfer from the SRAM field to the write data transfer buffer corresponds to the state in which data is stored in the intermediate buffer.

[Buffer Read Transfer / SRAM Read Mode]

In the buffer read transfer and SRAM read mode (hereinafter referred to as Buffer read transfer / SRAM read mode) are data from the Read data transfer buffer is transferred to the SRAM field and further one bit (a total of four bits if the device has a * 4 bit Structure) of the transmitted data according to the SRAM Address output from the SRAM field.

The buffer read transfer / SRAM read mode is set by setting the chip activation signal E # and the control clock signal CC1 # to "L" and setting the write activation signal WE # and the control clock signal CC2 # to "H" with the rising edge of the master clock signal K. The state of the control signals in an operating sequence with the buffer read transfer / SRAM read mode is shown in FIG. 16.

As shown in Fig. 16, with the rising edge of the first cycle of the master clock signal K, the SRAM read mode is set, a memory cell selection in the SRAM array is performed, and the data of the selected SRAM memory cell is read.

With the rising edge of the second cycle of the master Clock signal K become the chip activation signal E # and that Control clock signal CC1 # set to "L" while the Write enable signal WE # and the control clock signal CC2 # on "H" can be set. Through this combination of the states of the Control signals become the buffer read transfer / SRAM read mode fixed. In this operating mode there is a line in the SRAM field selected, and data is simultaneously from the Read data transfer buffer (DTBR) to the one selected line transferred from memory cells. After or parallel to Data transfer becomes a memory cell (column) Selection process according to the SRAM block address bits As0 to As3 executed, and the data related to the selected memory cell have been transferred are read.

In the third cycle of the master clock signal K, the Buffer read transfer / SRAM read mode set, data is transferred from the Read data transfer buffer (DTBR) transferred to the SRAM field, and it one bit is selected from the transmitted data (16 bits). The buffer read transfer / SRAM read mode is used for the following reasons executed in continuous cycles of the master clock signal K. It is possible to have one with each clock cycle Data transfer from the DRAM field to the read data transfer buffer by using the page mode of the DRAM used. The page mode of the DRAM is activated because of the Control circuit section for driving the DRAM array and the Control section for setting the operations that the SRAM field concern, are formed independently.

In the fifth cycle of the master clock signal K, the SRAM Decommissioning mode set, the SRAM is set for the fifth Cycle to the unselected state, and on Initial state of high impedance set.

In the sixth cycle of the master clock signal K, the SRAM Read mode set, which becomes the buffer read transfer / SRAM read mode  during the seventh and eighth cycle of the master clock signal K run continuously, and in the ninth cycle of the master Clock signal K, the SRAM read mode is determined.

The SRAM read mode and the buffer read transfer / SRAM read mode are executed continuously because of a cache hit the SRAM read mode is executed and with a cache Missing the latch function of the sense amplifier in the DRAM field is used and data of one row of memory cells in the DRAM Field have been locked, as will be described later. If which from an external device such. B. a CPU, required data is not in the SRAM field, but from Sense amplifiers are locked in the DRAM field, those of DRAM sense amplifier locked data from Read data transfer buffer are transferred. Then be transfer the data from the read data transfer buffer to the SRAM field, and with that the data can be read. The structure for Execution of such an operation mode will be detailed later described.

Fig. 17 shows the data flow in the buffer read transfer / SRAM read mode. As shown in Fig. 17, a row of the SRAM array 104 is selected by the word line driver circuit 118 a. Data is transferred from the read data transfer buffer (DTBR) to the selected line at the same time. Then, in accordance with a column selection signal from the column decoder 120, a memory cell in the SRAM array 104 is selected, and the data of the selected memory cell is output through a sense amplifier / IO control block 122 .

[Buffer Write Transfer / SRAM Write Mode]

In buffer write transfer and SRAM write mode (hereinafter referred to as Buffer Write Transfer / SRAM write mode) are data written in the SRAM field while data of the line with the Memory cell in which the data are written for Write data transfer buffer (intermediate buffer) (DTBW) transferred become. The transfer process is carried out in one clock cycle Master clock signal K completed. in the  Buffer write transfer / SRAM write mode are the Masking bits in the masking register all reset, and all data is transferred from the write data transfer buffer (DTBW) to the Transfer DRAM field.

In the buffer write transfer / SRAM write mode, the rising edge of the master clock signal K sets the chip activation signal E #, the write activation signal WE # and the control clock signal CC1 # to "L" and the control clock signal CC2 # to "H". As a result, data is written to the SRAM array and data is transferred from the SRAM array to the write data transfer buffer. The states of the external signals in operations involving the buffer write transfer / SRAM write mode are shown in FIG. 18.

As shown in FIG. 18, in the first cycle of the master clock signal K, the chip activation signal E # is at "H" and the SRAM is in an unselected state (SRAM set mode). In the second cycle of the master clock signal K, the chip activation signal E #, the write activation signal WE # and the control clock signal CC1 # are set to "L" and the control clock signal CC2 # to "H". The buffer write transfer / SRAM write mode is determined by these signal states. In this mode, the SRAM address bits As0 to As11 supplied at this time are all adopted, a column selection is carried out in the SRAM field and data is written externally into the selected SRAM memory cell. After the write operation is completed or in parallel with the write, the data of the memory cells connected to the one selected row of the SRAM field are transferred to the write data transfer buffer (DTBW) (more precisely to the intermediate buffer). In the third cycle of the master clock signal K, the buffer write transfer / SRAM write mode is carried out in a similar manner.

In the fourth cycle of the master clock signal K, the SRAM Reading mode set. Because the output enable signal G # is high, the output goes into a high impedance state transferred.  

In the fifth cycle of the master clock signal K, the SRAM Read mode is set, and there is data from the SRAM field read. The output enable signal G # is at "L" and that Data Q3 read in this cycle are output.

In the seventh cycle of the master clock signal K that is Output enable signal G # set to "H" to the output into a high impedance state. This will prevents that in the sixth cycle of the master clock signal K read data the subsequent data writing process influence.

In the eighth to tenth cycle of the master clock signal K, this becomes Chip activation signal E #, the write activation signal WE # and the control clock signal CC1 # to "L" and the control clock signal CC2 # set to "H". In these cycles there is an operation according to the buffer write transfer / SRAM write mode executed. By executing the buffer write transfer / SRAM Write mode is activated on a cache hit Write-through process realized (in which the in the SRAM field written data are transferred directly to the DRAM field).

Fig. 19 shows the data flow in the buffer write transfer / SRAM write mode. Referring to Fig. 19 is a one row of the SRAM array 104 selected by the word line driver circuit 118. A column of SRAM field 104 is selected by column decoder 120 . Write data is transmitted through this selected column via the SA / IO block 122 . After the transfer of the write data, the data of a row of memory cells, which has been selected by the word line driver circuit 118 a in the SRAM field 104 , are transferred to the write data transfer buffer (DTBW) 144 or more precisely to the intermediate buffer 142 .

[Buffer Read Mode]

In the buffer read mode, data is transferred directly from the Read data transfer buffer output. It won't overwrite  the content is carried out by the data transfer to the SRAM field. By executing the buffer read mode, data can be read without affecting the cache data stored in the SRAM field.

For the buffer read mode, the chip activation signal E # and the control clock signals CC1 # and CC2 # are set to "L" and the write activation signal WE # to "H" with the rising edge of the master clock signal K. In the buffer read mode, data is transferred from the read data transfer buffer (DTBR) to the input / output terminal DQ. In the buffer read mode, all address bits As4 to As11 for selecting a row of the SRAM are all set to "L" in order to ensure operation in the buffer read mode and to reliably prevent data change in the SRAM field. The SRAM address bits As0 to As3 are used to select a buffer of the read data transfer buffer (DTBR). In Fig. 20 an example of an operational sequence is shown with the buffer read mode.

As shown in Fig. 20, in the first cycle of the master clock signal K, the SRAM read mode is set and data is read from the SRAM array. In the second cycle of the master clock signal K, the chip activation signal E # and the control clock signals CC1 # and CC2 # are set to "L" and the write activation signal WE # to "H". This sets the buffer read mode. In the buffer read mode, the data of the read data transfer buffer (DTBR) is transferred to the input / output terminals DQ0 to DQ3 via the SRAM field (which is in a non-selected state). The SRAM block address bits As0 to As3 are used to select a buffer in the read data transfer buffer (DTBR).

The buffer read cycle is in one cycle of the master clock signal K completed.

In the third and fourth cycle of the master clock signal K, the SRAM read mode is set, and there is data from the SRAM field read. Although in the tenth cycle of the master clock signal K This is where SRAM read mode is set Output enable signal G # at "H" and the output in one  State of high impedance. In the eleventh to thirteenth cycle of the Master clock signal K is an operation in Buffer write transfer / SRAM write mode executed. By the Buffer read mode can image data on a CRT display unit can be displayed at high speed. In SRAM read mode the CPU reads the necessary data from the SRAM field and processes them. Then the processed data with the help operation in buffer write mode and DRAM Write transfer mode written in the DRAM field. By CDRAM can effectively operate this operation in the graphics area Video memory can be used.

Fig. 21 shows the data flow in the buffer read mode. As shown in Fig. 21, the word line driver circuit 118 a does not work. The SRAM field 104 is maintained in an unselected precharge state. Data from read data transfer buffer 140 traverses SRAM field 104 . A column of the SRAM array 104 is selected by the column decoder 120 and the SA / IO control block 122 , and the data is transferred to the data input / output terminal DQ. With this structure, the SRAM field 104 is also in the precharge state or the non-selected state (although the bit line potential changes due to the transfer data). The read data transmitted by the data transmission buffer 140 does not influence the data stored in the SRAM field 104 at all.

[Buffer write mode]

The buffer write mode is an operating mode in which externally supplied write data are not written into the SRAM memory cells, but into the write data transfer buffer (DTBW). For the buffer write mode, the chip activation signal E #, the write activation signal WE # and the control clock signals CC1 # and CC2 # are all set to "L". When the control signals are in these states, row selection operation is not performed in the SRAM field. It is necessary that the SRAM address bits As4 to As11 are all set to "L" to ensure the buffer write mode. The states of the control signals of operation sequences with the buffer write mode are shown in FIG. 22.

As shown in FIG. 22, with the rising edge of the master clock signal K, the chip activation signal E # is at "H" and the SRAM is in a non-selected state (SRAM set mode). With the rising edge of the second cycle of the master clock signal K, the chip activation signal E # f, the write activation signal WE # and the control clock signals CC1 # and CC2 # are set to "L". This sets the buffer write mode.

In this state, the SRAM field is not driven and external supplied data (D1) are in the write data transfer buffer (DTBW) written. The address bits As4 to As11 are set to "L" set. The write data transfer buffer (DTBW) becomes corresponding the SRAM block address bits As0 to As3 are selected and data in the selected write data transfer buffer (DTBW) written. When the buffer write mode is set, the masking data of the masking register corresponding to the external masking data valid at this time modified. If one of the masking values M0 to M3 is the same "0" is what a write indicates the corresponding bit of the masking register and indicates that the Masking is removed. Only the mask bit of the Masking register corresponding to the transfer buffer into which a Data writing in progress is reset.

In the third and fourth cycle of the master clock signal K, the SRAM read mode is set, and data is taken from the SRAM field read. In the fifth cycle of the master clock signal K that is Chip activation signal E # set to "H" and the SRAM Decommissioning mode set.

In the sixth to eleventh cycle of the master clock signal K be the chip activation signal E #, the write activation signal WE # and the control clock signals CC1 # and CC2 # are all set to "L" and set the buffer write mode. It will be in everyone  Cycle data in the write data transfer buffer (DTBW) written.

By executing the operation in the buffer write mode, data are written to the write data transfer buffer (DTBW), without affecting the data stored in the SRAM field, because no memory cell is selected in the SRAM field. You can then transfer data from Write data transfer buffer (DTBW) to the DRAM field data in the DRAM field can be written without the SRAM field influence stored data (cache data). So that can writing the graphic data at high speed be carried out.

Fig. 23 shows the data flow in the buffer write mode. In the buffer write mode, the word line driver circuit 118 a is not driven. A corresponding buffer in intermediate buffer 142 is selected by column decoder 120 , and data is written to the selected buffer. The operation of the section that drives the DRAM array will now be described.

[DRAM system]

Fig. 24 shows in tabular form, the modes of operation, involving the DRAM array, and the states of the control signals for implementing the respective operation modes. As shown in FIG. 24, the operations related to the DRAM array include a DRAM power saving mode in which the transmission of the clock signals to the DRAM portion is inhibited to effectively extend the operating cycles of the DRAM array, a DRAM NOP DRAM mode disable mode, a DRAM active mode to drive the DRAM array, a DRAM read transfer mode to transfer data from the DRAM array to the read data transfer buffer, a DRAM write transfer mode to transfer data from the write data transfer buffer to the DRAM array, one DRAM precharge mode to put the DRAM in a precharge state and a DRAM self-refresh mode to perform self-refresh of the DRAM array. The section for driving the DRAM array further includes a special mode for the CDRAM and an instruction register setting mode for setting instruction data for specifying the arrangement of the data input / output terminals and the like in an instruction register (not shown in Fig. 1). The mode of operation will now be described.

[DRAM power saving mode]

In the DRAM power saving mode, the master clock signal is not supplied to the DRAM area. The operating speed of the DRAM is lower than that of the SRAM. It takes several clock cycles to select a line and to address the DRAM field. The same applies to the data transfer mode. Therefore, the duration and timing for generating the control signals are determined in accordance with the master clock signal for each process. If the master clock signal is not applied to the DRAM control circuit ( 128 in FIG. 1) in this DRAM power save mode, the state of the previous clock cycle is maintained.

As shown in Fig. 25, the DRAM clock mask signal CMd for the DRAM power saving mode is set to "H" with the rising edge of the master clock signal K, and the DRAM enters the power saving mode from the next cycle. As shown in Fig. 25, the DRAM clock mask signal CMd is set to "H" on the rising edge of the second cycle of the master clock signal K, and the DRAM power saving mode starts after the third clock cycle of the master clock signal K. By stopping the DRAM operation reduces power consumption.

[DRAM NOP mode]

The DRAM-NOP mode is an operating mode in which a new one Process in the DRAM is blocked. The DRAM section keeps the Precharge status or the active status of the previous cycle.

As shown in Fig. 26, for the DRAM-NOP mode, the DRAM clock mask signal CMd is set to "L" with the rising edge of the master clock signal K, and the row address strobe signal RAS # and the column address strobe signal CAS # become with the rising edge of the master clock signal K both raised to "H". Because both the row address strobe signal RAS # and the column address strobe signal CAS # are at "H", the DRAM section maintains the unselected state, that is, the precharge state of the standby mode (if the precharge state was set in the previous cycle) .

In the operations related to the DRAM, the states of the control signals relating to the operation of the SRAM array are arbitrary, as the table of FIG. 24 shows. Therefore, the SRAM operation can be carried out independently of the DRAM operation. This also applies to the other processes that affect the DRAM field and are described below. The DRAM clock mask signal CMd allows the transmission of the master clock signal K in the next cycle if it is at "L". If the DRAM clock mask signal CMd is at "H", the transmission of the master clock signal K to the DRAM control circuit is blocked in the next cycle. When the DRAM-NOP mode is set, the DRAM maintains the precharge state when the precharge state has been set in the previous cycle and maintains the active state when the active state has been set in the previous cycle. The DRAM-NOP mode ensures that the DRAM area does not adopt a new operating mode.

[DRAM active mode]

The DRAM field is activated in DRAM active mode. To set of the DRAM active mode are with the rising edge of the Master clock signal K of the next clock cycle the row address RAS # strobe to "L" and column address strobe CAS # and the data transfer determination signal DTD # to "H" set when the DRAM clock mask signal CMd in the previous clock cycle is at "L". In this state the DRAM address Ad as a row address for specifying a row of the DRAM field, and it becomes a line selection operation  as well as capturing, amplifying and locking the Memory cell data executed by the sense amplifier.

[DRAM preload mode]

In the DRAM precharge mode, the DRAM is in a standby or Preload status offset. By executing the preload mode the DRAM active mode are ended. For the DRAM precharge mode the DRAM clock mask signal CMd with the increasing Edge of the master clock signal K set to "L", and that Row address scanning signal RAS # and the column address Sampling signal CAS # are generated with the rising edge of the master Clock signal K of the next cycle set to "K". If the DRAM precharge mode is set, the DRAM returns to Precharge status back. More specifically, one line (selected row) that was in the active state in the DRAM field in moved the unselected state to for the next Activation cycle to be ready. If another in the DRAM field Line is selected, it is necessary to use the DRAM End active mode once by a DRAM precharge cycle and run DRAM active mode again.

[DRAM read transfer mode)

The DRAM read transfer mode is an operating mode in which data transferred from the DRAM field to the read data transfer buffer (DTBR) become. The data transfer from the DRAM field to Read data transfer buffer (DTBR) and data transfer from Read data transfer buffer to the SRAM field and the Data input / output circuit are separated by Control systems run.

For the DRAM read transfer mode, with the rising edge of the master clock signal K, the row address strobe signal RAS # is set to "L", the data transfer designation signal DTD # is set to "H" and the column address strobe signal CAS # is set to "L" while the DRAM active mode is set. At this time, the column block decoder 112 shown in Fig. 1 operates with the DRAM input addresses Ad4 to Ad11 as column addresses. A corresponding column block (data block) of the memory cells connected to the selected row of the DRAM field is selected, and the memory cell data contained in the selected data block are transferred to the read data transfer buffer (DTBR).

To ensure this process it is necessary to Set address bits Ad0 to Ad3 to "L". If the DRAM Read transfer mode is set, all other operations locked for a predetermined period of time. After this Elapse of a predetermined clock signal time from the setting of the DRAM read transfer mode, the data in Read data transfer buffer (DTBR) stabilized. The necessary Time between the determination of the DRAM read transfer mode and the stabilization of the new data in Read data transfer buffer (DTBR) is called latency by a command value set in the command register, the will be described later. Of the Read data transfer buffer (DTBR) has a latch function and holds the data of the previous cycle. By setting the Latency and setting of data transfer clocking by the Master clock signal K can the content of the Read data transfer buffers (DTBR) securely with the new data can be overwritten and data can be transferred / read safely become. Because the access when changing the data in Read data transfer buffer (DTBR) is locked, the saving or reading incorrect data in or from the Read data transfer buffers (DTBR) can be prevented.

Fig. 27 shows the states of the external control signals and the states of the data stored in the read data transfer buffer when the DRAM precharge mode, the DRAM active mode and the DRAM read transfer mode are set. An operation sequence of the DRAM will be described with reference to FIG. 27.

As shown in FIG. 27, the DRAM clock mask signal CMd reaches the level "L" with the rising edge of the master clock signal K and the transmission of the master clock signal K to the DRAM control circuit ( 128 in FIG. 1) is permitted .

With the rising edge of the third cycle of the master Clock signal K become the row address strobe signal RAS # and that Data transfer determination signal DTD # both at "L" and that Column address strobe signal CAS # set to "H". The DRAM Precharge mode is set.

After the RAS precharge time tRP has elapsed (the minimal time required to precharge each signal line in the DRAM Section), in the seventh cycle of the master clock signal K the row address strobe signal RAS # to "L" and the column address Sampling signal CAS # and DTD # are both set to "H". In order to the DRAM active mode is set. Here is the DRAM Clock mask signal CMd in the previous cycle (sixth cycle) dropped to "L". That is in the following description DRAM clock mask signal CMd in the previous cycle of Operating mode setting always set to "L", and therefore it gets out not for cases that require a special description described.

When the DRAM active mode is set, it becomes that Time created DRAM addresses Ad0 to Ad11 as Row address used to define a row in the DRAM field, and the data of the selected memory cell are from a Sense amplifiers detected, amplified and locked.

After the RAS / CAS delay time tRCD has passed, in the tenth cycle of the master clock signal K, the row address strobe signal RAS # and data transfer determination signal DTD # are both set to "H" and the column address strobe signal CAS # to "L". This determines the DRAM read transfer mode. By the DRAM active mode, a memory cell block corresponding to the DRAM address Ad4 to Ad11 supplied at that time is selected from the memory cells connected to the selected row and after a predetermined period of time has elapsed (in FIG. 27, a latency of two Clock cycles), the data of the read data transfer buffer (DTBR) are replaced by new data.

If the latency when setting the DRAM read transfer mode n Clock cycles, the establishment of a new operating mode in the (n-1) th clock cycle from the cycle in which the DRAM Read transfer begins, blocked. When transferring data from The DRAM field for the read data transfer buffer (DTBR) is located Read data transfer buffer in a locked state. During this Time period is the buffer read mode (i.e. reading data blocked by the read data transfer buffer (DTBR)). The reason for this is that the data in the read data transfer buffer (DTBR) is unstable are.

The definition of a new operating mode becomes possible after all clock cycles, which are determined by the latency, have passed. In the twelfth cycle of the master clock signal K achieve the row address strobe signal RAS # and that Data transfer determination signal DTD # both the "L" and level the column address strobe signal CAS # is "H" level. With that the DRAM preload mode set. As a result, the DRAM field returns to Pre-charge status is back and is ready for the next access.

Fig. 28 shows the data flow in the DRAM read transfer mode. As shown in FIG. 28, in the DRAM read transfer mode, a block having a predetermined number of memory cells of the selected row in the DRAM array 102 is selected, and the data of the selected memory cell block is transferred to the read data transfer buffer 140 . In order to ensure the DRAM read transfer mode, the DRAM address bits Ad0 to Ad3 are all set to "L". When the DRAM field section is operated, an operation relating to the SRAM field can be carried out arbitrarily, with the exception of the DTBR blocking time. Accordingly, data writing or data reading can be performed by accessing the SRAM in parallel with the data transfer from the DRAM field to the read data transfer buffer (DTBR), and data can also be written to the write data transfer buffer (DTBW). It is important that the data transfer to the read data transfer buffer (DTBR) is not affected.

[DRAM write transfer mode]

In the DRAM write transfer mode, the data stored in the write data transfer buffer (DTBW) is written into the selected memory cell block of the DRAM array according to the masking data stored in the masking register. As shown in Fig. 29, with the rising edge of the master clock signal K after the lapse of a predetermined period of time (after the RAS / CAS delay time tRCD has elapsed) from the execution of the DRAM active cycle, the row address strobe signal RAS # comes on "H" and the column address strobe signal CAS # and the data transfer determination signal DTD # are set to "L". This sets the DRAM write transfer mode. The DRAM address bits Ad4 to Ad11 supplied at this time are adopted as the column address Col for selecting a column block (memory cell block), and a selection process of a memory cell block is carried out. Data is transferred simultaneously from the write data transfer buffer (DTBW) to the selected memory cell block. To ensure operation in the DRAM write transfer mode, the DRAM address bits Ad0 to Ad3 must be set to "L". In the first clock cycle from the establishment of the DRAM write transfer mode (the tenth clock cycle in FIG. 29), every new operation is blocked for the DRAM field.

In the cycle immediately after the first cycle after definition of the DRAM write transfer mode, the masking data of the Masking registers all set (data transmission lock) to to avoid incorrect overwriting of the next data.

As shown in Fig. 29, after the lapse of the RAS cycle time tRAS in the twelfth cycle of the master clock signal K, the row address strobe signal RAS # and the data transfer determination signal DTD # both become "L" and the column address strobe signal CAS # set to "H". This sets the DRAM precharge mode. In the first clock cycle after the DRAM write transfer mode has been determined, the write data transfer buffer (DTBW) is set to the locked state. More specifically, access to the write data transfer buffer is blocked in this cycle. Operations related to the SRAM field can be freely set and executed.

Fig. 30 shows the flow of data in the DRAM Schreibtransferm 99999 00070 552 00004 001000280000000200012000285919988800040 0002004337740 99880odus. As shown in FIG. 30, the data stored in the write data transfer buffer 144 is transferred to the DRAM array 102 in accordance with the masking data set in the masking register 146 . A row has already been selected in DRAM field 102 , and a block is selected from a plurality of memory cells of the selected row in DRAM write transfer mode. Data is transferred from the write data transfer buffer 144 to the selected block of a plurality of memory cells. As can be seen from FIG. 30, the SRAM field 104 can be addressed during this period, and the read data transfer buffer 140 can also be addressed.

A special structure of the DRAM area will now be described.

FIG. 31 shows an example of the structures of the DRAM control circuit and the mask circuit of FIG. 1. As shown in FIG. 31, a K buffer 124 receives an external clock signal K and generates an internal master clock signal Ki.

A masking circuit 126 has a shift register 202 for delaying the DRAM clock masking signal CMd by one clock signal period of the internal clock signal Ki from the K buffer 124 and a gate circuit 204 for passing the internal master clock signal Ki in accordance with the delayed DRAM clock masking signal CMd from the shift register 202 . As shown in FIG. 31, gate circuit 204 is formed by a p-channel MOS transistor (insulated gate field effect transistor) which blocks transmission of the internal master clock signal Ki when the delayed clock mask signal CMd is "H". If the clock mask signal CMd is "H" in a certain cycle, the transmission of the internal master clock signal Ki is blocked in the next cycle, and therefore the generation of the DRAM master clock signal DK is interrupted.

The DRAM control circuit 128 has a RAS buffer 206 , which takes the row address strobe signal RAS # with the rising edge of the DRAM master clock signal DK to generate an internal row address strobe signal RAS, a CAS buffer 208 which is connected to the rising edge of the DRAM master clock signal DK latches the column address strobe signal CAS # to generate an internal column address strobe signal CAS, a DTD buffer 210 , which is dependent on the DRAM master clock signal DK, for taking over the data transmission. Determination signal DTD # with its rising edge to generate an internal data transfer determination signal DTD, and a DRAM control signal generating circuit 212 which takes over the internal control signals RAS, CAS and DTD with the rising edge of the DRAM master clock signal DK determine the mode that is determined by the states of the signals and generate the necessary control signals in accordance with the specified operating mode, on.

The DRAM control signal generation circuit 212 also monitors the latency required for data transmission in accordance with the DRAM master clock signal DK. The DRAM control signal generation circuit 212 generates various control signals necessary for driving the DRAM field area and for the data transfer operation between the data transfer circuit (read data transfer buffer and write data transfer buffer) and the DRAM field. In Fig. 31 are a transmission control signal ADT for controlling the operation of the transmission circuits, a RAS control signal CRA for controlling the operation of the circuits related to the RAS signal (such as the row selection process in the DRAM array) and a control signal RCA for controlling the operation of the circuit sections that affect the CAS signal (such as the selection of a column) are represented as representatives.

The address buffer 108 has a row buffer 214 , which is dependent on the DRAM master clock signal DK and the RAS control signal CRA, for taking over an external DRAM address Ad and for generating a DRAM row address Adr and a column buffer 216 which is provided by the DRAM Master clock signal DK and the CAS control signal RCA is dependent on locking the DRAM address Ad and generating a DRAM column address Adc. Row address Adr is applied to row decoder 110 shown in FIG. 1, and a predetermined high order bit of the column address from column buffer 216 is applied to column block decoder 112 shown in FIG. 1. As will be described later, in some operating modes the column address Adc or Adr is used as the command value to the command register. The column address Adc is also used to determine the type of data transfer mode (which will be described later).

As described above, the DRAM control circuit 128 controls the operation of the DRAM array and the data transfer process between the DRAM array and the data transfer circuit. It is independent of the operation of the SRAM field area. As described above, the driving of the DRAM array and the data transfer between the DRAM array and the data transfer circuit can be performed regardless of the states of the control signals supplied to the SRAM control circuit 132 .

[Chip layout]

Fig. 32 shows a specific layout of the CDRAM field. As shown in FIG. 32, the CDRAM 100 is arranged on a rectangular chip. The CDRAM 100 has four DRAM memory sections DM1, DM2, DM3 and DM4, each with a memory capacity of 4 Mbit, SRAM memory sections SM1, SM2, SM3 and SM4, which are formed in the central region of the chip corresponding to the DRAM memory sections and one each 4 Kbit memory capacity, and data transmission circuits DTB1, DTB2, DTB3 and DTB4, which are formed between the DRAM memory sections DM1 to DM4 and the SRAM memory sections SM1 to SM4.

Each of the DRAM memory sections DM1 to DM4 is shown to be divided into 4 _* 16 = 64 memory blocks MBA. The memory block MBA has memory cells which are arranged in 256 rows by 256 columns. The DRAM memory sections DM1 to DM4 each have 16 pairs of IO lines, which are arranged so that they run through all of the row blocks RB shown in the figure. In Fig. 32 a large global IO line pair BGIO shown, the four pairs of global IO lines comprises. A global IO line corresponds to 64 columns of the DRAM field. One of the 64 columns is connected to a global IO line pair. In a DRAM memory section, 16 columns are selected at the same time. 4 columns are selected in the memory block MBA at the same time.

Four pairs of local IO lines are used to connect the simultaneously selected four columns with the global IO Line pair formed. The local IO line pair is only in the corresponding memory block MBA used. In each of the DRAM Memory sections DM1 to DM4 become only the memory block activated which contains the selected line (word line), and the other memory blocks are kept in the precharge state. By driving with this partial activation procedure (Block division method) can reduce the line consumption become.

Among the memory cells that are connected to the selected row of the DRAM, 16 columns of memory cells are selected, the data of the selected 16 bits of memory cells are transmitted to the local IO line pair and then to the global IO line pair. In Fig. 32, the expression "divided into four" indicates that four pairs of local IO lines LIO are formed in this divided block and each with the large global IO line pair BGIO (four pairs of global IO lines) that in the corresponding block is formed, are connected.

16 data transmission circuits in each of the Data frames DTB1 to DTB4 are according to the global IO line pairs formed. The SRAM memory sections SM1 to SM4 each have static memory cells that in 256 rows are arranged in 16 columns. In the Data transfer is carried out in each of the SRAM memory sections SM1 to SM4 selected a line and the data transfer between 16 bits of static memory cells with this one line are connected, and executed the data transmission circuits.

A DRAM row decoder and a row control circuit are arranged between adjacent memory sections along the narrow side of the CDRAM 100 . A DRAM row decoder / line control circuit RDC1 is arranged between the DRAM memory sections DM1 and DM3 and a DRAM row decoder / line control circuit RDC2 is arranged between the DRAM memory sections DM2 and DM4. The DRAM row decoder / row control circuit executes a row selection process in the corresponding memory section, drives the sense amplifier to acquire and amplify the data of the selected memory cell, precharges the bit lines, etc.

The SRAM control circuit and some of the DRAM control circuits are located in the central portion of the CDRAM 100 . The DRAM control circuits have a block decoder for selecting a column in the DRAM memory section, a circuit for controlling the column selection process, and various peripheral circuits. The SRAM control circuit has an SRAM row decoder, an SRAM column decoder and the SRAM control circuit shown in FIG. 1.

Input / output circuits 101 and 102 are formed in the central portion of the CDRAM. The input / output circuit 101 serves for data input / output of the DRAM memory sections DM1 and DM2 and the SRAM memory sections SM1 and SM2, which input / output the input / output data DQO and DQ1. The input / output circuit 102 carries out input / output of the input / output data DQO and DQ1 into or from the DRAM memory sections DM3 and DM4 and the SRAM memory sections SM3 and SM4.

Because the data input / output is performed in the central portion of the CDRAM chip 100 , the signal lines for performing the data input / output can be made shorter. This enables data input / output at high speed. Because the SRAM memory section is located in the center of the chip, the data input / output connections for the SRAM memory section can be made shorter. This enables high-speed access to the SRAM.

[Field structure]

Fig. 33 shows a structure for the SRAM array (the SRAM memory section shown in Fig. 32 or the SRAM array shown in Fig. 1). The SRAM array 104 has static memory cells SMC, which are arranged in a matrix of rows and columns. A row of static memory cells SMC is connected to an SRAM word line SWL, while a column of static memory cells SMC is connected to an SRAM bit line pair SBL. In Fig. 33, three SRAM word lines SWL1 to SWL3 are shown as representatives.

A static memory cell SMC has both cross-coupled p- Channel MOS transistors P1 and P2 as well as cross-coupled n- Channel MOS transistors N1 and N2. Transistors P1 and N1 form a first inverter, while transistors P2 and N2 form a second inverter. The inputs and outputs of the first and second inverters are cross connected to one another To form inverter latch circuit.

The static memory cell SMC also has an n-channel MOS Transistor N3, which is from a signal potential on the SRAM Word line is dependent, for connecting a connection node of transistors P1 and N1 with an SRAM bit line SBLa and an n-channel MOS transistor N4, which has a signal potential on the SRAM word line SWL is dependent on connecting one  Connection node of transistors P2 and N2 with an SRAM Bit line * SBLa on.

For each of the SRAM bit line pairs SBL, an SRAM Sense amplifier SSA and a bidirectional transfer gate BTG educated. The bidirectional transfer gate BTG is with one global IO line pair GIOa or GIOb connected, which differs from the DRAM field extends as will be described later. The as ΦTSD and ΦTDS shown transfer control signals are to the bidirectional transfer gate BTG created.

In the structure shown in Fig. 33, the SRAM word lines SWL1 to SWL3 are each connected to memory cells, the number of which is equal to the number of data bits that are transferred in one data transfer operation between the DRAM field and the SRAM field (16 bits at this embodiment).

Figure 34 shows an arrangement for the DRAM array. Fig. 34 shows a portion corresponding to one half of the memory block MBA of Fig. 32. More specifically, two pairs of global IO lines GIOa and GIOb and two pairs of local IO lines LIOa and LIOb are formed. A DRAM memory block MBÿ has a plurality of dynamic memory cells DMC, which are arranged in a matrix. A dynamic memory cell DMC has a memory transistor Q0 and a storage capacitor C0. A predetermined potential Vgg (usually an intermediate potential of Vcc / 2) is applied to an electrode (cell plate) of the storage capacitor C0.

The memory block MBÿ has DRAM word lines DWL, with which one row each of DRAM cells (dynamic memory cells) DMC is connected, and DRAM bit line pairs DBL to which one column of DRAM cells is connected to DMC. The DRAM bit line pair DBL has complementary bit lines BL and BL / BL on. The DRAM cell DMC is at the respective intersection between the DRAM word line DWL and the DRAM bit line pair DBL arranged.  

There is one DRAM sense amplifier for each DRAM bit line pair DBL DSA for detecting and amplifying the potential difference on the corresponding bit line pair formed. The DRAM sense amplifier DSA has a p-channel sense amplifier section cross-coupled p-channel MOS transistors P3 and P4 and one n-channel sense amplifier section with cross-coupled n-channel MOS transistors N5 and N6.

The operation of the DRAM sense amplifier DSA is by the Sense amplifier driver signals / ΦSAP and ΦSAN controlled by p-channel MOS transistor TR1 and n-channel MOS transistor TR2 in Dependence on a sense amplifier activation signal / ΦSAPE and ΦSANE can be delivered.

The p-channel sense amplifier section lifts depending on Sense amplifier driver signals / ΦSAP the potential on the Bit line with higher potential at the level of the Operating supply voltage Vcc. The n channel Sense amplifier section discharges depending on the Sense amplifier driver signals ΦSAN the potential of the bit line with lower potential on z. B. the level of the ground potential Vss.

When the sense amplifier enable signal / ΦSAPE is "L" reached, the p-channel MOS transistor TR1 generates that Sense amplifier driver signal / ΦSAP with the level of Supply potential Vcc and transfers it to the Supply node of the DRAM sense amplifier DSA. If that Sense amplifier activation signal ΦSANE reaches level "H", the n-channel MOS transistor TR2 transmits the sense amplifier Driver signal ΦSAN with the level of the ground potential Vss to other supply node of the DRAM sense amplifier.

Here, the driver signal lines on which transmit the sense amplifier driver signals ΦSAN and / ΦSAP are precharged to the intermediate potential Vcc / 2. For Simplifying the drawing is the circuit for preloading the Driver signal lines of the sense amplifier not shown.  

There is one for each of the DRAN bit line pairs DBL Precharge / equalization circuit formed DEQ, which is dependent from a precharge / compensation signal ΦEQ for precharging the respective bit line of the corresponding bit line pair a prescribed precharge potential Vb1 and for equalization of the precharge potential of the bit line BL and / BL is activated. The precharge / equalization circuit DEQ has n-channel MOS Transistors N7 and N8 for transferring the precharge potential Vb1 to the bit lines BL and / BL and an n-channel MOS Transistor N9 for equalizing the potentials of the bit lines BL and / BL on.

The DRAM memory block MBj also has a DRAM Column selection gate CSG based on the respective of the DRAM bit line pairs DBL is formed and dependent from a signal potential on a column selection line CSL is made conductive to the corresponding DRAM bit line pair DBL to be connected to the local IO line pair LIO. The Column selection line CSL is common to two pairs of DRAM Bit lines are formed and two pairs of DRAM bit lines are formed DBL selected at the same time. A pair of local IO Line pairs LIOa and LIOb receive data from the two pairs of DRAM bit lines that are selected at the same time. For each of the local IO line pairs LIOa and LIOb is one Precharge / equalization circuit similar to that Bit line equalization / precharge circuit DEQ formed. For The simplification of the drawings is that Precharge / equalization circuit not shown.

The memory block MBÿ also assigns DRAM-IO gates IOGa IOGb Connect the local IO line pairs LIOa and LIOb with the global IO line pairs GIOa and GIOb depending on a block activation signal ΦBA. In CDRAM only the block placed in the selected state, the one selected line (word line). Only for this one selected block, the DRAM IO gates IOGa and IOGb made conductive. The control signal ΦBA for selecting the block is, for example, from the four high-order bits of the DRAM Row address generated to select the word line  is used (in a structure in which only one row block of 16 line blocks (each with 256 lines) in the selected state).

[Data transfer process: Page mode transfer mode]

The data transfer process between the DRAM field and the SRAM field will now be described. In the following description is the data transfer gate for a better understanding of the Data transfer process between the fields simplified.

Fig. 35 shows a basic structure for the bidirectional transmission gate BTG. As shown in FIG. 35, the bidirectional transmission gate BTG has a 3-state buffer DR1, which is dependent on a transmission determination signal ΦTSD, for transmitting data on the SRAM bit line pair SBL to the global IO line pair GIO and a 3-state Buffer DR2, which is activated as a function of the carry determination signal ΦTDS, for transmitting the data on the global IO line pair GIO to the SRAM bit line pair SBL. The buffers DR1 and DR2 have a latch function. The details of the bidirectional transmission gate will be described later. First, the data transfer process from the DRAM field to the SRAM field will be described with reference to this figure and the signal diagram of Fig. 36.

Both the SRAM field and are located before the time t1 the DRAM field in the waiting state (precharge state).

The precharge determination signal ΦEQ is on an active "H" State, the DRAM precharge / equalization circuit DEQ is in one active state whereby the DRAM bit line pair DBL on predetermined precharge potential Vb1 and the potentials Bit lines BL and / BL compensate. Be similar the potentials of the local IO line pair LIOa and one global IO line pair GIO to an intermediate potential preloaded (the circuit structure is not shown).  

At time t1 when the precharge determination signal ΦEQ is at "L" drops, the precharge / equalization circuit DEQ is deactivated and the DRAM bit line pair DBL becomes electrical floating state at a predetermined precharge potential transferred. Similarly, the signal line that transmits the sense amplifier driver signals ΦSAN and / ΦSAP, too in the floating state at the intermediate potential Vcc / 2 transferred. The DRAM row decoder then carries one Line selection operation according to the supplied DRAM Address signal off.

At time t2, a DRAM word line DWL is selected in the DRAM field and the potential of the selected word line DWL increases. The selected DRAM word line extends in all memory blocks MBA (MBÿ) contained in a row block. A row of memory cells connected to the selected DRAM word line DWL is connected to the corresponding DRAM bit line pairs DBL (the DRAM bit line BL or / BL) (the memory transistor Q0 is made conductive), and the potential of the DRAM Bit line pair DBL changes in accordance with the data of the memory cell connected to it. As shown in Fig. 36, in three pairs of DRAM bit lines DBL1, DBL2 and DBL3, memory cells are selected which store the value "1", and the associated bit lines BL (or / BL) are shown with a raised potential.

At time t3, the sense amplifier activation signal rises ΦSANE to "H" and the sense amplifier driver signal ΦSAN decreases from the intermediate potential Vcc / 2 to "L" of the ground potential Vss down. The n-channel sense amplifier section, which is in the DRAM sense amplifier DSA included is activated, and that Potential of the bit line with the lower potential of the DRAM Bit line pair DBL drops to the level of the ground potential Vss down.

At time t4, the sense amplifier activation signal falls / ΦSAPE to "L" and the sense amplifier drive signal / ΦSAP increases from the intermediate potential Vcc / 2 to the level of  Operating supply voltage Vcc. This becomes the p-channel Sense amplifier section included in the DRAM sense amplifier DSA is activated, and the potential of the bit line with the higher Potential of the DRAM bit line pair rises to the level of Supply voltage Vcc on.

At time t5, a column selection line CSL is selected in accordance with a column selection signal from the DRAM column block decoder, and the potential of the selected column selection line CSL1 rises to "H". Consequently, in a memory block MBÿ two pairs of DRAM bit line pairs DBL (four pairs of DRAM bit lines in the memory block MBA) are connected to the local IO line pairs LIOa and LIOb via the DRAM column selection gate CSG. The potentials of the local IO line pairs LIOA and LIOB (collectively referred to in FIG. 36 by the reference symbol LIO) change from the template potential Vcc / 2 in accordance with the data transmitted by the selected DRAM bit line pair DBL.

At time t6, the block activation signal ΦBA rises only for the block containing the selected word line to "H" and the DRAM IO gate IOG (IOG collectively denotes the Gate IOGa and IOGb) is switched through. Consequently, that will Signal potential on the local IO line pair LIOa to global IO line pair GIO transmitted. The determination of the selected memory block (the block with the selected one Word line) is by decoding the high order bits of the Row address signal used to select the DRAM word line is used.

No read is performed in the remaining unselected memory blocks and the precharge state is maintained. Through the sequence of operations described above, only one memory block MBA of the 16 memory blocks MBA arranged vertically in Fig. 32 is connected to the bidirectional transmission gate circuit (i.e., connected to four bidirectional transmission gates BTGs).

In the SRAM, a line selection process is carried out by the SRAM row decoder at time ts11, an SRAM word line SWL is selected in the SRAM field (a total of four SRAM word lines) and the potential of the selected SRAM word line SWL (in FIG. 36 the SRAM Word line SW1) rises to "H". The row selection process in the DRAM section and the row selection process in the SRAM section are carried out asynchronously because the determination of the buffer read transfer mode in the SRAM is carried out independently of the DRAM read transfer mode in the DRAM.

The respective data of the SRAM cells which are connected to the SRAM word line SWL are transmitted to the corresponding SRAM bit line pair SBL. The potential of the SRAM bit line pair SBL changes from the precharge potential (or equalization potential) Vcc / 2 in accordance with the information stored in the corresponding SRAM cell. The circuit structure for equalizing the potential of the SRAM bit line pair SBL is not shown in FIG. 33. If an access cycle to the SRAM is established in CDRAM (i.e. access to the SRAM array is established with a rising edge of the master clock signal K), a single pulse signal can be generated to compensate for the SRAM bit line pair SBL.

At time t7, the data transfer determination signal rises ΦTDS to "H" for a predetermined period of time. On the global IO line pair GIO are already the data of the DRAM Cell has been transferred and the SRAM bit line pair SBL connected to the SRAM cell. Depending on Data transmission determination signal ΦTDS becomes the bidirectional Transmission gate BTG activated, and the signal potential on the global IO line pair GIO becomes the corresponding SRAM Bit line pair SBL transmitted. Consequently, one Data transfer from the DRAM cell to the SRAM cell carried out. As described above, are stored in a memory block NBÿ selected two bits of DRAM memory cells and the Memory cell data is stored on 16 pairs of global IO Transfer wire pairs to GIO. Therefore, a total of 16 bits  Data from DRAM cells on the data transmission circuit transmitted once to the SRAM cells.

Provided that the time t7 at which the Data transmission determination signal ΦTDS is activated after Time t6 at which the block activation signal ΦBA rises and after the time ts11 at which the SRAM word line SWL is selected, the temporal relationship between at times ts11, t1 and t6. The signal ΦTSD, that specifies a data transfer from the SRAM field to the data field, is kept at an inactive level "L" in this cycle.

At time ts12, the word line selection process in the SRAM Field 2 completed. This is also the data transmission from 16 Bits of memory cells completed. At time ts21 the SRAM word line SWL in the SRAM field again in the selected one State set.

The DRAM word line DWL is selected in the DRAM field State maintained (because no DRAM precharge mode is set). At time t5 'if the DRAM read transfer mode again is set, the column selection line CSL1 is not in the selected state, and at time t5 ' next column selection line CS2 in the selected state transferred. This process is usually known as page mode. By selecting a new column selection line CSL2 to Time t5 ′ changes the potential of the local IO Line pair LIO corresponding to the data of the memory cell, the is selected by the column selection line CSL2. Alternatively a structure can be used in which the potentials of the local IO line pair LIO and the global IO line pair GIO once after deactivating the column selection line CSL be restored to the precharge state. During this The block selection signal ΦBA is held at "H" for a period of time. The new data on the local IO line pair LIO become the global IO line pair GIO transmitted. The active time of the Column selection line can be determined by latency.  

At time t7 ', the data transmission signal ΦTDS is again generated. At time t7 ′, the potential of the global IO Line pair GIO already set in the stable state and in the SRAM field are the data of the memory cells that have been newly connected to the SRAM word line SWL2, already transferred to the SRAM bit line pair SBL and in one stable condition. 16 bits of data on the global IO Cable pair GIO are via the bidirectional Transmission gate BTG at once to the 16 bits Memory cells are transferred using the SRAM word line SWL are connected.

At time ts22, the word line selection process is SWL2 completed in the SRAM field, and at time ts31 a new SRAM word line SWL3 selected. The selection / non-selection the word line SWL in the SRAM field is replaced by the State combinations of the signals E #, WE # and CC1 # and CC2 # fixed. Because the SRAM work at high speed it works faster than the high speed mode of the DRAM. Furthermore, at the time of data transmission in the SRAM the next new word line safely in the selected state be transferred.

A column selection line becomes in the DRAM field at time t6 ' DSL3 in the selected state and dependent this changes the potentials on the local IO line pair LIO and the global IO line pair GIO. At time t7 ' generates the data transfer determination signal ΦTDS, and the Data on the DRAM bit line pair DBL3 are connected to the SRAM Bit line pair SBL transmitted.

At time t1, the DRAM word line DWL is not in the selected state, the data transfer cycle will completed and the DRAM field returns to the Ready state back (execution of the DRAM Preload mode).  

In the SRAM field, the potential of the SRAM word line SWL3 falls Time TS32 to the potential "L", and the potential of the SRAM bit line pair SBL returns to precharge potential. Here is the potential of the SRAM bit line pair SBL in Ready status shown as intermediate potential. With With the help of a clamping transistor it can reach the level of Supply potential can be preloaded.

The DRAM block decoder selects eight column select lines CSL once out. A column selection line CSL selects two pairs of DRAM bit line pairs DBL out. The data transfer from the DRAM Field to SRAM field becomes parallel to the global IO line pair executed. Therefore 16 data bits are transmitted together. By repeated execution of the data transfer cycle can transferred data volume increased from 16 to 32.48 bits etc. become.

In the description above the data transfer from DRAM field to SRAM field in one step. in the CDRAMs of the present invention can be Data transfer process from the DRAM field to Data transmission circuit and the data transmission process of the bidirectional data transmission circuit to the SRAM field run independently of each other. The working principle is however, similar to that described above, and by using the DRAM sense amplifiers in the DRAM field as latch means can large amount of data at high speed to the SRAM field are transferred using the page mode of the DRAM.

After the time TS32, the SRAM field section can be external be addressed. In contrast, the DRAM field can be in the DRAM the time t8 until the RAS precharge time tRP has elapsed not be addressed. With the help of this structure, a large amount of data at high speed from DRAM field to SRAM field are transmitted and the transmitted data in SRAM can be addressed externally at high speed. For example, in the event of a cache miss, the DRAM field transmitted data immediately after completion of this Data transmission can be read.  

By repeatedly executing the DRAM read transfer mode and the Buffer read transfer mode of the SRAM will allow a plurality of data blocks from the DRAM field to the SRAM field.

Fig. 37 schematically shows the data transfer process from the DRAM field to the SRAM field. The data transfer process will be described with reference to FIG. 37.

As shown in Fig. 37, in the DRAM field, the DRAM word line DWL1 is set to the selected state. Data block D1 has a plurality of memory cells (16 bits of memory cells in this embodiment) that are transferred by a transfer operation. The SRAM word line can be selected in the SRAM field at this time. It is important that the selection process should be completed before the transfer process from the DRAM field to the SRAM field is carried out (more specifically, before the data transfer process from the bidirectional transfer gate to the SRAM field is carried out).

As shown in FIG. 37, the data block D1 of the DRAM word line DWL1 in the DRAM field is collectively transmitted to the selected memory cells of the SRAM word line SWL1 of the SRAM field via the bidirectional transmission gate BTG.

As shown in Fig. 37, data block D1 is placed in the unselected state and in the SRAM field the next word line SW2 is placed in the selected state. In this state, the data block D2 newly selected in the DRAM field is transmitted via the bidirectional transmission gate BTG to the memory cells of the SRAM word line SWL2. The data block D2 is then set to the unselected state and the SRAM word line SWL2 is set to the unselected state.

As shown in Fig. 37, a high speed mode is executed (DRAM read transfer mode), the next data block D3 on the DRAM word line DWL1 is selected, and the data is transferred via the bidirectional transfer gate BTG to the memory cells which have a newly selected SRAM Word line SWL3 are connected in the SRAM field.

By using the high speed mode of the DRAM (Page Mode) can handle a large amount of data with high data as described above Speed to be transferred to the SRAM field.

In this embodiment, the Data transmission process of the bidirectional transmission gate executed in two steps. It is a first step in the Data transfer from the DRAM field to bidirectional Transmission gate and second step of data transmission from bidirectional transmission gate to the SRAM field available. These data transfers are under control separate control systems. The bidirectional Transmission gate can be addressed directly from the outside, by setting the buffer read or write mode. Therefore, it is possible not only to transfer data between the SRAM field and the DRAM, but also one Block write mode in which data from the outside successively to be written. The SRAM field is not in the selected state, and therefore the stored in it Data not affected (provided that the operation in Buffer read or write mode takes place).

Fig. 38 shows a signal diagram of the data transfer process from the SRAM field to the DRAM field. The operation signals shown in Fig. 38 are the same as those of Fig. 36, except that the data transfer designation signal ΦTSD is generated instead of the data transfer designation signal ΦTDS, the direction of data transfer from the SRAM field to the DRAM field and the potential of the Bit line pairs DWL of the DRAM field changes in accordance with the data transmitted by the SRAM field. In this case, an operation similar to that at the time of data transfer from the DRAM field to the SRAM field in the DRAM field and SRAM field is carried out, except that the operation mode set is different. More specifically, the buffer write transfer mode or the buffer write transfer / write mode is set in the SRAM field section, and the DRAM write transfer mode is set in the DRAM. Therefore, the detailed description of the process is not repeated.

Fig. 39 schematically shows the data transfer operation from the SRAM array to the DRAM array. In this case too, the only difference is that the direction of data block transfer differs from that shown in the diagram of FIG. 37. A detailed description is not repeated. By using this mode, not only high-speed data transfer from the SRAM field to the DRAM field, but also a block write mode can be implemented (because data can be written directly from the outside into the bidirectional transfer gate).

[IO section]

Fig. 40 shows a structure for the IO region of the SRAM portion. In the structure shown in FIG. 1, when the bidirectional transmission gate is addressed externally, data is written and read via the SRAM field. The SRAM field must be kept in the unselected state. The structure of the input / output section at this time is shown. Although no SRAM sense amplifiers SSA, which are formed for the respective SRAM bit line pair SBL, are not shown, one is formed for each SRAM bit line pair. An SRAM column selection gate 302 is formed for each of the SRAM bit line pairs SBL. A column selection signal CD from the column decoder ( 120 in FIG. 1) is supplied to the column selection gate 302 . A pair of SRAM bit lines is thus selected from the 16 bits of SRAM bit line pairs SBL.

The internal data bus 123 (see FIG. 1) has an external write data line pair 123 a for transmitting write data and read data transmission line 123 b for transmitting read data to the main amplifier circuit. The read data transmission line 123 b can be formed from a pair of signal lines.

The internal write data line pair 123 a has write data lines DBW and * DBW for transferring complementary data generated by the Din buffer circuit (input buffer circuit). The internal write data line pair 123 a is connected to the write circuit 303 . The write circuit 303 amplifies the internal write data from the internal write data line pair 123 a and transfers the amplified data to the internal data lines DBWa and * DBWa.

Write circuit 303 has n-channel MOS transistors T301, T302, T303 and T304. The gates of transistors T302 and T303 are connected to the internal write data line DBW. The gates of transistors T303 and T304 are connected to the internal write data line * DBW. The connection section of the transistors T302 and T304 is connected to the internal data line DBWa, and the connection section of the transistors T301 and T303 is connected to the internal data line * DBWa.

Transistors T301 and T302 transmit a signal on the Level of the supply voltage Vcc when it is conductive are. Transistors T303 and T304 transmit this Ground potential Vss when they are turned on. For the internal data lines DBWa and * DBWa is a sense amplifier SSAa formed to amplify the data supplied. The data of the sense amplifier SSAa become the main amplifier circuit transfer. The operation will now be briefly described.

It is assumed that the value "H" is transferred to the internal write data line DBW. The value "L" is transferred to the internal write data line * DBW. The transistors T302 and T303 are turned on. Consequently, the value "H" is transferred from the write circuit 303 via the transistor T302 to the internal data line DBWa, while a value "L" is transferred via the transistor T303 to the other internal data line * DBWa.

When reading data, data "L" are transferred from the input buffer circuit (Din buffer circuit) to both internal write data lines DBW and * DBW. The output of write circuit 303 assumes a high impedance state. The SRAM sense amplifier SSAa is activated. The SRAM bit line pair SBL is connected to the internal data lines DBWa and * DBWa via the selected column selection circuit 302 . The internal to the data lines and DBWa * DBWa transmitted data is amplified by the SRAM sense amplifier SSAA and then the data transmission line 123 b transmitted to the main amplifier circuit.

Using the structure of Fig. 40, data can be written directly into the data transfer buffer (bidirectional transfer gate circuit) via the SRAM field. However, if the bidirectional transmission gate BTG (or buffer circuit) is to be addressed via the SRAM field, it is necessary to connect the SRAM field to the transmission gate in order to release the balanced state of the SRAM bit line pairs SBL in the SRAM field. The SRAM word line is placed in the unselected state. As a result, the bidirectional transmission buffer (bidirectional transmission gate circuit) can be addressed externally via the SRAM field without influencing the data stored in the SRAM field. The reason for this is that a bidirectional transmission gate or bidirectional transmission buffer is formed for each of the SRAM bit line pairs.

Because the write data transmission line 123 a and the read data transmission line 123 b are formed separately as the internal data line 123 , the input / output circuit layout can be simplified compared to a structure in which the writing and reading of data is carried out through a common internal data bus be designed.

[Data transfer buffer circuit]

In the above operation description with the page mode operation is the bidirectional transmission gate BTG to simplify the Description has been described as a 3-state buffer. The bidirectional transmission gate has a latch function.  

The operating mode described by Formation of the latch function for the bidirectional Transmission gate is realized.

Fig. 41 shows a more detailed structure of the bidirectional transmission gate. The bidirectional transfer gate has a read transfer buffer 210 for receiving data from the DRAM field, that is, the data on the global IO line pair GIO, and a write transfer buffer 250 for receiving data from the SRAM field (data stored in the SRAM field or externally created data).

The read transfer buffer 210 has a gate 212 which is switched on in response to a data transfer determination signal ΦTDS1, a latch circuit 230 for locking the data supplied via the gate 212 , an inverter circuit 218 for inverting the locked data of the latch circuit 230 , and a gate 220, which is switched on in response to a transmission determination signal ΦTDS2, for transmitting the output data from the inverter circuit 218 to the SRAM bit line pair SBL. Latch circuit 230 has an inverter circuit 214 with a high driving capacity and an inverter circuit 216 with a lower driving capacity. The output of inverter circuit 214 is connected to the input of inverter circuit 216 and the output of inverter circuit 216 is connected to the input of inverter circuit 214 . Because the driving ability of the inverter circuits 214 and 216 differs, there is a function of locking data and, in addition, the one-way data transfer can be carried out at high speed.

The write transfer buffer 250 has a gate 260 , which is switched on as a function of a transfer determination signal ΦTSD2, for transferring the data to the SRAM bit line pair SBL, an inverter circuit 258 for inverting the data supplied via the gate 260 , a latch circuit 232 for locking the Output value from the inverter circuit 258 and a gate 252 , which is dependent on the transfer determination signal ΦTSD1, for transferring the output value from the latch circuit 232 to the global IO line pair GIO. Latch circuit 232 has an inverter circuit 254 with a high driving capacity and an inverter circuit 256 with a lower driving capacity. The output of inverter circuit 254 is connected to the input of inverter circuit 256 , and the output of inverter circuit 256 is connected to the input of inverter circuit 254 .

The DRAM control circuit shown in FIG. 1 generates the transfer determination signals ΦTDS1 and ΦTSD1 in accordance with the row address strobe signal RAS #, the column address strobe signal CAS # and the data transmission determination signal DTD #.

The SRAM control circuit 132 shown in FIG. 1 generates the transfer determination signals ΦTDS2 and ΦTSD2 in accordance with the chip activation signal E #, the write activation signal WE # and the internal clock signals CC1 # and CC2 #. The operation of the bidirectional transmission buffer shown in FIG. 41 will now be described with reference to FIG. 42, which shows an operation signal diagram.

As described above, the DRAM field and the SRAM field are driven independently. As shown in FIG. 42, for the SRAM section from the first to the sixth clock cycle of the master clock signal K, the chip activation signal E # is at "L" and the write activation signal WE # and the control clock signals CC1 # and CC2 # are all at "H" . This sets the SRAM read mode so that a static memory cell corresponding to the SRAM address As which is supplied with the rising edge of the master clock signal K is selected and the data of the selected memory cell is read.

In the DRAM section, the row address strobe signal RAS # falls to "L" with the third cycle of the master clock signal K. This determines the DRAM active mode, the DRAM address Ad that is being supplied at this time is adopted as the row address, and a row selection process is carried out. After the RAS / CAS delay time tRCD has passed, the column address strobe signal CAS # falls to "L". The transmission determination signal DTG # is at "H". Consequently, the DRAM read transfer mode is set, the DRAM address Ad currently applied is adopted as the block address, a memory block is selected in the DRAM field, and the data of the selected memory cell is transferred to the read transfer buffer (the transfer control signal ΦTDS1 shown in Fig. 41 reaches "H").

After the DTBR lockout time (which is determined by the latency) has passed, the control clock signal CC1 # falls to "L" in the SRAM section, and the buffer read transfer / read mode is set. As a result, the transfer control signal ΦTDS2 shown in Fig. 41 reaches "H" level and the data latched in the latch 230 is transferred to the SRAM bit line pair SBL. The data transmitted to the SRAM bit line pair is further selected depending on the SRAM address As which is set at the time the SRAM read transfer / read mode is set, and thus data is read. More specifically, from the eighth cycle of the master clock signal of Fig. 42, new data b1,. . . that are transferred from the DRAM field are read continuously.

In the eighth cycle of the master clock signal K, both achieve this Row address strobe signal RAS # as well Direction of transmission determination signal DTB # the level "L" which DRAM precharge mode is set and the DRAM returns to Precharge status back.

Fig. 43 schematically shows the parallel operation of the DRAM and the SRAM. As shown in Fig. 43A, in the SRAM field, data reading is performed according to the externally applied SRAM address As. In parallel to the data reading process in the SRAM field, the selection of a row and a memory cell block MDB0 is carried out in the DRAM, the selected memory cell block MDB0 is transferred to the transfer buffer DTBR and stored there.

As shown in Fig. 43B, the buffer read transfer / read is performed, data stored in the read transfer buffer DTBR is transferred to the SRAM array, and one bit of data is read from the memory cell data block MDB0 (16 bits). Repeating this process enables high speed access.

Especially in graphics applications, this can be the next address to be known beforehand. More specifically becomes the data of a scan line on a cathode ray tube addressed one after the other. The addresses of those on the monitor data shown follow one another. Therefore, the as next address to be addressed must always be known. By Using the CDRAM for graphics applications can save the graphics data can be processed at high speed by using the as next data to be addressed are preselected in the DRAM field and this data is locked in the read transfer buffer.

As will be described later, by using this mode of operation, the sense amplifiers in the DRAM array can be used as an additional cache. This enables a reduction in the waiting time in the event of a cache miss. This process will be described in detail later. Fig. 44 shows another mode of operation when the DRAM field and the SRAM field are operated in parallel. In contrast to the operation according to FIG. 42, the DRAM read transfer mode is determined again after the tenth cycle of the master clock signal K in the process shown in FIG. 44. As a result, the data of another memory cell block of the DRAM row currently selected is transferred to the read transfer buffer.

In the (n + 1) th cycle of the master clock signal K, this becomes Control clock signal CC1 # set to "L" and that Control clock signal CC2 # is set to "H". Hence the Buffer read transfer / read mode set in the Read transfer buffer DTBR stored data becomes the SRAM field transferred, and the data of the transferred memory cell Data blocks are further selected and read. By  Repeating this process can result in a large amount of data with high Read speed.

By using this mode of operation, that is, the high speed mode (page mode) of the DRAM, the data transfer operation can be carried out at high speed. More specifically, the process shown in Figs. 43A and 43B is carried out repeatedly. The data transfer from the DRAM field to the SRAM field can be carried out in accordance with the page mode operation until the precharge mode of the DRAM field is determined. At this time, a data block can be transferred in the reverse direction from the SRAM field to the DRAM field in accordance with the page mode. Because data can be written directly from the outside into the write data transfer buffer circuit by executing the buffer write mode and then setting the DRAM write transfer mode, data can be written into the DRAM field according to the page mode.

[Masking register]

As shown in Fig. 1, a mask register is formed for the write data transfer buffer. The reason for this is that unnecessary data transfer to the DRAM field must be prevented when data is written externally to the write data transfer buffer in the buffer write mode. The function of the masking register is briefly described. Its detailed structure is described later along with the detailed structure of the bidirectional transfer gate.

Fig. 45 shows an example of the structure of the mask register corresponding to a 1-bit write data buffer circuit. As shown in Fig. 45, the mask register 290 has a latch circuit 261 composed of inverter circuits 266 and 268 , a gate 262 , which is dependent on a setting determination signal ΦS, for transmitting a signal with the supply level Vcc to the latch node LN, a gate 264 , which is dependent on a reset determination signal ΦR, for transmitting a signal with the ground level Vss to the latch node LN, and a gate 270 for selectively transmitting the output data from the write data transfer buffer (DTBW) 215 to the global IO line pair GIO corresponding to the latch data of the latch circuit 261 . When the setting determination signal ΦS is supplied, the mask register 290 stores mask setting data and inhibits the transfer of write data from the write data transfer buffer (DTBW) 250 . When the reset determination signal ΦR is asserted, the mask register 290 passes the data output from the write data transfer buffer (DTBW).

Fig. 46 is an example of the structure shows a control circuit for generating the Maskierungsdateneinstell- and reset determination signals. The masking data set / reset determination signal generating circuit includes a decoder 272 for decoding the SRAM block address bits As0 to As3, an AND circuit 274 which receives the column selection signal CD of the decoder 272 and the buffer write mode determination signal ΦBW, an OR circuit 278 which one Receives output signal from AND circuit 274 and buffer write transfer mode (with buffer write transfer / write mode) determination signal ΦBWT, a pulse generation circuit which is dependent on the fall of signal ΦTSD1 to generate a single pulse and an OR circuit 282 which outputs an output signal from Circuit 280 and the masking data setting determination signal EMS receives. The masking data reset signal ΦR is generated by the OR circuit 278 , while the masking data setting signal ΦS is generated by the OR circuit 282 .

More specifically, when the buffer write mode is set, the mask value is reset only for the write data transfer buffer to which the data is written. When data transfer from the SRAM field is specified, the masking data is reset for each bit. When the mask data setting signal EMS (generated by the command register described later) is generated, the mask register is set. When the mask activation signals M ₀ to M ₃ are used, a structure is used in which the output signal from the gate circuit 274 is set to "L" when the mask activation signals M0 to M3 are active.

Fig. 47 schematically shows the function of the masking register. As shown in Fig. 47A, only the mask value corresponding to the written write transfer buffer is reset in the mask register MR when external write data (DQ) is written into the write data transfer buffer (DTBW). Therefore, in the DRAM write transfer mode for transferring data to the DRAM field, only the data which have been written into the write data transfer buffer DTBW are transferred from the transfer buffer.

In Fig. 47B, data is transferred from the SRAM field to the write data transfer buffer DTBW. In this state, all masking data in the masking register MR are reset. Therefore, all data transmitted from the SRAM field is transmitted to the DRAM field.

By forming the masking register for the write data As described above, transfer buffers (DTBW) are only the necessary data written to the DRAM field when data from written directly into the write data transfer buffer on the outside become.

By forming a masking register for the write data As described above, CDRAM cannot only transfer buffer as Main memory of the CPU can be used, but in a simple way also as memory for graphic data.

As shown in Fig. 41, it is possible to store data in the write data transfer buffer (from the SRAM field or from the outside) from the DRAM field to the read transfer buffer before transferring data to be read because the read transfer buffer and the Write transfer buffers are formed separately. This enables high-speed access.

Because the masking register is formed, in the DRAM field only overwrite the necessary data (because the Masking data can be reset). Therefore, it is not necessary, data from the DRAM field by one Read-Modify-Write process to read and read the data Rewrite memory cell externally. Therefore, the required data overwritten at high speed become.

In the structure of the bidirectional data transfer buffer circuit shown in FIG. 1, the write data transfer buffer has an intermediate register in order to safely transfer the necessary data only to the DRAM field. When the DRAM write transfer mode is set and the DRAM array is active, the data of the write data transfer buffer is generally written to the specified memory cell block of the DRAM array. At this time, the masking register provides a mask against overwriting. The bit whose masking register is set is not described. Data transfer between the write data transfer buffer ( 144 in FIG. 1) and the intermediate register ( 142 in FIG. 1) is controlled by using the two least significant bits of the DRAM address Ad. Data transfer between register 142 and buffer 144 is completed in a cycle in which the RAS # latency has elapsed after the DRAM active instruction has been triggered and the CAS # latency has elapsed after the DRAM write transfer mode has been set. If the DRAM address Ad0 is "0", no data transfer between the registers 142 and 144 is carried out. A data transfer takes place if it is "1".

[DRAM self-refresh]

The memory cells of the DRAM field must be refreshed periodically. For this purpose, a self-refresh mode is established. Fig. 48 shows the states of various control signals in the self-refresh mode. As shown in Fig. 48, for the DRAM self-refresh mode with the rising edge of the master clock signal K, the row address strobe signal RAS # and the column address strobe signal CAS # become "L" and the data transfer determination signal DTD # becomes "H""set. In the DRAM self-refresh mode, the output from an internally formed address counter is used as the line address, and a line selection process and a refresh process are carried out. At the end of the refresh cycle, the value of the address counter is increased by 1. Although the structure for executing the DRAM self-refresh mode is not explicitly shown, it is included in the DRAM control circuit 128 of FIG. 1. In order to execute the operation mode for driving the DRAM array after the DRAM self-refresh mode, a DRAM precharge operation must be performed once. This is similar to the CAS before RAS refresh mode (CBR) in a standard DRAM. In this refresh mode, executing the DRAM precharge mode puts a line that is in an active state into the unselected state. This completes the refresh state.

The structure for executing the DRAM self-refresh mode is included in the DRAM control circuit 128 of FIG. 1. A structure can be used in which the states of the signals RAS #, CAS # and DTD # are monitored with the rising edge of the master clock signal K. When the predetermined conditions are set, it is determined that the DRAM self-refresh mode is set, and in accordance with the determination result, the count value of the address counter is supplied as a row address instead of the externally applied DRAM address Ad. More specifically, the state detection circuit of an ordinary standard DRAM can be used to use the states of the control signals RAS #, CAS # and DTD # in the CBR mode detection section.

Alternatively, an externally created DRAM address can be used as Refresh address can be used.

[Command register setting mode]

The CDRAM has a command register (not shown in FIG. 1) for determining the arrangement of the input / output ports, setting the latency in the DRAM read transfer mode and the latency of the DRAM write transfer mode, setting the output mode (latch transparent and register mode), etc. on.

For the instruction register setting mode (SCR mode), with the rising edge of the master clock signal K, the row address strobe signal RAS #, the column address strobe signal CAS # and the data transfer determination signal DTD # are all set to "L" as shown in FIG . 49 is shown. At this time, the DRAM address bits Ad0 to Ad11 are accepted as command data Cmd and the necessary internal mode is determined.

As shown in Fig. 49, the DRAM precharge mode is set in the third cycle of the master clock signal K, and after the RAS precharge time tRP has passed, the row address strobe signal RAS #, the column address, becomes the seventh cycle of the master clock signal K -Sampling signal CAS # and the data transfer determination signal DTD # are all set to "L". This sets the command register setting mode. With the rising edge of the master clock signal K of the seventh cycle, the DRAM address bits Ad0 to Ad11 are adopted as command setting data and the internal state is set. In the command register setting mode, the self-refresh of the DRAM field is carried out simultaneously. When accessing the DRAM field, it is necessary to raise a word line in the DRAM field as quickly as possible after the rising edge of the master clock signal K. For this purpose, the number of mode determinations should be kept as small as possible (in order to reduce the time required for the mode determination). Therefore, in the DRAM field, the self-refresh is carried out in the instruction register setting mode. In order to cancel the self-refresh, a precharge process is carried out in the twelfth cycle of the master clock signal K.

However, it is also possible to set data in this Execute mode only in the command register so that the operation of the  DRAM is not affected at all. You can do that easily Implement wisely when using a structure where the Command register the DRAM addresses Ad0 to Ad11 in the SCR (Command register setting) mode directly and not via the DRAM Address buffer received.

Fig. 50 shows in a table the correspondence between the command data and the content set at that time. In Fig. 50, the DRAM address bits Ad11 to Ad7 are reserved for future expansion. The address bits Ad4 through Ad6 are used to set the access latency (the latency in DRAM read transfer mode and DRAM write transfer mode, that is, the number of clock cycles that determine the transfer clock in the data transfer buffer). Four different access latencies are prepared according to the rate (number of cycles) of the clock signal K.

The address bits Ad2 and Ad3 are used to determine the output mode used. If the two address bits Ad2 and Ad3 are at "L", the transparent output mode is set. Is that Address bit Ad2 to "H" and address bit Ad3 to "L", the Latch output mode set. Is the address bit Ad2 on "L" and the address bit Ad3 at "H" is the register output mode fixed.

The address bit Ad1 is used to define the Output port configuration used. Is the address bit Ad1 to "L", the common DQ arrangement is fixed. In this State can mask activation signals (masking data) to mask external write data. Is that Address bit Ad1 to "H", the DQ separation mode is set. The Input / output of data is via separate connections executed.

The address bit Ad0 is used to set the masking data of the Masking register used. If the address bit Ad0 is at "L", the masking data of the masking register will not changed. If the address bit Ad0 is at "H", all Masking data set. When switched on, the state is the  Masking data not stable. When a buffer write mode in a blind cycle and then data on DRAM field are transmitted, it is therefore possible that the DRAM Write transfer mode executed with unstable masking data and that the mask formed in the initial cycle is unstable. To avoid such a condition, after the Turn on the masking data of the masking register every set. This process is described below.

Fig. 51 shows the structure of the mask register data control system shown in Fig. 46. As shown in Fig. 51, the data for the corresponding global IO line pair GIO changes according to the potential transmitted from the write data transfer buffer when that Transfer determination signal ΦTSD1 for the write data transfer buffer DTBW rises for a predetermined period of time (this period is determined by the latency) and when the masking data of the masking register 290 (see FIG. 45) is in the reset state. When the transfer of the write data transfer buffer is completed, the pulse generation circuit 280 generates a single pulse, an adjustment signal ΦS is generated, and the data stored in the mask register is set.

In the initial state after switching on, the Masking data must be set exactly if data is appropriate the buffer write mode to the write data transfer buffer be written, and then the data written to the DRAM field are transmitted. Therefore, it is necessary that To set masking data of the masking register before the Buffer write mode is running. To do this implement a masking value of the Masking register set by a command transferred.

As shown in Fig. 52, a predetermined number of master clock signals K are transmitted to the DRAM section after the supply voltage is applied to the CDRAM. At this point the blind cycle is executed. The row address strobe signal RAS #, the column address strobe signal CAS # and the data transfer designation signal DTD # are all "H". The DRAM thus enters the DRAM-NOP mode. The DRAM master clock signal DK is transmitted to the peripheral circuit, an operation is performed in accordance with the applied master clock signal DK, and the peripheral circuit is initialized. This corresponds to the initialization operation of a standard DRAM. In this state, the masking data in the masking register are unstable.

If in this dummy cycle the DRAM write transfer mode the masking register can be safely executed in a set state. In DRAM write transfer mode however, data transfer from the write data Transfer buffer to the DRAM field executed. The dates in Transfer buffers are unstable, so the state of the DRAM field becomes unstable. Hence the setting of the masking data the masking register in the dummy cycle using a such DRAM write transfer mode is not cheap.

After completion of the dummy cycle, the row address strobe signal RAS #, the column address strobe signal CAS # and the data transfer designation signal DTD # are respectively set to "L" to execute the command register setting mode. The mask setting signal ΦMS for the mask register rises to "H", and the data of the mask register is surely set to the set state (see Fig. 45). Fig. 53 shows a structure for the section related to the SCR mode. As shown in Fig. 53, the SCR mode circuit includes an SCR mode detection circuit 400 which detects from the states of the row address strobe signal RAS #, the column address strobe signal CAS # and the data transfer determination signal DTD # dependent on the rising edge of the DRAM master clock signal DK, for detecting the determination of the SCR mode, a command register 402 , which is dependent on the SCR mode detection signal from the SCR mode detection circuit 400 , for taking over the address Ad die is supplied at this time, as a command value for generating a required signal, a self-refresh mode detection circuit 404 for detecting the setting of the self-refresh mode in accordance with a combination of the states of the row address strobe signal RAS #, the column address strobe signal CAS # and the data transfer determination signal DTD # with the rising edge of the DRAM master clock signal DK, and a self-refresh maintenance control circuit 406, which is dependent on the self-refresh detection signal from the self-refresh mode detection circuit 404 , for executing the self-refresh mode.

Self-refresh control circuit 406 has an address counter and a multiplexer circuit for multiplexing the output of the address counter with an external address to apply the result to the address buffer or the DRAM row decoder. When the SCR mode is detected, the self-refresh control circuit 406 also performs self-refresh of the DRAM in response to the SCR mode detection signal from the SCR mode detection circuit 400 .

Fig. 54 shows another example of the structure of the portion that relates to the SCR mode. In the structure shown in Fig. 54, only the instruction register 402 is driven when the SCR mode is set. The self-refresh control circuit 406 is driven only when the self-refresh mode is set. The reason why the self-refresh of the DRAM field is only carried out when the SCR mode is set is to reduce the number of operating modes to be determined and to select the word line in the DRAM field as quickly as possible. As shown in Fig. 54, the instruction data in the instruction register can be set even during the page mode operation and the precharge operation of the DRAM array when only the instruction register is driven in the SCR mode. Therefore, command data can be selectively changed in the operating cycle of the DRAM field.

Fig. 55 shows an example of an operation sequence of the DRAM array with an instruction register setting mode for setting the instruction register. As shown in FIG. 55, in the first cycle of the master clock signal K, the DRAM active mode is set and a row selection process in the DRAM field is carried out.

In the fourth cycle of the master clock signal K, the DRAM Write transfer mode set, a block of memory cells of the DRAM field is selected and the data stored in the Write transfer buffers are saved to the selected one Transfer memory cell block. According to a predetermined Time period (latency is 3 in the example shown) is in seventh cycle of the master clock signal K of the DRAM Write transfer mode set again. In the second Write transfer mode is in the ninth cycle of the master Clock signal K during the data transfer of the command register Setting mode set, that is, RAS #, CAS # and DTD # all reach level "L". The one fed at this time Address is accepted as command value and in the command register set.

In the twelfth cycle, the DRAM write transfer mode is again specified, and data transfer from the write data Transfer buffer to DRAM executed. In the fifteenth cycle of the Master clock signal K, the DRAM precharge mode is set, and the DRAM field returns to the precharge state.

As shown in Fig. 55, the command data can be changed without affecting the operation of the DRAM field because the setting of the data for the command register is carried out only in the command register setting mode.

In order to implement this structure, the address bits Ad0 to Ad11 supplied to the DRAM field must be divided into those for selecting the row and column of the DRAM field and those for setting the command register. This is shown in Fig. 56.

As shown in Fig. 56, an address buffer 108 , which receives DRAM address bits Ad0 to Ad11, generates internal row and column addresses, locks the address bits Ad0 to Ad11 applied as row address and column address and passes them to the DRAM row decoder or DRAM -Column decoder too. Depending on the row address lock signal GRAS and the column address lock signal ΦCAS. The command register 402 takes over the DRAM address bits Ad0 to Ad11 as command data depending on the detection signal for the command register setting mode ΦSCR. Because the DRAM address bits Ad0 through Ad11 are separately supplied to the address buffer 108 and instruction register 402 , the instruction data can be set without affecting the operation of the DRAM field when the instruction register setting mode is set.

Fig. 57 shows a structure for controlling the input / output by the command data. As shown in Fig. 57, the instruction register 402 has latches 410 , 412 , 414 and 416 , which are dependent on the determination signal ΦSCR for the instruction register setting mode, for latching the supplied DRAM address bits Ad11 to Ad0. Corresponding to the DRAM address bits Ad0 to Ad11, twelve latch circuits are formed, and four latch circuits of these are shown as representatives. Latch circuit 410 latches DRAM address Ad1 and latches 412 and 414 latch DRAM addresses Ad2 and Ad3, respectively.

The input / output section has an input circuit 424 b connected to the input data terminals D0 to D3, an input circuit 424 a connected to the data input / output terminals DQ0 to DQ3 (Q0 to Q3), and an output circuit 422 connected to the Data input / output terminals DQ0 to DQ3 is connected. The activation / deactivation of one of the input circuits 424 a and 424 b is carried out by the input control circuit 423 . The input control circuit 423 activates one of the input circuits 424 a and 424 b in accordance with a signal from the latch circuit 410 formed in the instruction register 402 .

The output circuit 422 outputs data that is transmitted to the internal data output line 421 a at a predetermined time in accordance with the control signals ,1, / Φ1 and Φ2 from the output control circuit 420 . The data output mode includes a transparent mode 1, a transparent mode 2, a latch mode and a register mode. The output control circuit 402 selects the output mode in accordance with the DRAM address bits Ad2 and Ad3 supplied by the latch circuits 412 and 414 of the instruction register 402 . The operation of the input control circuit will now be described.

Fig. 58 shows a structure of the input control circuit and the input circuits. As shown in Fig. 58, the input control circuit 423 has a buffer 435 which receives an instruction CM from an instruction register 402 , an inverter buffer 434 for inverting the instruction CM and a gate 436 which is dependent on an output signal from the buffer 435 for Transfer the output signal from the input circuit 424 b to the internal write data line 421 b.

The input control circuit 424 a has an input buffer 431 for accepting the input signal DQ, which is applied as a function of the DRAM clock signal DQ, and a gate circuit 432 for transmitting the output signal of the input buffer 431 selectively to the internal write data line 421 b as a function of an output signal from the input circuit 424 b. The input buffer 431 is deactivated (set in a high output impedance state) when the output signal of the inverter circuit 434 formed in the input control circuit 423 is "L".

The command signal CM reaches the "H" level when the address bit Ad1 is at "H". This state indicates that the DQ disconnect state is set. More specifically, the input buffer 431 is deactivated and the write data D is transferred from the input circuit 424 b to the internal write data transmission line 421 b. The input circuit 424 b accepts the applied data D as a function of the DRAM master clock signal DQ and generates internal write data. If the address bit Ad1 is at "L", the command signal CM reaches the level "L". This state indicates that the ordinary DQ mode, that is, the mask activation mode has been set. In the input control circuit 423 , the gate 436 is set in the blocking state. The output signal of the input circuit 424 b is not transmitted to the internal write data line 421 b. The masking data M are output from the input circuit 424 b. The input buffer 431 accepts the data in accordance with the DRAM master clock signal DK and in accordance with the masking data M and selectively transmits the internal write data via the gate 432 to the internal write data transmission line 421 b. This allows masking to be performed while data is being written.

Fig. 59 shows an example of a specific structure of the output circuit. As shown in Fig. 59, the output circuit 422, a first output latch 981, the / is dependent on the output control circuit 420 of control signals Φ1 and Φ1, for latching data on read data buses DB and FDB (data line 421 a), a second output latch 982 , which is dependent on a clock signal Φ2, for transferring latch data of the first output latch 981 or data on the data buses DB and * DB, and an output buffer 983 which receives data from the output latch 982 and is dependent on the output signal from gate circuit 984 for transferring the data as output data to an external terminal DQ. Gate circuit 984 receives a signal ΦDES indicating the SRAM lock state and an output enable signal ΦG which is generated in synchronism with the output enable signal G #. When the output of gate circuit 984 is "H", output buffer 983 is placed in a high output impedance state.

The first output latch 981 has clock signal inverters ICV1 and ICV2, which are activated as a function of clock signals Φ1 and / Φ1. The input or output of the clock signal inverter ICV1 is connected to the output or input of the clock signal inverter ICV2. When the clock signal Φ1 is at "H", the clock signal inverters ICV1 and ICV2 are activated, and the first output latch 981 is thus put into the locked state. If the clock signal Φ1 is at "L", the clock signal inverters ICV1 and ICV2 are deactivated. Therefore, the first output latch 981 does not lock.

When the clock signal Φ2 is at "L", the second output latch 982 locks the data supplied to its inputs A and * A and outputs it at the outputs Q and * Q. If the clock signal Φ2 is at "H", the second output latch 982 outputs the data at outputs Q and * Q which were locked when the clock signal Φ2 was at "L". This happens regardless of the signal states at inputs A and * A. The clock signals Φ1, / Φ1 and Φ2, which control the locking process, represent signals which are synchronized with the master clock signal K (DRAM master clock signal DK) and the times of their generation are controlled by the output control circuit 420 .

Fig. 60 shows an example of a specific structure for the second output latch 982nd As shown in FIG. 60, the second output latch 982 has a D flip-flop DEF which receives the clock signal .phi.2 at its D input, the signal applied to input A (* A) and its clock signal input CLK. The output signal Q (* Q) of the second output latch 982 is output at the output Q of the D flip-flop DEF. The D flip-flop DFF works with rising edge triggering takes over the signal fed to input A when the clock signal Φ2 drops to "L". It outputs the adopted input signal A continuously as long as the clock signal Φ2 is at "L".

If the clock signal Φ2 is at "H", it outputs the previously locked data continuously regardless of the state of the input signal A which is fed to its input terminal D. D flip-flops DFF are formed for inputs A and * A, respectively. The second output latch 982 can have a different structure, and any circuit structure can be used provided that it can realize the latch state and the pass state depending on the clock signal Φ2.

Fig. 61 is an example of a specific structure shows the output control circuit 420. The output control circuit 420 has delay circuits 981 a, 981 b and 981 c, for delaying the master clock signal K by a predetermined period of time, a single pulse generation circuit 982 a, which is dependent on the output signal of the delay circuit 981 a, for generating a single pulse signal with a predetermined Pulse width, a single pulse generation circuit 982 b, which is dependent on the output signal of the delay circuit 981 , for generating a single pulse signal with a predetermined pulse width and a single pulse generation circuit 982 , which is dependent on the output signal from the delay circuit 981 c, for generating a single pulse signal with a predetermined pulse width. From the single pulse generating circuit 982 a, the clock signals are generated Φ1 and / Φ1. The output signals from the single pulse generation circuits 992 b and 992 c are supplied to an OR circuit 993 . The OR circuit 993 generates the clock signal Φ2. The delay by the delay circuit 991 b is shorter than that by the delay circuit 991 c. The single pulse generation circuits 992 a to 992 c are activated / deactivated in accordance with a command value which is generated from two bits of the address bits Ad2 and Ad3 by the command register. When these two bits of command data (addresses Ad2 and Ad3) indicate the latch mode as the output mode, the single pulse generation circuits 992 a and 992 c are activated and the single pulse generation circuit 992 b is deactivated. The operation of the data output circuit will be described with reference to Figs. 59 to 61.

i) Latch output mode.

In Fig. 62, the operating signals in the latch output mode are shown. The latch output mode is set by setting the address bit Ad3 to "L" and the address bit Ad2 to "H" in the command register setting mode. At this time, the single pulse generation circuits 992 a and 992 c are activated. It is assumed that the output enable signal G # is active "L", which indicates the data output, and that the gate circuit 994 of FIG. 59 activates the main amplifier 993 . It is also assumed that the SRAM read mode has been set as the output mode.

With the rising edge of the master clock signal K, the SRAM address As (An) transferred to the address buffer, in the SRAM A corresponding SRAM word line SWLn is selected in the field and data RDn appear on the SRAM bit line pair SBL.

The single pulse generation circuit 992 a generates a single pulse depending on the rise of the master clock signal K, which is held at "L" for a predetermined period of time at a predetermined time. When the clock signal Φ1 drops to "L", the lock function of the first output latch 981 is disabled. At this time, the clock signal Φ2 is "H" and the second output latch 982 maintains the latch state to latch and output the data Qn-1 that was read in the previous cycle.

Among 64 bits (16 × 4) of the data RDn on the SRAM bit line pairs SBL which have been selected in accordance with the external address As, four bits of data which are selected in accordance with the block address are transmitted to the internal output data buses DD and * DD . The clock signal -1 rises to "H" as soon as the data DBn on the data buses DB and * DB are stabilized. This puts the first output latch 981 in the locked state to lock the stabilized data DBn.

Then a single pulse is generated by the single pulse generation circuit 992 c and the signal Φ2 drops to "L". The second output latch 982 takes over the data DBn, which has been locked by the first output latch 981 , as a function of the drop in the signal und2 and transfers the data via the output buffer 983 to the output terminal DQ.

The generation of the clock signal Φ2 is carried out in synchronization with the drop in the master clock signal K, and, depending on the drop in the master clock signal K, the data DBn selected in this cycle are output as output data Qn. The next rise in the master clock signal K causes the clock signal Φ2 to rise to "H". The second output latch 982 continuously outputs the stabilized data DBn regardless of the value on the internal output data buses DB and * DB.

The clock signal ignal1 then drops to "L" and releases the latch state of the first output latch 981 , so that it is ready for the next cycle, that is to say for the next stable data to be locked. By repeating the above-described operations, data read in the previous cycle is successively output as stabilized data depending on the rise of the master clock signal K.

ii) Register output mode.

The register output mode will be described with reference to FIG. 63. The register output mode is set by setting the address bit Ad3 to "H" and the address bit Ad2 to "L" in the instruction register setting mode. In the register output mode, the single pulse generating circuit 992 activates b and the single pulse generating circuit 992 c disabled. In this case, a single pulse which falls to "L", produced b in response to the rise of the master clock signal K of the one-shot pulse generating circuit 992nd Because the clock signal Φ1 is "H", the second output latch 992 latches the data DBn-1 that was read in the previous cycle.

In the register output mode, the time at which the Clock signal Φ to "L" depending on the rise of the master Clock signal K set. Therefore, in the (n + 1) th cycle of the Master clock signal K the data DBn of the nth clock cycle as Output data Qn is output at the output terminal DQ. More accurate said, the latch output mode is different from that Register output mode only by the time of activation, that is, the time of the transition of the clock signal Φ2 "L". Therefore, both the latch output mode and the data, that have been read in the immediately preceding cycle,  and then data is output in the current cycle read, output as well as the register output mode, in the data read in the nth cycle in the (n + 1) th Cycle will be realized.

iii) Transparent output mode.

The transparent output mode will be described with reference to FIG. 64. First, the first transparent output mode will be described with reference to Fig. 64A. The first transparent output mode is set by setting the address bits Ad2 and Ad3 to "L". In the first transparent output mode, the clock signals Φ1 and Φ2 are kept at "L". At this time, the first output latch 981 is not latched, and the internal output latch 982 is also in the on state. In this case, therefore, the read data DBn that have been transferred to the internal data buses DB and * DB are not locked, but rather are output directly as output data Qn. Therefore, when the value on the SRAM bit line SBL is invalid (INV), invalid data INV appears at the output terminal DQ.

The second transparent output mode (transparent 2) is set by setting the address bits Ad2 and Ad3 to "H". As shown in Fig. 64B, the clock signal Φ1 is generated when the second transparent output mode is set. While the clock signal Φ1 is at "H", the first output latch 981 performs a lock operation. Therefore, even if the value RDn on the SRAM bit line pair SBL is invalid, the value on the data buses DB and * DB from the first output latch 981 is locked as a valid value and output for a predetermined period of time (as long as the clock signal Φ1 is at "H" lies). Therefore, the period of time during which invalid data INV is output becomes shorter. In the second transparent output mode, the clock signal Φ2 is also kept at "L".

In the structure described above, a D flip-flop with falling edge triggering is used as the second output latch 982 . A latch circuit with rising edge triggering can be used if the polarity of the clock signal Φ2 is changed. The first output latch 981 can be implemented by other latches.

In the operation of signal diagrams of FIGS. 62 to 64B, the chip enable signal E # and output enable signal G # are both held at an active "L". This indicates that no high impedance state should be set in each clock cycle. The setting of the high impedance output state by the chip activation signal E # and the output activation signal G # will now be described.

[Data output clocking] [Transparent output mode]

FIG. 65A and 65B show the relationship between the output data and the Chipakivierungssignal E # and the output enable signal G # in the transparent output mode. In the transparent output mode, the data is transferred directly to the output buffer on the internal data buses DB and * DB. If the chip activation signal E # with the rising edge of the master clock signal K is at "H", the SRAM blocking state is assumed and the output state of high impedance is set. When the output enable signal G # is "H", the output state of high impedance is set.

It is assumed that the output enable signal G # is already active "L", as shown in Fig. 65A. In this state, data reading is performed in this cycle when the chip activation signal E # is at "L" with the rising edge of the master clock signal K. After the time period tKHQZ has passed from the rising edge of the master clock signal K, the output state of high impedance is released and read data are transmitted. After the time period tKHA has passed from the rising edge of the master clock signal K, valid data is output.

Is the chip activation signal E # with the rising edge of the master clock signal at "H" becomes high Output impedance is set after the time period tKHQX of the rising edge of the master clock signal K has elapsed is.

When a data read operation is performed for the rising edge of the master clock signal "K" as the chip enable signal E # drops to "L", as shown in Fig. 65B, this cycle becomes a data read cycle. If the output enable signal G # falls to "L" after the chip enable signal E #, the data read in this cycle (cycle 1 in Fig. 65B) is output as valid data after the time tGLQ has elapsed since the output enable signal G # has dropped. Similarly, when the chip enable signal E # is set to "L" with the rise of the master clock signal K, the data read in this cycle (cycle 2) is output in a similar state to that shown in Fig. 65A. If the output activation signal G # is raised to "H" in this cycle, the output state of high impedance is set after the lapse of the time period tGHQ.

The states of the signals indicated by broken lines in Figs. 65A and 65B show that the output value represented by the broken line appears when the state of the chip activation signal E # indicated by the broken line is set.

[Register Output Mode]

This is an output mode in which an output register is formed between the output buffer and the internal data buses DB and * DB. The data is output with a delay of one cycle. More specifically, as shown in Fig. 66A, the first cycle of the master clock signal K represents a read mode when the chip enable signal E # is lowered to "L" in the first cycle of the clock signal K while the output enable signal G # is at "L" . The data read in cycle 1 99999 00070 552 001000280000000200012000285919988800040 0002004337740 00004 99880 is read in the next cycle 2. That is, the read data is output after the lapse of the time period tKHQZ from the rising edge of the next master clock signal, and valid data are output after the lapse of the time period tKHAR. After the time tKHQX has elapsed from the rising edge of the master clock signal K in the next clock cycle 3, the output state of high impedance is set. If the chip activation signal E # is again set to "L" in cycle 2, valid data are output in cycle 3, as shown by the broken line in FIG. 66A.

It is assumed that the data read operation is carried out by lowering the chip activation signal E # to "L" in the state of high output impedance with the output activation signal G # at "H". In this state, as shown in Fig. 66B, the data read in cycle 1 is output as valid data after the lapse of the period tGLQ from the drop of the output activation signal G # in the second cycle. If the chip activation signal G # is "L" in the second cycle, valid data are output in cycle 3. If the output activation signal G # is raised to "H" in the clock signal cycle 3, the initial state of high impedance is set after the lapse of the time period tGHQ.

[Latch output mode]

The latch output mode represents an output mode in which an output latch circuit is formed between the output buffer and the internal data buses DB and * DB. It is assumed that the data read operation is carried out by lowering the chip activation signal E # to "L" in the first cycle of the master clock signal K (as shown in Fig. 67A). In this case, data is output in the first cycle after the lapse of the time tKLQZ from the falling edge of the master clock signal K. After the time span tKLA has elapsed from this falling edge, valid data are output. After the time period tKLQX has elapsed from the falling edge of the clock signal of the next clock signal cycle (cycle 2), the data are set in accordance with the initial state of high impedance. If the chip activation signal E # has been lowered to "L" in cycle 2, data is output after the lapse of the time period tKLQZ from the fall of the master clock signal K (as shown by the dashed line). In the process shown in Fig. 67A, the output enable signal G # is already at "L". As shown in Fig. 67B, it is now assumed that the output enable signal G # later falls to "L". If, by lowering the chip activation signal E # in the first cycle of the master clock signal K, data reading is carried out, and in this first cycle of the master clock signal K the output activation signal G # is lowered to "L", the data read in cycle 1 become after the elapse of the Time period tGLQ is output from the falling edge of the output activation signal G #. If data reading is carried out again in cycle 2, the data read in cycle 2 are output after cycle time tKLQZ has elapsed from the falling edge of master clock signal K in cycle 2. If the output activation signal G # is subsequently raised to "H" (provided that no output control is carried out by the chip activation signal E #), after the lapse of the time period tGHQ, the output state of high impedance is set from the rising edge of the output activation signal G #.

In transparent output mode, the length of time during which the output data is valid, only that period of time during the valid data appear on the internal buses. In this Latch output mode will be the read data for the output locked, and therefore valid data is kept even during the Time period spent during which invalid data on the internal data buses appear. Therefore, it can be sufficient Time period to be made available for the CPU or another device as an external processing unit is necessary to accept the output data. In this Register output mode will use the data from the previous cycle a delay of one cycle. In this case a so-called pipeline operation can be implemented,  thereby realizing high-speed data reading leaves. By setting the output modes described above in A match can be made with the command data in the command register Users choose the output mode that is appropriate for the system suitable is.

[Signal parameters]

Fig. 68 shows in a table the setting and holding times that are required for the respective signals. The operating mode of the CDRAM is determined by the combination of states of the control signals with the rising edge of the master clock signal K, and the CDRAM carries out the specified operation in accordance with the determined operating mode. The externally applied signals are all supplied in the form of pulses. The set time required for the external signals (the time required to set the signal to a stable level with the rise of the master clock signal K) and the hold time (the time to hold the signal stable after the rise of the master clock signal K is required) match for all external signals. Therefore, an external device can easily determine the timing of signal generation because the timing for generating signals and the timing for setting the signals to a stable state can be made the same for all signals.

The minimum clock cycle time of the master clock signal K is 8 ns and the maximum clock cycle time is the same 100 ns. The master clock signal K has an "H" time tKH and one "L" time tKL on. The DRAM clock mask signal CMd has one Response time tCMDS and a hold time tCMDH. The Row address scan signal RAS # has a response time tRS and a hold time tRH. The column address strobe signal CAS # points a setting time tCS and a holding time tCH. The Data transfer determination signal DTD # has a set time tDTS and a hold time tDTH. The SRAM clock mask signal CMs has a response time tCMsS and a hold time tCMsH. The Chip activation signal E # has a response time tES and a Stop time tHE.  

The write activation signal WE # has a response time tWS and a holding time tWH. The control clock signal CC1 # has one Response time tC1S and a hold time tC1H. The control signal CC2 # has a response time tC2S and a hold time tC2H. The DRAM address bits Ad0 to Ad11 and the SRAM address bits As0 to As11 have a response time tAS and a hold time tAH. The Mask activation signals N0 to N3 have one Response time tMS and a holding time tNH. The input data DQ0 to DQ3 or D0 to D3 have a response time tDS and a Holding time tDH. The response time is at least 2 to 3 ns, while the hold time is at least 3 to 4 ns. The Rise / fall time of the internal signal is 2 ns (if it is changes in the range from 0 V to 3 V).

[Connection arrangement]

Fig. 69 shows the shape of a case containing the CDRAM according to the present invention and the connection arrangement. The CDRAM is in a Type II TSOP (thin small outline package), with a connection spacing of 0.65 mm and 400 mil thickness.

The connections with the numbers 1, 15, 17, 31, 46 and 48 will a supply voltage Vcc is supplied. The ground potential Vss becomes the connections with the numbers 12, 16, 20, 32, 43, 47, 51 and 62 fed. The DRAM address bits Ad0 to Ad11 are sent to the Connections with the numbers 2 to 4, 28 to 30, 33 to 35 and 59 up to 61. The SRAM address bits As0 to As11 are the Connections with the numbers 22 to 24, 37 to 41 and 53 to 56 fed. The control clock signals CC2 # and CC1 # are the Connections with the numbers 5 and 6 supplied. The Write activation signal WE # and the chip activation signal E # are fed to the connections with the numbers 7 and 11 respectively. The DRAM clock mask signal CMd and the SRAM Clock masking signal CMs is sent to the connectors with the numbers 9 or 10 created.

The master clock signal K is the connection with the number 11 fed. The row address strobe signal RAS #, the column address  Strobe signal CAS # and the data transfer designation signal DTD # are fed to the connections with the numbers 25 to 27. The input data D0 to D3 or the Mask activation signals M0 to M3 are applied to the Connections with the numbers 13, 19, 44 and 50 created. The Connections with the numbers 14, 18, 45 and 49 are used for this Output data Q0 to Q3, or they are output as Input / output data connections DQ0 to DQ3 used.

The connections with the numbers 36, 42, 52, 57 and 58 are not connected (NC).

In the connection arrangement shown in FIG. 69, the supply voltage Vcc and the ground potential Vss, which are supplied in the middle section of the housing, are used for the data input / output section. The ground potential Vss and the supply voltage Vcc, which are supplied to the connections with the numbers 12 and 15, respectively, are used for driving the data M0 / D0 and DQ0 / Q0, which occur at the connections with the numbers 13 and 14. The supply voltage Vcc and the ground potential Vss, which are supplied to the connections with the numbers 17 and 20, are used for the circuit which drives the data DQ1 / Q1 and M1 / D1 at the connections with the numbers 18 and 19. The ground potential Vss and the supply voltage Vcc which are applied to the connections with the numbers 43 and 46 are used for the circuits for driving the data M2 / D2 and DQ2 / Q2 which occur at the connections with the numbers 44 and 45. The supply voltage Vcc and the ground potential Vss supplied to the connections with the numbers 48 and 51 are used for the circuit for driving the data DQ3 / Q3 and M3 / D3 which occur at the connections with the numbers 49 and 50. The supply voltage and the ground potential are distributed to the respective circuits in such a way that the influence of internal interference is reduced.

In the embodiment described above, data input / output is carried out via the bit lines of the SRAM array. The data input / output can also not be carried out via the bit lines of the SRAM field, but the data can be input / output via the connection section of the SRAM field and the bidirectional transmission gate. In this case, a sense amplifier / IO block 122 and the SRAM column decoder 120 may be arranged between the SRAM array 104 and the bidirectional data transmission circuit 106 of the structure of FIG. 1.

For the structure shown in FIG. 1, the four command bits (command (0) to (3)) which are applied by the DRAM address buffer 108 to the bidirectional data transmission circuit 106 have not yet been described. These are used to set the mode of operation in the data transmission circuit, and they can similarly be used in the second embodiment. Therefore, the details will be described later.

Embodiment 2

Fig. 70 shows the overall structure of CDRAM according to a second embodiment of the present invention. In Fig. 70, the portions corresponding to the components of the CDRAM shown in Fig. 1 are given the same reference numerals, and therefore, their detailed description is not repeated here.

In the CDRAM shown in FIG. 70, a column decoder 120 and a sense amplifier / IO block 122 are formed between the bidirectional data transfer circuit 106 and the SRAM array 104 . This structure enables direct access to each buffer of the bidirectional data transmission circuit 106 from the outside.

The CDRAM shown in Fig. 70 has a mask circuit 1436 and a Din buffer 1434 that receive external data DQ0 to DQ3 and M0 to M3 (or D0 to D3) in an input / output circuit 1435 , and a main amplifier circuit 1438 for outputting data to the connections DQ0 to DQ3 (or Q0 to Q3). The data output clock to the main amplifier circuit 1438 from the input / output circuit 1435 is set by the external output enable signal G #, and the data input / output clock is set by a DQ control signal DQC.

The DQ control signal DQC controls only the activation / deactivation of the input / output circuit 1435 . If the DQ control signal DQC is "H", the input / output circuit is activated. If the DQ control signal DQC is "L", the Din buffer 1434 , the masking circuit 1436 and the main amplifier circuit 1438 are deactivated. In the common DQ arrangement, the write activation signal WE # determines whether the Din buffer circuit 1434 or the main amplifier circuit 1438 is to be activated.

In the CDRAM shown in Fig. 70, the chip select signal CS # is supplied to a K buffer clock signal generating circuit 1424 . The K-buffer clock signal generation circuit 1424 also receives an external master clock signal K. The chip select signal CS # controls only the operation of the DRAM field, the operation of the SRAM field, the data transfer between the DRAM field and the SRAM field Data transmission between the data transmission circuit and the DRAM field and the data transmission between the data transmission circuit 106 and the SRAM field. The other structures are essentially the same as those shown in FIG. 1. However, the control clock signal supplied to the SRAM control circuit 143 is referred to as the control clock signal CC0 # or CC1 #. With the changed designation of these signals, the types of data transmission have also changed. The data transfer process will be described in detail later.

Also in FIG. 70, CDRAM is selected to have memory cell blocks (16 bits) selected at once in a DRAM array 102 (a memory section) by column block decoder 112 . In SRAM field 104 , 16 bits of memory cells are connected on one row. Correspondingly, the bidirectional data transmission circuit has transmission gate buffers with 16 bits. The function of the DQ control DQC is described.

[DQ control]

FIG. 71 shows a specific structure of the K buffer clock signal circuit and the marker circuit shown in FIG. 70. In the CDRAM shown in Fig. 70, the activation / deactivation of the DRAM control circuit 128 and the SRAM control circuit 432 is controlled by the chip select signal CS #. In the CDRAM of FIG. 1, only the SRAM control circuit 132 is controlled by the chip activation signal E #. Therefore, the control signal buffer (a circuit for locking external control signals) included in the DRAM control circuit 128 operates only in response to the DRAM master clock signal DQ, as shown in FIG. 31. In the DRAM shown in FIG. 70, both the DRAM control circuit and the SRAM control circuit take over the applied data in accordance with the master clock signal K and the chip selection signal CS #. In Fig. 71, the SRAM control circuit and the DRAM control circuit are shown as a control circuit 1452nd

As shown in Fig. 71, the K buffer clock circuit 1424 includes a K buffer 1460 , which receives the master clock signal K, for generating an internal clock signal and a CS buffer 1462 which is dependent on an internal clock signal K buffer , to accept the chip selection signal CS #. The mask circuit 1450 (referring to the mask circuits 126 and 130 shown in Fig. 70) has a shift register 1464 , which is dependent on the internal clock signals K buffer 1460 , for outputting the clock mask signal CM with a delay of one clock cycle and a selection gate 1466 for selectively passing the internal clock signal from the K buffer 1460 to generate the master clock signal Ki in accordance with the masking data from the shift register 1464 . In this second embodiment, when the mask value CM is at "L", the generation of the internal master clock signal Ki is inhibited.

The control circuit 1452 is activated when it receives the internal chip selection signal CS from the CS buffer 1462 at its activation input INA. The control circuit 1452 operates in accordance with the master clock signal Ki from the mask circuit 1450 when it is in the active state. Therefore, when the chip select signal CS is at an inactive level "H", the CDRAM is not selected and the control circuit 1452 is deactivated.

Fig. 72 shows a structure for the control circuit 1452nd The output activation signal G # is generated asynchronously to the master clock signal K. At this time, the DQ control signal DQC can be generated asynchronously to the master clock signal K.

The activation / deactivation of the DRAM control circuit and the SRAM control circuit is controlled by the chip selection signal CS. The external control clock signals RAS #, CAS #, DTD #, CC0 #, CC1 #, DQC and WE # are taken over in accordance with the master clock signal K and the chip selection signal CS. Therefore, the structure of the buffer circuit that takes over the external control signals is the same as that of FIG. 6. Therefore, the control signal buffer 1480 is shown, which represents buffers for accepting the external control clock signals. The control clock signal ΦE # represents the external control signals.

As shown in FIG. 72, the control circuit 1452 has a control signal buffer 1480 , which is dependent on the master clock signal K and the chip selection CS #, for taking over the external control clock signal ΦE and a control signal generation circuit 1482 which is based on the chip selection signal CS and the master Clock signal Ki is dependent on for generating the necessary control signals in accordance with a state combination of the control signals which are applied by the control signal buffer 1480 .

The DRAM address buffer 108 has the same structure as shown in Fig. 31, and the SRAM address buffer 116 has the same structure as shown in Fig. 6 (except that the chip select signal CS is applied in place of the chip enable signal I). The structures of the K buffer and the CS buffer are the same as those shown in Fig. 7. As shown in Figs. 71 and 72, the control circuit 1452 is deactivated when the chip select signal CS is "H", and therefore no internal operation is performed. This state does not affect the signal states of the clock mask signal CM. More specifically, the control circuit 1452 is deactivated when the chip select signal CS is "H" regardless of whether the master clock signal Ki is applied or not.

If the clock mask signal CM is at "L", the master clock signal Ki is not generated in the next cycle. As can be seen from the structure shown in Fig. 72, no new external control signal ΦE # is adopted in the control circuit 1452 , so when the clock mask signal CM reaches a level "L", no master clock signal Ki is generated in the next cycle, and therefore the state of the previous cycle is maintained in control circuit 1452 . Specifically, if the chip select signal CS is "H" in the previous cycle, the control circuit 1452 is in an inactive state. At this time, the control circuit 1452 is kept in the state of the previous cycle even if the chip select signal CS changes to the active level "L" because no master clock signal Ki is applied. Namely, the CDRAM enters the power saving mode (both the DRAM section and the SRAM section).

The chip activation signal CS is in the previous cycle at the active level "L" and reaches the clock mask signal CM in the current cycle level "L", no master Clock signal Ki applied even if the chip selection signal CS # im next clock cycle set to an inactive level "H" becomes. Therefore, this cycle will be the same as in the previous one Cycle output data continues to be output.

Fig. 73 shows a structure for controlling the operation of the input / output circuit 1435 of Fig. 70. As shown in Fig. 73, the input / output control circuit has a G buffer 1492 , which takes the output enable signal G # asynchronously to the clock signal K, for Generating an internal output enable signal, and a DQC buffer 1490 , which is dependent on the chip select signal CS and the internal master clock signal Ki, for accepting the external DQ control signal DQC # for generating the internal DQ control signal DQC. A structure can be used as the DQC buffer 1490 , in which, like the output activation signal G #, the DQ control signal DQC # is adopted asynchronously to the master clock signal K for generating the internal DQ control signal.

The input / output circuit 1435 has a Din buffer 1434 , the activation / deactivation of which is controlled in dependence on an output signal from the DQC buffer 1490 , and a gate circuit 1494 , the internal DQ control signal DQC, the internal output activation signal G and the chip selection signal CS for activation / deactivation of the main amplifier circuit 1438 receives. When the DQ control signal DQC reaches the "H" level, the output enable signal G reaches the "L" level and the chip select signal CS reaches the "L" level, the gate circuit 1494 activates the main amplifier circuit 1438 . When the chip select signal CS is "H", the main amplifier circuit 1438 is placed in a high output impedance state. It is put in a high output impedance state even when the DQ control signal DQC is "L".

The Din buffer 1434 is activated / deactivated by the internal DQ control signal DQC from the DQC buffer 1490 . The internal write determination signal ΦW determines whether or not write data should be generated. Specifically, the Din buffer 1434 generates the internal write data when the DQ control signal DQC is "H" and the data write determination signal ΦW is activated.

Fig. 74 shows a control sequence of output states by the output enable signal, the DQ control signal and the chip select signal. As shown in Fig. 74, in the first cycle of the master clock signal K, the chip select signal CS # is at "H" and the first cycle is a NOP cycle (no operation). The DRAM control circuit and the SRAM control circuit do not operate and the output is placed in a high impedance state.

In the second cycle of the master clock signal K, if that Chip selection signal CS # on "L" field, that Output enable signal G # at "L" and the DQ control signal DQC is at "H", a data read operation is performed (the operation is performed by combining the states of the other control signals set; whose operation is not here but later described in detail) and the value Q1 is spent.

In the third cycle of the master clock signal K, if that Chip selection signal CS # again reaches level "H", the NOP mode set and the CDRAM does not work. Hence it will again placed in a high output impedance state.

In the fourth cycle of the master clock signal, if that Chip selection signal CS # again reaches level "L", is in Correspondence with the address As at that time is created, a data read is carried out, and the read value Q2 is issued.

In the fifth cycle of the master clock signal K, even if both the chip selection signal CS # as well as the output activation signal G # are both at "L", the input / output circuit operates not because the DQ control signal DQC is at "L". Therefore there is a state of high output impedance in this cycle.

If the chip selection signal CS # is at "L" in the sixth cycle is set, the DQ control signal DQC is set to "H" is set and the output activation signal G # is in this Cycle raised to "H". The output is dependent on Rise of the output enable signal G # to a high state Impedance offset. According to the increase in Output enable signal G # turns on for a short period of time stabilized or non-stabilized value output  

Because the chip select signal CS # and the DQ control signal DQ can be fed separately, as described above, only that Data input / output are controlled by the DQ control signal DQC, while an internal operation is carried out in the CDRAM. A Memory expansion and bank switching of the cache DRAM can easily implemented and the degree of freedom of banking Structure can be enlarged. This example will now described.

[Change of the memory structure by the DQ control]

Fig. 75 shows an example of the structure of a memory system for a CPU as an external processing unit that requires data with a width of 32 bits. As shown in FIG. 75, CDRAMs CDR # 0 to CDR # 7, each performing 4-bit data input / output, are connected to a 32-bit data bus 1002 . The input / output of the CDRAMs CDR # 0 and CDR # 1 are controlled by the DQ control signal DQC-0. The data input / output of the CDRAMs CDR # 2 and CDR # 3 are controlled by the DQ control signal DQC-1. The data input / output of the CDRAMs CDR # 4 and CDR # 5 are controlled by the DQ control signal DQC-2. The data input / output of the CDRAMs CDR # 6 and CDR # 7 is controlled by the DQ control signal DQC-3.

Not only the chip selection signal CS #, but also other control signals are jointly applied to the CDRAMs CDR # 0 to CDR # 7. In Fig. 75, the chip select signal CS # is only shown as a representative. In the memory system shown in Fig. 75, the memory is controlled byte by byte. This is because the data is 8-bit units when a value is 32 bits. Therefore, when the DQ control signals DQC-0 to DQC-3 are activated at the same time, input / output of data of 32 bits is carried out, and when a DQ control signal DQC-i is activated, a value of 8 bits can be obtained. Therefore, values with 8 bits, values with 16 bits and values with 32 bits can be easily achieved as output values. In this case, the chip select signal CS # is commonly applied to all CDRAM CDR # 0 to CDR # 7, and an operation is carried out therein. Therefore, data input / output can be carried out at high speed by controlling only the DQ control signals DQC-0 to DQC-3. This structure enables the memory system structure to be easily changed if the data bus comprises 16 bits, 32 bits or even 64 bits.

When the width of the data bus is fixed, it becomes common a bank structure is used to increase the storage capacity. Switching the bank structures can be done easily become. The following is a bank switch using of the DQ control signal described.

Referring to Fig. 76, it is assumed that a memory system is formed by using 8 CDRAMs each with 4M _* 4 bits or with 4 memory layers each with a storage capacity of 4 megabits. As in the case of Fig. 75, 2 CDRAMs form a set and the input / output control is carried out byte by byte.

In this case, as shown in Fig. 75, 256 sets are cached (SRAM), each set having a block of 32 bits * 16 bits because a CDRAM has a * 4-bit structure. This results in a total of 4 (bits) _* 8 (CDRAMs) = 32 bits, and 16 bits of memory cells are connected to one row of the SRAM field. As with the structure of the main memory (DRAM field), blocks (16 bits) with a width of 32 bits are arranged for one page in this case. The number of pages is 4 KPages because it corresponds to the number of word lines. One page has 64 blocks. It is believed that a memory system with twice the storage capacity, i.e. 32 megabits, is formed by using the memory system having the structure described above.

Fig. 78 shows an example of the storage system architecture. As shown in Fig. 78 can be selected by the chip select signal CS # 0 CDRAMs CDR # 0 to # 7, and CDR by the chip select signal CS # is the CDRAMs CDR # 8 to CDR # 15. The data input / output of the CDRAMs CDR # 0, CDR # 1, CDR # 8 and CDR # 9 is controlled by the same DQ control signal DQC-0. Similarly, a common DQ control signal DQC is applied to the CDRAMs arranged in the vertical direction of the drawing.

In the memory system architecture shown in Fig. 78, the CDRAMs CDR # 0 to CDR # 7 or the CDRAMs CDR # 8 to CDR # 15 are selected and operated. Therefore, of the 16 CDRAMs, ie CDRAMs CDR # 0 to CDR # 15, always work 8. This is half of all CDRAMs that are present in the memory system and therefore the power consumption can be reduced.

As shown in Fig. 79, however, the block size is not changed even though the number of sets of the cache is increased. More specifically, as shown in Fig. 79, the cache CAC # 1 can perform data transfer with the main memory MEM # 1, and the cache CAC # 2 can perform data transfer with the main memory MEM # 2 only. The reason for this is that the data transfer can only be carried out between the corresponding cache and the main memory.

Figure 80 shows another example of a memory system using the DQ control signal. As shown in Fig. 80, the memory system 16 has CDRAMs CDR # 0 to CDR # 15. In the memory system of FIG. 80, two kinds of control signals DQ DQC, i.e., DQ0 and DQ1 used. When these two DQ control signals DQC0 and DQC1 are both activated, the corresponding CDRAM is put into the active input / output state. For the CDRAMs CDR # 0 to CDR # 7, the second DQ control signal DQC1-0 is supplied together. For the CDRAMs CDR # 8 to CDR # 15, a second DQ control signal DQC1-1 is supplied together.

For the CDRAMs CDR # 0, CDR # 1, CDR # 8 and CDR # 9, the first DQ Control signal DQC0-0 applied. For CDRAMs CDR # 2, CDR # 3, CDR # 10 and CDR # 11 becomes the first DQ control signal DQC0-1 fed. Similarly, for CDRAMs CDR # 4, CDR # 5, CDR # 12 and CDR # 13 the DQ control signal DQC0-2 applied, and for CDRAMs CDR # 6, CDR # 7, CDR # 14, CDR # 15 becomes the DQ control signal DQC0-3 fed.  

For the CDRAMs CDR # 0 to CDR # 15, the chip selection signal CS # fed together. Similarly others Control clock signals common to CDRAMs CDR # 0 to CDR # 15 created (not shown).

In the structure of the memory system shown in Fig. 80, the activation / deactivation (selection / non-selection) of the CDRAMs CDR # 0 to CDR # 15 is controlled together by the chip selection signal CS #. The data input / output is controlled by the DQ control signals DQC0 and DQC1. When the chip select signal CS is activated, driving of the DRAM field, driving of the SRAM field and internal data transmission are generally carried out in the CDRAMs CDR # 0 to CDR # 15. Therefore, the block size of the cache is twice that of the structure shown in Fig. 79. Half of the area of the doubled cache block is controlled by the second DQ control signal DQC1 (DQC1-0 and DQC1-1).

Since only the data input / output is controlled by the DQ control signal as shown in Figs. 78 to 81, a high impedance output state can be realized in bank switching while the CDRAM is operating internally, and data input can be inhibited , so that erroneous data input / output during bank switching can be prevented.

When the bank switching is carried out using two kinds of DQ control signals as shown in Fig. 80, only the data input / output is controlled by the DQ control signal, and an internal operation of the CDRAM is carried out. Therefore, data input / output can be performed faster when switching banks.

Fig. 82 shows a structure for realizing the memory system of Fig. 80. As shown in Fig. 82, a gate circuit 1100 which receives the first DQ control signal DQC0 and a second DQ control signal DQC1 is formed. Gate circuit 1100 may be formed at the subsequent stage of the DQC buffer in the structure of FIG. 73 or at the previous stage of the DQC buffer. When both the first and second DQ control signals DQC0 and DQC1 reach the active "H" state, the gate circuit 1100 activates the DQ control signal and applies it to the gate circuit 1494 shown in FIG. 73 and to the Din Buffer 1494 . By using the gate circuit shown in Fig. 82, the buffer can be easily switched and the memory enlarged.

[General functional structure]

Fig. 83 shows the functional structure of the CDRAM according to the second embodiment. As shown in Fig. 83, the DRAM array DRA has a memory capacity of 4K rows * 64 columns _* 16 blocks _* 4 (IO). 64 columns of DRAM bit line pairs are arranged in one block and one column is selected in one block.

The SRAM field SRA has a memory capacity of 256 rows _* 16 columns _* 4 (IO). A row is selected in the SRAM field, and data transfer can be performed between the selected row of 16 bits and 16 bits (1 bit of each block) selected in the DRAM field.

The column decoder COLD selects DTBR (16 bits _* 4 (IO)) from the read data transfer buffer and transmits the read data to the data input / output terminal DQ via the IO circuit IOC. The column decoder COLD also transmits the 4 bits of data supplied from the IO circuit IOC to the corresponding 4 bits of the write data transfer buffer DTBW (16 bits _* 4 (IO)). The column decoder COLD also writes 4 data bits from the IO circuit IOC in 4 bits to memory cells of the SRAM field SRA when data writing is carried out. As will be described later, the column decoder COLD also has the function of transferring 16 _* 4 bits of data stored in the read data transfer buffer DTBR to the write data transfer buffer DTBW (the structure will be described later). The DRAM control circuit 128 (see FIG. 70) controls the data transfer from the DRAM field DRA to the read data transfer buffer DTBR and the data transfer process from the write data transfer buffer DTBW to the DRAM field DRA. An operating mode in which data is transferred simultaneously to the read data transfer buffer DTBR at the time of data transfer from the write data transfer buffer DTBW to the DRAM field is newly created, as will be described later. This data transmission is also controlled by the DRAM control circuit 128 .

The SRAM control circuit 1432 (see Fig. 70) controls the data reading from the SRAM field SRA to the data input / output terminal DQ, the data writing from the data input / output terminal DQ to the SRAM field SRA, the data transfer from the read data transfer buffer DTBR to the SRAM field SRA , the data transfer from the SRAM field SRA to the write data transfer buffer DTBW, the data write from the input / output port DQ to the write data transfer buffer DTBW, the data read from the read data transfer buffer DTBR to the input / output port DQ, the data write from the data input / output port DQ to the SRAM Field SRA and to the write data transfer buffer DTBW as well as reading data from the read data transfer buffer DTBR to the data input / output terminal DQ and data transfer to the SRAM field SRA.

Fig. 84 shows a more detailed structure of the data transfer portion. In Fig. 84, those portions are shown, which to a pair of global IO lines GIO and a pair of SRAM bit lines SBL belong. Din buffer 1634 and main amplifier 1638 perform one bit input / output of data.

As shown in Fig. 84, a path for data transfer to the DRAM array includes a write data transfer circuit 1620 having a write data transfer buffer for latching and transferring data to be transferred to the DRAM array and a masking register for masking it Transfer operation and a selector 1615 for selecting either the write data from the Din buffer 1634 or the data from the first sense amplifier 1612 , which will be described later, according to the operating mode to apply the selected data to the write data transmission circuit 1620 .

The selector 1615 is activated in response to the signal ΦBW in the buffer write mode (an operation mode in which external write data is written in the write data transmission circuit 1620 ), and in response to the selection signal from the column decoder 1616 , the selector 1615 transfers the write data from the Din buffer 1634 to Write data transfer circuit 1620 .

In the data transfer process from the SRAM field to the write data transfer buffer or in the operating mode for storing data from the read data transfer buffer DTBR, which will be described later, the selector 1615 transfers the applied data to the write data transfer circuit 1620 in response to the signal ΦDW. The write data transmission circuit 1620 locks the applied data in response to the signals ΦDW and ΦBW, and transmits the applied data to the global IO line pair GIO in response to the transmission determination signal ΦDBT.

The path for transferring data from the DRAM array includes a read data transfer circuit 1610 for latching and outputting the data on the global IO line pair GIO and an SBL driver circuit 1611 receiving the data from the read data transfer circuit 1610 for transferring the data Data to the SRAM bit line pair SBL depending on the signal ΦBR. The read data transmission circuit 1610 locks the applied data and then transmits it in response to the signal ΦBR. Therefore, the signal ΦBR includes the latch determination signal and the transmission determination signal. The locking operation is carried out under the control of the DRAM control circuit while the transmission determination signal is generated under the control of the SRAM control circuit. In Fig. 84, both signals, that is, the latch determination signal and the transmission determination signal are collectively referred to as a control signal ΦDR.

The path for reading data includes a sector 1613 for selecting either the data from the read data transmission circuit 1610 or the data on the SRAM bit line pair SBL, a first sense amplifier 1612 for amplifying the data from the selector 1613 and a second sense amplifier 1614 for another Amplify the output from sense amplifier 1612 . The second sense amplifier 1614 is activated only when a selection signal is supplied from the column decoder 1616 and performs an amplification process. In the unselected state, the output of amplifier 1614 is in a high impedance state. When data is applied from the selector 1613 , the first sense amplifier 1612 always performs an amplification process.

The selector 1613 selects the data on the SRAM bit line SBL depending on the signal ΦBWT in the buffer write transfer mode (data transfer from the SRAM field to the write data transfer circuit 1624 ). The selector 1613 selects data from the read data transfer circuit 1610 depending on the signal ΦDX in the buffer read mode (for reading data stored in the read data transfer circuit 1610 (DTBR) outside the device) and in the second transfer mode (an operation mode for Transferring data stored in the read data transfer circuit 1610 to the write data transfer circuit 1620 (described later).

In the SRAM read mode for reading data on the SRAM bit line SBL, the selector 1613 selects the data on the SRAM bit line SBL depending on the signal SignalR.

The write driver circuit 1618 amplifies the data applied by the Din buffer 1634 and transfers it in dependence on the output signal from the column decoder 1616 into the SRAM bit line pair SBL. Column decoder 1616 is activated when a bit is selected from the column block (a block of 16-bit memory cells that are selected simultaneously) that represents a column block that represents the column block decoder of FIG. 70.

As shown in Fig. 84, both the write driver 1618 and the second sense amplifier 1614 are driven by the output of the column decoder 1616 . The write driver circuit 1618 is activated in the operating mode for writing data into the SRAM field, while the second sense amplifier 1614 is activated in the data read mode. The output signal of the column decoder 1616 determines whether they are actually activated in the respective operating mode. The operation of the CDRAM according to the second embodiment will now be described.

FIG. 85 shows in a table the states of external control signals for realizing processes which relate to the SRAM control circuit of the CDRAM according to the second embodiment, and the processes implemented at this time. The processes implemented are the same as those for the first embodiment. The difference is that external control clock signals CC0 # and CC1 # are used in the second embodiment, and the logic of the clock mask signal CMs # is inverted so that the SRAM power save mode and the data suspend state (continuous input / output of the same data) are next Cycle is executed when the mask signal CMs is at "L".

Another difference is that the Chip selection signal CS # and the DQ control signal DQC added have been. If the chip selection signal CS # is at "H", the Output placed in a high impedance (Hi-Z) state, and both the DRAM section and the SRAM section of the CDRAM are closed.

If the SRAM clock mask signal CMs # is at "L", the SRAM power saving mode set the transmission of the clock signal is locked and the internal state is maintained. The leads to a data suspend condition.  

If the chip selection signal CS # is at "L" and the SRAM Clock mask signal CMs # at "H", the CDRAM is in a selected state and the master clock signal turns on the SRAM control circuit is applied. In the following description it is assumed that the chip selection signal CS # and Clock mask signal CMs # are at "L" or "H".

When the control clock signals CC0 # and CC1 # are both "H", the SRAM lock mode is set and the output is set to placed in a high impedance state. Internally there is a company executed. In this case, the DQ control signal DQC can be in one any state.

[Special operating modes] [SRAM read mode]

If the control clock signal CC1 # is set to "L" and the control clock signal CC0 # and the write activation signal WE # are set to "H", the SRAM read mode is set. Data is selected in the SRAM field. At this time, when the DQ control signal DQC is set to "H", data is read out which is read from the SRAM field. Fig. 86 shows the data flow in the SRAM read mode. As shown in FIG. 86, in the SRAM read mode, a row is selected in the SRAM array 104 , the data of the memory cells connected to this row are amplified by the first sense amplifier 1512 and then transmitted to the second sense amplifier 1514 . Column decoder 1516 selects one of the 16 bits (if there are 4 IOs) and activates the corresponding second sense amplifier 1514 . The selected 4 bits (if the IO section has a 4-bit structure; the same applies to the following description) are amplified by the second sense amplifier 1514 and transmitted to the main amplifier circuit 1438 . When the DQ control signal DQC is "H", the main amplifier circuit 1438 is activated and the read data is transferred to the input / output terminal DQ ( Fig. 86 shows a state in which the common DQ arrangement is selected as the data input / output structure; the same applies to the following description). When the DQ control signal DQC is at the "L" level in this state, the main amplifier circuit 1438 does not operate and the operation is similar to the SRAM disable mode.

[SRAM write mode]

When the control clock signal CC0 # is set to "H", and that Control clock signal CC1 # and the write activation signal WE # are set to "L", the SRAM write mode is set. If the DQ control signal DQC is at "H", they become this External data created at the time and it will be internal write data generated. The internal generated Write data is corresponding to the RAM address bits As0 to As11 that are being fed at that time into the selected memory cells.

As shown in Fig. 87, the data supplied to the DQ output terminal in the SRAM write mode is applied to the write driver circuit 1518 via the Din buffer 1434 . The write driver circuit 1518 writes the applied data depending on the column selection signal from the column decoder 1516 into the corresponding memory cell of the SRAM field 104 .

[Buffer Read Transfer Mode]

If both the control clock signal CC0 # and the DQ- Control signal DQC are set to "L", and that Control clock signal CC1 # and the write activation signal WE # are set to "H", the buffer read transfer mode fixed. The DQ control signal DQC is set to "L" to to realize an initial state of high impedance and a to avoid erroneous output of the data by the Read transfer buffer circuit are transferred.

For the data, the data in the read data transfer buffer (DTBR) locked data are simultaneously transmitted to the SRAM field. In this case, the SRAM address bits As4 to As11 are  Row address is used and it becomes a row selection process executed.

As shown in Fig. 88, in the buffer read transfer mode, 16 bits of data of the read data transfer buffer circuit (DTBR) are simultaneously transferred to the selected row of the SRAM array 104 . In Fig. 85, "used" means that the data locked therein is used. The indication "load / use" means that the data is locked and used.

[Buffer Write Transfer Mode]

The control clock signal CC1 # is set to "H", and will the control clock signal CC0 #, the write activation signal WE # and the DQ control signal DQC is set to "L", the Buffer write transfer mode set. In this case Data from the SRAM field to the read data transfer buffer circuit transfer. As will be described in detail later, the Write data transfer buffer circuit and the Masking register circuit both an intermediate latch and have a two-stage latch circuit structure. in the Buffer write transfer mode is data from the SRAM field in the Intermediate latch that is in the write data transfer buffer circuit is formed, saved. In the same way, in the Masking register circuit the masking data of the Intermediate mask registers all reset. The SRAM Address bits As4 to As11 are adopted as SRAM row addresses, a row selection process is carried out in the SRAM field and the Data of the memory cells of the selected row become Transfer write data transfer buffer circuit.

As shown in Fig. 89, in the buffer write transfer mode, the data of the memory cells connected to the selected row of the SRAM array 104 are amplified by the first sense amplifier 1512 and then stored in the write data transfer buffer circuit 1520 (more specifically, therein formed intermediate register).

[Buffer Read Transfer and Read Mode]

When the control clock signal CC0 # is set to "L" and the control clock signal CC1 #, the write enable signal WE # and the DQ control signal DQC are set to "H", the buffer read transfer and read modes are set. In this case, the data stored in the read data transfer buffer is transferred to the SRAM field and data is transferred externally. In this case, all SRAM address bits As0 to As11 are used. As is apparent from Fig. 85, the buffer read transfer mode to the read mode and Pufferlesetransfer- coincides, except that the state of the control signal DQ DQC differs. At this time, not only the input / output circuit, but also the activation / deactivation of the column decoder can be controlled by the DQ control signal DQC.

As shown in Fig. 90, in the buffer read transfer and read mode, 16 bits of data are transferred from the read data transfer buffer circuit 1510 to the selected row of the SRAM array 104 , and it becomes a data bit (more specifically, 4 bits because there are 4 IOs). which have been selected by the column decoder 1516 are transmitted to the data input / output terminal DQ via the first and second sense amplifiers 1512 and 1514 .

[Buffer Write Transfer and Write Mode]

When the control clock signal CC0 # and the write enable signal WE # are set to "L" and the control clock signal CC1 # as well the DQ control signal DQC is set to "H", the Buffer write transfer and write mode set. In this Mode are externally created write data in a corresponding Memory cell of the SRAM field written and the written ones Data is also written to the corresponding register, the is formed in the write data transfer buffer circuit. Also in this case the write data Transfer buffer circuit the data of a line with which the  Memory cells are connected that write this data subject to transfer to the intermediate register. To this At that time, the masking data of the masking register all reset.

More specifically, as shown in Fig. 91, the data applied to the data input terminal DQ is supplied to the Din buffer 1434 , the write driver circuit 1518 is activated in accordance with a column selection signal from the column decoder 1516 and writes the data to a corresponding memory cell of the SRAM Field.

The data of a row of memory cells of the selected row, which contains the memory cell which has been subjected to data writing, are transmitted to the write data transfer buffer circuit 1520 via the first sense amplifier 1512 . Fig. 91 shows the write data as it was written to the corresponding memory cell of the SRAM array via the write driver circuit 1518 , and then the data of one row of memory cells is transferred to the write data transfer buffer circuit 1520 via the first sense amplifier 1512 . In parallel to the data writing into the memory cell of the SRAM array 104 through write driver circuit 1518, however, the data of the memory cell may be transmitted 1520 to the write data transfer buffer circuit 1520, the selected row in the SRAM array 104 through the first sense amplifier, and in this write data transfer buffer circuit 1520 may data writing to the corresponding register is performed at the same time as the write driver circuit 1518 .

In this structure, column decoder 1516 is shown to drive only write driver circuit 1518 and second sense amplifier 1514 . The column decoder 1516 , however, has a function of selecting registers formed in the latch data transfer buffer circuit 1520 .

In buffer write transfer and write mode, the Buffer write transfer operation only performed if the DQ Control signal DQC is set to "L".  

[Buffer Read Mode]

When the control clock signals CC0 # and CC1 # are both at "L" and that Control activation signal WE # and the DQ control signal DQC "H" are set, the buffer read mode is set. in the Buffer read mode, data in the read data Transfer buffer circuit according to the SRAM address bits (Block address) As0 to As3 selected, and the selected ones Data are output. If in this case the DQ control signal DQC is set to "L", no data reading is carried out, and the SRAM lock mode is set.

In the buffer read mode, data from the read data transfer buffer circuit 1510 is amplified by the first sense amplifier 1512 , and then a corresponding second sense amplifier is activated only in accordance with the column selection signal from the column decoder 1516 , the output signal of the activated second sense amplifier is transmitted to the main amplifier circuit 1438 , and then read data is transmitted from the Main amplifier circuit 1438 is transferred to the data input / output terminal DQ as shown in FIG. 92.

[Buffer write mode]

If the control clock signals CC0 # and CC1 # as well as that Write enable signal WE # are set to "L", and that DQ control signal DQC is set to "H", the Buffer write mode set. In this case corresponding registers of the write data transfer buffer circuit selected according to the block address bits As0 to As3, and a external value is written to the selected register. In in this case, in the write data transfer buffer circuit only those masking data reset that the register correspond, which is subject to data writing.

More specifically, as shown in Fig. 93, the buffer write mode is selected by a column selection signal from the column decoder 1516 (whose path is not shown) in the write data transfer buffer circuit 1520 , and a write value from the Din buffer 1434 is selected in the selected register written.

In the table of Fig. 85, the control signals associated with the operation of the DRAM array and the state of the DRAM address are not shown. The SRAM field and the DRAM field are driven independently of one another. Therefore, the states of the control signals relating to the operation of the DRAM and the state of the SRAM addresses are arbitrarily specified in the table according to FIG. 85.

Fig. 94 is a table showing the operating modes of the DRAM array, the states of the control signals and the states of the data transmission buffer at that time. As shown in Fig. 94, the operation of the DRAM array section does not affect the operation of the SRAM section and data input / output. Therefore, the states of the control signals CC0 #, CC1 #, WE # and DQC belonging to the SRAM can be in any state. The states of these control signals are therefore not shown.

[DRAM power saving mode]

Is the DRAM clock mask signal CMd # in the previous cycle at "L", the DRAM array enters the DRAM power save mode, and maintains the state that was set in the previous cycle. The chip selection signal CS # is used for the SRAM section and prevent the DRAM section from creating a new one Operating state.

In the first embodiment, the chip activation signal E # is only supplied to the SRAM control section and is not used in the DRAM section. In the second embodiment, the chip select signal CS # is also applied to the DRAM control section. When the chip select signal CS # is set to the inactive state "H", the DRAM enters the NOP mode (no operation) in which no operation is carried out. Therefore, in the structure shown in Fig. 71, the internal chip select signal CS supplied to the input ENA of the control circuit 1452 resets the control circuit 1452 and is used to control the active / inactive state.

A structure can be used in which the chip selection signal CS # is supplied to the K buffer 1424 (see FIG. 74), and if the chip selection signal CS # is "H", the master clock signal K cannot be applied to the DRAM- Control circuit 128 and the SRAM control circuit 1432 are applied. If the chip selection signal CS is "H", the acceptance of a new control signal is blocked in the control circuit.

[DRAM NOP mode]

If the chip selection signal CS # is at "L" (in the following Description assumes that this condition is met) and the clock mask signal CMd # is on in the previous cycle "H" (this condition also applies to the following description) and are both the row address strobe signal RAS # and that Column address strobe signal CAS # at "H", the NOP mode of the DRAM (DNOP mode) set. In this case, the DRAM field the state of the previous cycle is maintained and there is no new operation executed. This mode is used to control the DRAM section to prevent a new operating mode to take. Is a specific one in the previous cycle Operating mode has been set and is the DRAM-NOP mode is set in this state internally that in the previous one Cycle specified operation executed.

[DRAM Read Transfer Mode]

When the row address strobe signal RAS # and the data transfer determination signal DTB # are both set to "H" and the column address strobe signal CAS # is set to "L", the DRAM read transfer mode is set. In the DRAM read transfer mode, the address bits Ad4 to Ad9 in the DRAM field are used as the column block address, and a memory cell block (column block) is selected by the block decoder 112 , which is shown in Fig. 70. The data of the selected column block (memory cell block) is transferred to the read data transfer buffer circuit.

More specifically, as shown in Fig. 95, the selected column block (a memory cell block or a data block) is selected in the DRAM array 102 and the selected column block is transferred to the read data transfer buffer circuit 1510 and latched there.

[DRAM active mode]

When the row address strobe signal RAS # is set to "L", and both the column address strobe signal CAS # and that Data transfer determination signal DTD # are set to "H", the DRAM active mode is set. In this mode the at this time address bits Ad0 to Ad11 as DRAM Row address is taken over, and in the DRAM field the Row address performed a row selection. The DRAM Active mode maintains the row selection state until the DRAM Pre-charge mode is set, which is described below. By using the DRAM active mode, the sense amplifier of the DRAM can be put into the data lock state by a data transmission using the page mode can be implemented (as in the first embodiment).

[DRAM preload mode]

If the row address strobe signal RAS # and that Data transfer determination signal DTD # both at "L" are set, and the column address strobe signal CAS # is at "H" the DRAM precharge mode is set. In this Mode is a word line selected in the DRAM field in the unselected state changes, and the DRAM returns to Initial state back (standby state). If in the DRAM field another line should be selected, it is necessary between the DRAM active mode and the following DRAM active mode to execute the DRAM precharge mode.  

[Self-refresh mode]

When the address strobe signals RAS # and CAS # are both set to "L" and the data transfer designation signal DTD # is set to "H", the self-refresh mode is set in the DRAM section. In this mode, a refresh address is generated from an address counter (not explicitly shown in Fig. 70) formed in the DRAM, and the memory cell data is refreshed according to the refresh address. As with the first embodiment, execution of the DRAM precharge mode is necessary to complete the self-refresh mode. The DRAM address created at this time can be used as a refresh address.

[Data transfer operation from the write data transfer buffer circuit to the DRAM array]

There are four different types of data transfers from the write data transfer buffer circuit to the DRAM array. Data transfer from the write data transfer buffer circuit to the DRAM array is determined by setting the row address strobe signal RAS # to "H" and by setting the column address strobe signal CAS # and its data transfer designation signal DTD # to "L". In this state, the address bits Ad4 to Ad9 supplied at this time are applied to the block decoder 112 (see Fig. 70), and data transfer is performed on the column block (memory cell block or data block) selected in the DRAM field. There are four different data transfer modes. These four data transfer modes are described below.

Fig. 96 shows the states of the control signals in the DRAM write transfer mode (which summarizes the four data transfer modes). In the first cycle of the master clock signal K, the row address scanning signal RAS # is set to "L" with the rising edge and the DRAM active mode is defined. The address bits Ad0 to Ad11 supplied at this time are adopted as the DRAM row address, and a row selection process is carried out in the DRAM field. After a predetermined latency (number of clock cycles necessary to allow the column address strobe signal CAS # to drop) has elapsed, in the fourth cycle of the master clock signal K the column address strobe signal CAS # and the data transfer determination signal DTD # are both set to "L". As a result, the DRAM write transfer mode (DWT mode) is set. In write transfer mode, an operation for selecting a column block (a block of memory cells or a data block) is performed in the DRAM field. Ad4 to Ad11 are used as addresses. The remaining low-order address bits Ad0 to Ad3 are used as commands for specifying the type of write transfer mode.

In the table of FIG. 94 shows a state, only the low address bits Ad0 to be used in the Ad1. The remaining address bits Ad2 and Ad3 are reserved for future expansion. In a structure in which a command value for setting the DRAM write transfer mode is applied simultaneously with the DRAM column block address when the column address strobe signal CAS # falls, it is unnecessary to form a separate terminal for data transfer setting. This can reduce the chip area.

The external control devices can also perform data on simple Generate ways for write transfer mode setting are necessary so that the control of the overall system is simplified. That will be before the detailed description of the write transfer mode explained.

Fig. 79 shows an example of a data processing system that uses a CDRAM. As shown in Fig. 79, the data processing system includes a CPU 2002 as an external processing unit for performing the necessary data processing, a CDRAM 2000 , which acts as main memory and cache memory, a cache controller 2004 , which controls the mode of operation and other things of the CDRAM 2000 specifies an SRAM address latch 2006 , which locks the SRAM address A0 to A11 from the CPU 2002 , a row latch 2008 , which locks the address A10 to A21 from the CPU 2002 as a DRAM row address, a column Latch 2010 for locking the addresses A4 to A9 from the CPU 2002 as a DRAM column block address and a multiplexer 2014 for multiplexing the addresses from the row latch 2008 and column latch 2010 to apply the result to the CDRAM 2000 . The multiplexer 2014 simultaneously applies the address from the column latch 2010 and the command data from the command latch 2012 to the CDRAM.

The cache controller 2004 has a circuit section for detecting a cache miss in accordance with the cache address A0 to A11 by the CPU 2002 for generating a control signal according to the determination result. The SRAM address bits As0 to As11 of the CDRAM 2000 are generated by the Latch 2006 . The DRAM address bits Ad0 to Ad11 of the CDRAM 2000 are generated by the multiplexer 2014 .

In the address structure shown in Fig. 97, the address bits A12 to A21 created by the CPU 2002 are used as the tag address of the cache. The CPU address bits A10 and A11 are used as the way address. The CPU address bits A4 to A9 are used as the set address. The CPU address bits A0 to A3 are used as block addresses. The CPU address bits A22 to A31 (in the case that the address includes 32) are used as the chip select address. Namely, the address arrangement shown in Fig. 97 shows a structure in which a 4-way set associative mapping between cache and main memory is implemented.

The cache controller 2004 decodes a chip selection address, not shown, and generates a chip selection signal (or a chip activation signal (in the case of the first embodiment)).

In the structure shown in Fig. 97, the multiplexer 2014 can generate the DRAM column address and the command data for the write data transfer mode at the same time. Therefore, the type of write transfer mode can be set without affecting the working speed. Furthermore, this control method is easily used as a method for generating the command data for identifying the type of the write transfer mode.

Now the operation of the respective write transfer modes described.

[DRAM Write Transfer Mode 1]

This mode is determined by setting the address bits Ad0 and Ad1 to "0", which coincides with the DRAM column address be fed. In this mode, data from the Intermediate register in the write data transfer buffer DTBW loaded, and the loaded data becomes the DRAM field transfer. Synchronous with data transfer from the intermediate register the write data transfer buffer circuit to the data transfer buffer DTBW become masking data of the intermediate register Masking register in the transmission masking circuit transferred and this data transfer is masked. In this The masking data of the intermediate register after the mode Completion of data transfer set.

Here, the intermediate register 142 of the write data transfer buffer circuit and the write data transfer buffer DTBW are shown in Fig. 70 by reference numerals 142 and 144 , respectively. The intermediate register is not shown for the masking register circuit. The detailed structure will be described later. In this description, the structure is simplified for easier understanding of the data transmission process.

As shown in FIG. 98, in the DRAM write transfer mode 1, data is transferred from the write data transfer buffer (DTBW) 1520 to the DRAM array 102 . In the DRAM field 102 , a column block (a memory cell block or a data block) has been selected and the data is written to the selected column block at once.

[DRAM Write Transfer Read Mode]

This mode is set by setting the address bits Ad0 and Ad1 to "1" and "0", respectively. In this mode, data from the write transfer buffer circuit (DTBW) is transferred both to the selected column block of the DRAM array and to the read data transfer buffer circuit. The data from the column block containing the memory cell that has been subjected to data writing is transferred to the read data transfer buffer circuit (DTBR). Thus, in a cache miss write from this read data transfer buffer circuit, reading data can be performed if the same block is set in the next cycle and because the data can be written from the read data transfer buffer circuit (DTBR) to the SRAM array 104 , the contents of the SRAM field 104 that was accessed unsuccessfully can be rewritten. Therefore, the cache miss delay can be reduced and a CDRAM that operates at high speed can be formed.

More specifically, as shown in Fig. 99, in the DRAM write transfer mode 1 / read mode, data is transferred from the write data transfer buffer circuit (DTBW) 1520 to the selected column block of the DRAM array 102 (a masking operation corresponding to the masking data in the masking register is performed) and that Data from this selected column block of DRAM array 102 is transferred to read data transfer buffer circuit (DTBR) 1510 .

[DRAM write transfer mode 2)

This mode is determined by setting the column block Address bits Ad0 and Ad1 at "0" and "1", respectively. In this operating mode a data transfer from the write data Transfer buffer circuit (DTBW) to the selected column block of the DRAM field executed. In this case, the Write transfer buffer circuit no data transfer from Intermediate register to the write data transfer buffer (DTBW) carried out. The same applies to the masking register.  

The write data transfer buffer circuit separates the intermediate register from the buffer register section which transfers the data to the DRAM array. When the DRAM write transfer mode 2 is repeatedly executed, the same data is transferred to the DRAM field. If the column block in the DRAM field is selected in page mode, the data in the DRAM field can be overwritten by the same value at high speed. Therefore, so-called "fill" (coloring in one color) can be implemented at high speed in a graphics application. The data transfer process is essentially the same as that shown in FIG. 98. The only difference is whether the same value is transferred or not.

[DRAM write transfer mode 2 / read mode]

This mode is determined by setting the address bits Ad0 and Ad1 to "1". In this operating mode, in addition to DRAM write transfer mode 2 an operation for transferring data the selected column block of the DRAM field for read data Transfer buffer circuit (DTBR) performed. Also in this Operating mode can be a "filling" at high speed will be realized. Accordingly, one can obtain a CDRAM that is very effective for graphics applications.

[General data transfer process]

Fig. 100 shows a signal diagram of a data transmission sequence from the DRAM array to the read data transfer buffer circuit. Data transfer from the DRAM array to the read data transfer buffer circuit will be described with reference to FIG. 100.

In the first cycle of the master clock signal K when the row address Sampling signal RAS # is set to "L", and the column address Sampling signal CAS # and the data transmission determination signal DTD # are set to "H", the DRAM active mode ACT fixed. In the DRAM section at that time  created address bits Ad0 to Ad11 are used as row addresses, and a row selection process is performed.

In the cycle after the RAS-CAS delay tRCD has elapsed, that is, in the fourth cycle of the master clock signal K if that Column address strobe signal CAS # is set to "L", and that Row address scan signal RAS # and the data transmission Determination signal DTD # are set to "H", the DRAM Read transfer mode (DRT) set. In the DRAM field is a Column block (a memory cell block or a data block) of the selected row using the as column block address (C1) selected address selected, and the data of the selected column blocks are used for read data Transfer buffer circuit. Here is a latency of assumed three clock signal cycles.

The latency means the number of clock signals that are necessary are that the new data from the read data Transfer buffer circuit to the SRAM field and / or the Data input / output port DQ are transmitted as before described in connection with the first embodiment has been. This latency can be seen as the access time of the read data Transfer buffer circuit can be viewed. Is the latency n Clock cycles, the (n-1) th cycle is in the "DTBR lock state" transferred. More specifically, the data transmission is carried out by the Read data transfer buffer circuit locked (in this cycle the process of accessing the read data Transfer buffer circuit blocked).

In the seventh cycle of the master clock signal K, the data of the Read data transfer buffer circuit stabilized, and in this The DRAM read transfer mode in the DRAM section becomes cycle again fixed. In the line that is in the first cycle of the Master clock signal K has been set, another Column block corresponding to the column block address (C2) selected, and after the CAS latency has elapsed, the Data of the newly selected column block (a Memory cell block or data block) for read data Transfer buffer circuit.  

In the SRAM section, in the seventh cycle of the master Clock signal R the control clock signals CC0 # and CC1 # both at "L" is set, and the write enable signal WE # is set to "H" set. The DQ control signal DQC is at "H" and Data input / output is activated. In this state it is Buffer read mode is set and the column decoder performs the Selection process in accordance with the address bits As0 to As3 from that point in time and it reads the corresponding data from the values that are in the read data Transfer buffer circuit are stored. To be more precise read data B1 in the eighth cycle of master clock signal K. By executing the DRAM read transfer mode and by executing the buffer read mode (BR) in one cycle after the elapse the latency can namely read data after the lapse of Time tCAC obtained from the determination of the buffer read transfer mode become.

In the tenth cycle of the master clock signal K through the Column block address (C2) selected data of the read data Transfer buffer circuit saved. In this cycle buffer read mode (BR) executed again, and in each Clock cycle become those in the read data transfer buffer circuit stored data read one after the other (B2, B3, B4 and B5).

Parallel to the buffer read mode process, the twelfth cycle of the Master clock signal of the DRAM read transfer mode redefined, and after three clock signal cycles have passed, those are Data of the read data transfer buffer circuit stabilized. in the SRAM field section becomes access in this fourteenth cycle locked to the read data transfer buffer circuit, and therefore the SRAM address created at this time is ignored (because that is the DTBR lockout time).

In the fifteenth cycle of the master clock signal K, the Buffer read mode set, and those in the read data Transfer buffer circuit (B6) stored data are read.  

In the fifteenth cycle of the master clock signal K, this will be Row address strobe signal RAS # and the data transmission Determination signal DTD # set to "L", and that Column address strobe signal CAS # is set to "H". So that will the DRAM preload mode (PCG) is set. So the line which has been selected in the DRAM field, in the not selected state.

As has been described above, the combined Using DRAM read transfer mode and buffer read mode the data of the DRAM field via the read data Transfer buffer circuit can be read without the SRAM field too influence. Because this is done by using Page mode of the DRAM can be executed (the DRAM active mode continue until a DRAM precharge mode is executed) the data is read at high speed.

Fig. 101 shows a signal diagram of the data transfer sequence from the write data transfer buffer circuit to the DRAM array. Referring to Fig. 101, the DRAM write transfer mode for transferring data from the write data transfer buffer circuit to the DRAM array will be described.

In the first cycle of the master clock signal K, the row address Sampling signal RAS # is set to "L", and the column address Sampling signal CAS # and the data transmission determination signal DTD # are both set to "H", making the DRAM active mode (ACT) is set. In the DRAM field is a Row selection process performed.

In the SRAM section, the first to fourth cycle of the master Clock signal K a buffer write (BW) executed, and in second to fourth cycle of the master clock signal K are the Data B1 to B4 are stored in succession in the intermediate register, which is formed in the write data transfer buffer circuit. The buffer write mode (DBW) is defined by Setting the clock signals CC0 # and CC1 # and the Write activation signal WE # to "L" and by setting the DQ Control signal DQC executed at "H".  

In the fourth cycle of the master clock signal K is by setting the row address strobe signal RAS # to "H" and by setting of the column address scanning signal CAS # and of the data transmission Determination signal DTD # at "L" of the DRAM write transfer mode 1 (DWT1) set. When the DRAM write transfer mode 1 is set, the ones saved in the intermediate register are saved Data (B1 to B4) to the write data transfer buffer (DTBW) transfer. The transferred to the write transfer buffer (DTBW) Data is stored in the column block (a memory cell block or Data block) after the latency has passed (three clock cycles) saved in the DRAM field.

When the latency has passed, that is, in the seventh cycle of the master clock signal K become the column address strobe signal CAS # and the data transfer determination signal DTD # again "L" and the row address strobe signal RAS # are set to "H". In this mode, setting the SRAM address bits As0 to As3, which are created at this time, as command data of the DRAM write transfer mode 2 (DWT2) set. If the DRAM Write transfer mode 2 is set, it will Intermediate register from the write data transfer buffer (DTBW) disconnected, and there is no data transfer from Intermediate register to the write data transfer buffer (DTBW) carried out. The in the write data transfer buffer (DTBW) stored data will become after the latency has passed selected column block of the DRAM field.

As shown in Fig. 101, in the DRAM write transfer mode, the mode setting is made in accordance with the DRAM address bits Ad0 to Ad3 at the time of the DRAM write transfer mode setting. Therefore, the DRAM write transfer mode can be set without affecting the operation in the SRAM section.

In the tenth cycle of the master clock signal K, the Buffer write mode (BW) set, and in the tenth to twelfth Cycle of the master clock signal K, data B5, B7 in Write data register (intermediate register) stored.  

In the twelfth cycle of the master clock signal, the DRAM Write transfer mode set, and that in the intermediate register stored data B5 to B7 become the write data Transfer buffer transferred. After the passage of one predetermined latency, the new data B5 to B7 in selected column block of the DRAM. In the thirteenth Cycle of the master clock signal K is in the SRAM section Buffer write mode (BW) has been set. Because in this cycle however, data stored in the intermediate register for Write data transfer buffer are transferred, the access locked on the intermediate register. Therefore, the thirteenth Cycle of the master clock signal K set buffer write mode not executed.

In the fifteenth cycle of the master clock signal K, the DRAM Precharge mode (PCC) is set and the DRAM field returns to Precharge status back.

More specifically, in DRAM write transfer mode Data transmission of the DRAM field in the manner of a pipeline or run independently of the operation of the SRAM section, because an intermediate register and a write data transfer buffer are formed. In write transfer mode 1 is in the first cycle the intermediate register with the write data transfer buffer connected. The intermediate register and the write data Transfer buffers start at the beginning of the next cycle separated from each other. At the time of this separation, the Masking data in the masking register circuits that the Intermediate registers correspond, all set.

After the separation of the intermediate register and the write data Transfer buffers can transfer data from the SRAM field or from the outside into the Intermediate registers are written.

In DRAM write transfer mode 2, the intermediate register and the write data transfer buffer is kept separate. Therefore, no data transfer from the intermediate register to Write data transfer buffer executed and that in the previous  Cycle data stored in the write data transfer buffer transferred to the selected column of the DRAM field.

In DRAM write transfer mode is in addition to data transfer to the DRAM field a transmission mode for read data Transfer buffer circuit formed. This is useful if it is as Cache memory is used.

[Control system for the write transfer process]

Fig. 102 shows a structure for controlling the DRAM write transfer operation. As shown in Fig. 102, the write transfer control system includes a write transfer detection circuit 2110 which is comprised of an internal DRAM master clock signal DK, an internal row address strobe signal RAS, an internal column address strobe signal CAS and an internal data transfer designation signal DTD is dependent, for detecting the determination of the DRAM write transfer mode, an instruction register 2112 which stores the two least significant bits Ad0 and Ad1 of the DRAM column address currently being applied when the DRAM write transfer mode is set in accordance with the signals DK, RAS, CAS and DTD and a read transfer detection circuit 2114 , which is dependent on the signals DK, RAS, CAS and DTD, for detecting the determination of the data transfer from the DRAM field to the read data transfer buffer circuit 2106 . Write transfer detection circuit 2110 , command register 2112 and read transfer determination circuit 2114 are included in DRAM control circuit 128 shown in FIG. 70. Instruction register 2110 is shown to receive only the low order address bits Ad0 and Ad1. Address bits Ad0 to Ad3 can also be used (to expand the functionality).

When the DRAM write transfer mode is set, the read transfer detection circuit 2110 generates a signal ΦBW to set the data transfer from the write data transfer buffer (DTBW) 2100 to the DRAM field (which indicates the global IO line pair GIO in Fig. 102) and a transfer signal ΦTBE to perform data transfer from the intermediate register 2104 to the write data transfer buffer (DTBW) 2100 when the DRAM write transfer mode is set.

The control system also includes a gate circuit 2116 which receives the ΦTBE signal from the write transfer detection circuit 2110 and the address bit Ad1 from the command register 2112 and generates a transfer designation signal when the DRAM write transfer mode 1 is set (by performing data transfer from the latch to the write data transfer buffer a gate circuit 2118 , which receives the address bit Ad0 from the command register 2112 and the signal ΦTBE, for generating the mode detection signal when the write transfer mode is set with the data transfer to the read data transfer buffer (DTBR) 2106 , a gate circuit 2120 which is selected by the read transfer mode Determination signal ΦDRM is dependent on the read transfer detection circuit 2114 and on the output signal from the gate circuit 2118 , for generating a signal for specifying the data transfer from the DRAM field to the read data transfer buffer, and a read transfer driver circuit 2112 , which from Output signal is dependent on the gate circuit 2120 to generate a driver signal ΦDR to drive the data transfer to the read data transfer buffer (DTBR) 206 . When the output signal of gate circuit 2118 or read transfer mode detection signal ΦDRM is activated, read transfer driver circuit 2112 generates signal ΦDR to drive data transfer to read data transfer buffer (DTBR) 2106 .

A transfer gate 2102 is formed between the write data transfer buffer (DTBW) 2100 and the intermediate register 2104 . The transfer gate 2102 transfers the output signal from the intermediate register 2104 to the write data transfer buffer (DTBW) 2100 depending on the output signal of the gate circuit 2116 .

By using the structure described above, the type of DRAM write transfer mode can be detected, and the  Data transfer process can be done exactly in accordance with the detected operating mode can be performed.

Operation of the DRAM write transfer mode 2 will now take place described (with a mode in which a data transmission for Read data transfer buffer circuit is executed).

[DRAM write transfer mode 2)

As shown in Fig. 103, it is assumed that data corresponding to the buffer write mode (BW) is written in the write data transfer buffer circuit, then the write transfer mode 1 (DWT1) is executed, and then the DRAM write transfer mode 2 (DWT2) is repeated several times . The type of DRAM write transfer mode is determined by setting the value of the two least significant bits A0 and A1 (corresponding to Ad0 and Ad1) of the DRAM address Ad in the respective mode.

Fig. 104A shows the data flow in DWT1 mode. As shown in Fig. 104A, in DRAM write transfer mode 1, 16 bits of data D1 to D16 stored in the intermediate register are transferred to the write data transfer buffer circuit (DTBW). At the same time, the masking data of the intermediate masking register are stored in the masking register because the masking register has a similar hierarchical structure to the intermediate register. The data D1 to D16 stored in the write data transfer buffer circuit (DTBW) are masked according to the masking data M1 to M16 stored in the masking register and transferred to the column block (hatched area A) selected in the DRAM field . The masking data of the intermediate masking register are all set after the transfer of the masking data to the masking register to reset the corresponding masking data when data is subsequently written to the intermediate register in the buffer write mode (BW).

Fig. 104B shows the data flow in the DRAM write transfer mode 2. In the DRAM write transfer mode 2, no data transfer from the intermediate register to the write data transfer buffer circuit (DTBW) is carried out, as shown in Fig. 104B. Therefore, the data stored in the write data transfer buffer circuit (DTBW) is the data that was transferred from the intermediate register in the previous cycle. The masking data is also not transmitted in the masking register from the intermediate masking register. Therefore, the same data as in the previous cycle is transferred to another column block of the selected row in the DRAM field. The same data is written column-by-column in the DRAM field.

By repeatedly executing the process shown in FIG. 104B, a predetermined area B of the CRT screen of the display unit can be changed by the same data as shown in FIG. 105. This enables the so-called "filling process" to be carried out at high speed in a graphics application. The structure of the masking register will be described later in detail.

In DRAM write transfer mode, data transfer to the DRAM Field through the masking data of the masking register be masked. If the data of the DRAM field by external It is therefore not necessary to overwrite write data necessary to use the read-write mode (read-modify-write Mode), and therefore the content of the DRAM field be changed at high speed.

Once manufactured, the CDRAM is tested as a single chip or part of a circuit to determine if it is working properly. More specifically, as shown in FIG. 106, a test pattern with various patterns is applied from a tester 2510 to the CDRAM 2500 . It is necessary to determine whether the CDRAM 2500 is operating normally by determining the operating states of the CDRAM 2500 in accordance with the test pattern. In this case, the test of the CDRAM should preferably be carried out simply in view of the test reliability and the time required for the test. A structure for simplifying the test is described below.

[Command register setting mode]

The command register setting mode (SCR cycle) is through Setting the row address strobe signal RAS #, the column address Sampling signal CAS # and the data transfer determination signal DTD # with the rising edge of the master clock signal K. "L" set. At this time, the DRAM address is as Command value used. The command data are in the Command registers saved, and the setting of latency and the output modes (transparent, register and latch) as well as the CDRAM connector arrangement (IO structure) is executed. The command data from the tester should preferably be on can be generated easily.

Fig. 108 shows a structure for the command register in the command register setting cycle. Under the DRAM address Ad, the low-order nine bits Ad0 to Ad8 are regarded as the content of the command and stored in the command register. The address bit Ad9 is used as a bit which indicates the activation / deactivation of the data transfer to the read data transfer buffer circuit in the DRAM write transfer mode.

The address bit Ad10 is used to indicate whether the DRAM Write transfer mode includes a DWT1 mode or DWT2 mode. The address bit Ad11 is used to set / reset the test mode used. If the test mode is set, the DRAM Write transfer mode set the command data Ad0 to Ad3, however, this command data is ignored at this time.

With this structure, the tester can only view the command data generate using the DRAM address bits Ad0 to Ad11 become. It is not necessary to use the DRAM Column block address and the command data that specify the type of DRAM Specify write transfer mode to create. Therefore, the Tester structure can be simplified, the setting of  Command data can be carried out easily and the test can be carried out with high reliability.

Fig. 109 shows the correspondence between the command data and the DRAM write transfer mode in the test mode. As shown in Fig. 109, the test mode is set when the address bit Ad11 is "1"("H") in the command register setting mode. The test mode is reset when it is "0". When the test mode is set and the address bits Ad10 and Ad9 are both "0", the DWT1 mode is set. When the address bits Ad10 and Ad9 are "0" and "1", respectively, the DWT1R mode is set. If the address bits Ad10 and Ad9 are "1" and "0", respectively, the DWT2 mode is set. If the address bits Ad10 and Ad9 are both "1", the DWT2R mode is set.

In test mode, the test mode state is maintained until the Self-refresh mode is running or according to that Command register setting mode a test mode reset is carried out. In the test mode state, a Self-refresh of the DRAM field carried out. Alternatively, you can even just the setting of the command register in Command register setting cycle can be performed.

Fig. 110 shows an example of the circuit structure for determining the DRAM write transfer mode in accordance with the setting / resetting the test mode. As shown in Fig. 110, the test mode control system has an S 99999 00070 552 001000280000000200012000285919988800040 0002004337740 00004 99880CR mode detector 2600 which receives the internal control signals RAS, CAS, DTD and the DRAM master clock signal DK to determine whether the Command register setting mode (SCR) is set or not, a command register 2602 depending on the detection of the SCR mode by the SCR mode detection circuit 2600 for latching the DRAM address Ad0 to Ad11 as a command value, and a test mode detection circuit 2604 which receives the data corresponding to the address Ad11 from the command register 2602 to determine whether the test mode has been set or not.

The SCR mode detection circuit 2600 determines that the SCR mode is set when the signals RAS, CAS and DTD are all at the "L" level with the rising edge of the master clock signal DK. In response to the SCR mode detection by the SCR mode detection circuit 2600 , the instruction register 2602 latches the DRAM address bits Ad0 through Ad11 that are being supplied at that time. In Fig. 110, the command register 2602 is shown as a simple latch circuit. The DWT mode detection circuit 2110 and the command register 2112 are the same as those shown in Fig. 101 and they are the circuit for detecting the type of the DRAM write transfer mode. The command register 2112 latches depending on the detection of the DWT mode through the DWT mode detection circuit 2110 the command value indicating the type of the DRAM write transfer mode.

The test mode control system further comprises a selection gate circuit 2606 which is dependent on the output signal from the test mode detection circuit 2604 for passing either the address bits Ad9 and AD10 from the command register 2602, or the address bits Ad0 and Ad1 from the command register 2112 (herein provide the internal signals, which have the same reference numerals as addresses which represent command data). When the test mode detection circuit 2604 detects the test mode, the transmission gates 2611 and 2613 are turned on in the selection gate circuit 2606 and the transmission gates 2615 and 2617 are disabled. Therefore, the address bits Ad10 and Ad9 are transmitted to the gate circuits 2116 and 2118 shown in Fig. 102. When the test mode is reset, the output of the test mode detection circuit 2604 becomes "L", the transmission gates 2611 and 2613 are inhibited , and the transmission gates 2615 and 2617 are turned on.

When the test mode operation is set by the SCR mode, the test mode is maintained until the self-refresh mode (ARF mode) is set, or the test mode reset (setting the Ad11 bit to "0") is carried out by using the SCR mode again. Therefore, in the test mode operation, the output of the test mode detection circuit 2604 is kept "H", the command value from the command data register 2112 is ignored when the DRAM write transfer mode is set, and the address bits Ad10 and Ad9 set when the SCR mode is set are called the type identification bits of the Transfer DRAM write transfer mode.

In the structure shown in Fig. 110, external address bits Ad0 to Ad11 are supplied to the instruction registers 2602 and 2112 . Because self-refresh is performed in the DRAM field when the SCR mode is set, the refresh address may be generated as an internal address and the above-mentioned signals are supplied to prevent this condition. Because the external addresses are adopted as command data, the command data can be set in the command register without affecting the operation of the DRAM when the DRAM field is active (by executing the DRAM active mode).

[Cache operation)

Fig. 111 shows an example for the cache system structure. As shown in Fig. 111, the cache system includes a CPU 3000 as an external processing unit, a CDRAM 3200 serving as a main memory and a cache memory, and a cache control circuit 3100 for controlling access to the CDRAM 3200 . The CDRAM 3200 has an SRAM section 3210 and a DRAM section 3230 that are driven independently, and a bidirectional data transfer circuit (DTB) 3220 for performing data transfer between the SRAM section 3210 and the DRAM section 3230 and data output outside on.

The cache control circuit 3110 has a decoder 3102 for decoding a set address which is applied by the CPU 3000 , for generating a signal for selecting a corresponding set, a tag memory 3106 for storing a tag address for the respective set, a write indicator bit memory 3104 for storing whether the contents of the SRAM section 3120 and the DRAM section 3230 are different from each other in accordance with the tag address in the tag memory, a controller 3108 which receives the chip selection address and the tag address from the CPU 3000 reading the tag address of the set set by decoder 3102 in tag memory 3106 , determining whether or not the tag addresses match, and determining whether the chip select address specifies CDRAM 3200 , and Generating a control signal in accordance with the determination result, and a (write-back) selector 3100 for storing the tag address from the CPU 3000 in the corresponding set of tag memory 3106 in the event of a cache miss (if the tag address does not match) and to apply to CDRAM 3200 the internal address read from tag memory 3106 .

In CDRAM 3200 , a row in SRAM section 3210 enables data transmission with any column block of DRAM section 3230 . Therefore, a desired mapping type (direct mapping, set-associative and fully associative mapping) can be carried out.

As shown in FIG. 111, the multiplexer circuit 3300 multiplexes the row address and the column address upon access to the DRAM section 3230 and selects one of the addresses from the CPU 3000 and the selector 3110 in the cache control circuit 3110 . The operation will now be described.

In the CDRAM 3200 , a line can be kept in the selected state by the DRAM active mode (ACT mode) in the DRAM field. The data of the memory cells connected to this one row are amplified and locked by the DRAM sense amplifier. The DRAM sense amplifier is used as a cache in the present invention.

[Write-back cache system]

In the write-back system (system with write-back strategy), the contents of the cache memory are transferred to the main memory in the event of a cache miss. More specifically, data is transferred from the SRAM section 3210 to the DRAM section 3230 (writeback). There are two different ways to address the CDRAM 3200 in the write-back cache. More specifically, this is (a) no assignment at the time of data write (data is not written to the SRAM section) and (b) data is written in both read and write operations in the event of a cache miss (assignment).

i) Unassigned mode

Access to the CDRAM without assignment is described with reference to the flowcharts of Figs. 112 and 113.

If there is an access request from the CPU 3000 (step S2), it is determined (step S4) whether the process is a data read or a data write. The controller 3108 shown in Fig. 111 determines whether there is an access request (chip select port).

If it is determined in step S4 that there is a data read, it is determined whether or not the data requested by the CPU 3000 is stored in the SRAM field (step S6). If it is determined that the value requested by the CPU 3000 is in the SRAM field (due to a match, non-match between the tag address stored in the external memory of the cache control circuit 3100 and the tag address, established by the CPU 3000 is determined), the SRAM read mode (SR cycle) is determined (step S7). Consequently, in the SRAM field, the selection of the memory cell is made in accordance with the block address and the set of the CPU address. The data of the selected SRAM memory cell are read. After step S7, the process returns to step S2.

If it has been determined that the data requested by the CPU 3000 is not in the SRAM field (cache miss), it is first determined in step S6 whether the write indicator bit is set or cleared (step S8). If the write indicator bit is cleared, it means that the content of the cache matches the content of the main memory. The change in the data in the SRAM field has already been transferred to the data in the memory cell of the DRAM field. In this case it is determined whether the same page is addressed or not. More specifically, it is determined whether the CPU determines the row that has been selected in the DRAM field (step S10).

In the DRAM field, the line that was selected in the previous cycle is always kept in the selected state. Because part of a set address and a tag address from the CPU or a CPU address corresponds to a DRAM row address, it is determined by comparing the address sections whether the same page is accessed or not. This process is performed in controller 3108 shown in FIG. 111. The line of the DRAM that is in the selected state is the line that was selected in accordance with the tag address in the tag memory in the event of a cache miss in a previous cycle, or the line that is determined by the CPU address is. After the write-back process, a new line can be selected according to the CPU address. Alternatively, the line that is selected in accordance with the tag address can be set to the selected state. Both structures can be used.

If it is determined in step S10 that the page is not the same is addressed, that is, if it is determined that a other line of the DRAM field is specified, the DRAM Precharge mode (PCG cycle) executed (step S12). Hence the line that was in the selected state put in the unselected state.

Then a DRAM active mode process (ACT cycle) performed (step S14). As a result, one line of the DRAM Field corresponding to the currently created CPU address in the selected state, and the data of the Memory cells connected to the selected one row are detected, amplified and by the DRAM sense amplifier locked.  

If it is determined in step S10 that the same page is accessed, or if the DRAM active mode in step S14 is executed, the DRAM read transfer mode (DRT cycle) executed (step S16). Consequently, the data of those Transfer memory cells to the read data transfer buffer circuit, which are connected to the selected row of the DRAM field, that is determined by the column block address Column block is located.

Then the buffer read transfer / read mode (DRT cycle) executed (step S18). In this operating mode, the Data stored in the read data transfer buffer corresponding to the CPU address for the selected line in the SRAM field transferred, and data is transferred in parallel to the data transfer to SRAM field read according to the CPU address (data can read directly from the read data transfer buffer circuit become).

In step S8, a set write indicator bit indicates that the content of the SRAM field and the corresponding set of the DRAM Field are different. In this case, the SRAM Buffer write transfer mode (BWT cycle) executed (step S9). As a result, the data of the memory cells of the CPU Address in the SRAM field selected line for write data Transfer buffer circuit. Then, as in step S10 determines whether the same page is accessed or not (Step S11).

If it is determined in step S11 that the page is not the same is addressed, the DRAM precharge mode (PTG cycle) and the DRAM active mode (ACT cycle) (Steps S13 and S15). As a result, a Row selection according to the one currently selected by the CPU created address executed, and the data of the memory cells, which are connected to the selected line are recorded, amplified and locked by the sense amplifier. Then the DRAM read transfer mode (DRT cycle) and the Buffer read transfer / read mode (DRTR cycle) performed  (Steps S17 and S19). As a result, even with one Cache miss or a high page miss Read speed.

Then the controller waits for the next access request (Step S21). It is determined whether the next Access request affects the same page or not (step S27). The determination of whether the same page is being accessed takes place as follows: It is determined whether the line to the the memory cells with those in the buffer write transfer mode (BWT- Cycle) in step S9 in the write data Transfer buffer circuit include stored data, and the The line currently selected in the DRAM field is the same Display line. This determination can be made using the Tag addresses are given. If it is determined in step S23 that the same page is accessed, the DRAM Write transfer mode 1 (DWT1 cycle) performed (S29). Therefore become those in the write data transfer buffer circuit stored data for the corresponding position of the DRAM field transfer.

If the same page is not accessed, the DRAM precharge mode (PCG cycle) and DRAM active mode (ACT- Cycle) carried out sequentially (steps S25 and S27), and the Line of the DRAM field in which the data Transfer buffer circuit stored data are stored in the selected state. After step S27 the flow advances to step S29. The content of the set in the SRAM field with the content of the corresponding set of the DRAM field match.

After steps S18 and S29, the flow returns to step S2 back to wait for the next access.

If it is determined in step S4 that there is a data writing operation, the control flow shown in Fig. 113 is performed. If a data write operation is specified, it is first determined whether the memory cell in the SRAM field that the CPU wishes to access exists (step S30). If this is the case, that is to say in the case of a cache hit, the SRAM write mode (SW cycle) is executed (step S32), and data are written into the corresponding memory cell of the SRAM field in accordance with the CPU address. The corresponding write indicator bit is then set in the control circuit 3100 . As a result, a state is displayed in which the content of the SRAM field and the content of the corresponding data block of the DRAM field are different from each other (step S34). Upon completion of step S34, control returns to step S2 shown in FIG. 112.

It is determined in step S30 that a cache miss the buffer write mode (GW cycle) is executed (Step S31). Consequently, according to the CPU address of the SRAM write data to the corresponding position of the write data Transfer buffer circuit written. With locking this Holds write data in the write data transfer buffer circuit the control flow to move on to the next access request wait (step S33). If the next access request is made, it is determined whether this access request is a line concerns that are currently in the DRAM field in one selected state (step S35).

It is found that the CPU has access to a line requests that is different from the line that is currently is selected in the DRAM field, steps S37 and S39 executed, the DRAM field is preloaded and activated, and a line corresponding to the CPU address is selected in the State shifted. Then the DRAM Write transfer mode (DWT cycle) executed, and the data that has been stored in the write data transfer buffer circuit are written to a corresponding position on the line, which is currently selected in the DRAM field (step S41). Step S41 is carried out even if in step S35 it is determined that the same page is to be accessed. Upon completion of step S41, control returns to step S2 back.  

As described above, by using the Sense amplifier of the DRAM section as a cache Data writing / reading performed at high speed if the data requested by the CPU is a Memory cell not stored in the SRAM field, but from Sense amplifiers are locked in the DRAM field.

When transferring data from the write data The transfer buffer circuit to the DRAM field becomes the command DWT (DWT1) run continuously as long as the CPU has the same line of the DRAM field. This enables data writing with high speed.

ii) assignment mode

Figs. 114 and 115 show flow charts of access to the cache memory when memory with write-back strategy, an assignment is performed on a cache miss in a cache. Referring to FIGS. 114 and 115, the access operation of the CDRAM will be described.

Fig. 114 shows a flowchart of the operation in data reading. The process flow shown in FIG. 114 matches the previous unassigned process flow shown in FIG. 112. Corresponding steps are therefore designated by the same reference numerals and their detailed description is not repeated here.

Fig. 115 shows a flow chart of data write operation with allocation in a cache system with write-back strategy. In the data writing process, it is first determined in S50 whether there is a cache hit or not. If a cache hit is detected, the SRAM write mode (SW cycle) is executed (step S51). In accordance with the CPU address, data is written into the corresponding memory cell of the SRAM field. Then, the write indicator bit corresponding to that of the CPU address set is set in the cache control circuit 3100 (step S51). Then the control sequence returns to step S2 shown in Fig. 114.

If it is determined in step S50 that the access has a cache Represents miss hit, the buffer write mode (BW cycle) executed (step S53). Then it is determined whether the CPU access request one memory cell in one Line determines which is currently in the DRAM field in the selected state (step S54). If the CPU Address does not match the row address of the row in the DRAM field matches which is currently in the selected state the DRAM precharge mode (PTG cycle) is executed (Step S55). Then in accordance with the CPU address the DRAM active mode (ACT cycle) is performed (step S56).

If it is determined in step S54 that the same page is accessed, after step S56 the DRAM Write transfer mode 1 / read mode (DTW1R cycle) executed (Step S57). The data in the write data Transfer buffer circuit stored data to the appropriate Column block position in the selected row of the DRAM field written. With the command DWT1R the data of the selected column blocks simultaneously with the data writing into the DRAM field for the read data transfer buffer circuit transfer. Then the buffer read transfer mode (BRT- Cycle) (step S58). Consequently, they become Read data transfer buffer circuit transferred data in the corresponding line of the SRAM field. So be the write data both in the DRAM field and in the SRAM field saved.

It is then determined whether the write indicator bit is set or is deleted (step S59). Is the write indicator bit deleted, control returns to step S2. Is this Write indicator bit is set, the buffer write transfer mode (BWT cycle) executed, and the memory cell data of the SRAM, which are determined by the CPU address become the Transfer write data transfer buffer circuit (step S60). When the next access request is made (step S61), determines whether the data on which the CPU is at that moment want to access, exist in the line that is  is currently in the selected state in the DRAM field (Step S62). It is found that access is not on same page, the precharge mode will be successively (PCG cycle) and the DRAM active mode (Acc cycle) (Steps S63 and S64), and the row selection process of the DRAM Field is carried out according to the CPU address. Is in Step S62 determined that access to the same page or after completion of step S64, the DRAM Write transfer mode (DWT cycle) executed. Corresponding become those in the write data transfer buffer circuit stored data on the corresponding position of the selected Transfer line of the DRAM field (step S65). Through the above described operating mode is in the DRAM field the line according to the CPU address in the selected state, the DRAM sense amplifier can be used as a pseudo cache for a cache Missed hits are used, and thus the Access time worsened in the event of a cache miss be minimized.

[Carbon copy mode]

In write-through mode, in the event that that data is written into the SRAM field, the written ones Data always in the corresponding memory cell of the DRAM field written. In this case, the process flow differs depending on the presence / absence of one To assign.

a) Copy procedure with assignment

Figs. 116 and 117 are flowcharts showing the operation according to the write-through method, when an assignment is carried out. Referring to FIGS. 116 and 117 access to the CDRAM in the cache memory system is described.

First, the data reading operation will be described with reference to FIG. 116.

If there is an access request from the CPU (step S70) it is determined whether the access request is a Represents data reading or writing (step S72). If it is determined that there is a data read, a cache hit / miss is determined (step S74). At a Cache hit, the SRAM read mode (SR cycle) is executed, and the data of the memory cell derived from the CPU address in the SRAM field is set to be read (step S75). To Step S75 returns control to step S70.

In the event of a cache miss, it is first determined whether the CPU Address is correct that is currently selected in the DRAM field in the State (step S76). It is determined that the CPU is the one Line of the DRAM field that is currently selected, then the DRAM read transfer mode (DRT cycle) is performed (Step S78). Therefore, the data of the column block that is from the CPU address is set in the DRAM field, for read data Transfer buffer circuit. In step S76 determines that the CPU address is another line of the DRAM field the DRAM precharge mode (PTG cycle) and the DRAM active mode (ACT cycle) executed (steps S77 and S79). In the DRAM field, the line specified by the CPU address is in the selected state, and the DRAM Sense amplifiers are the data of the memory cells that with the selected row are locked. After step S79 step S78 is executed, and that of the CPU address specified data block becomes the read data Transfer buffer circuit.

Then the buffer read transfer / read mode (BRTR cycle) executed (step S80), which in the read data Transfer buffer circuit stored data becomes corresponding position of the SRAM field transmitted, and that of data requested from the CPU are read. After completing In step S80, the control flow returns to step S70.

If it is determined in step S72 shown in FIG. 116 that the write mode is set, the process shown in FIG. 117 is performed. First, a cache hit / miss is determined (step S82). When a cache hit is detected, the buffer write transfer / write mode (BWTW cycle) is performed. As a result, external write data is written into the memory cell of the SRAM array specified by the CPU address and the corresponding register of the write data transfer buffer circuit. In this mode of operation, the data of the row selected in the SRAM field and the write data are stored in the write data transfer buffer circuit.

If the next access request is made after step S74 is determined (step S86) whether this access request defines the line of the DRAM field that is in the selected state (step S88). If it is determined that the same line is set, that is, the same page the DRAM write transfer mode (DWT cycle) executed (step S90). Consequently, those in the Write data transfer buffer circuit for stored data selected column of the DRAM field (that of the CPU address is fixed) transferred.

If a line is set in step S88 which is different from the selected row of the DRAM field is different the DRAM precharge mode (PCG cycle) and the DRAM Active mode (ACT cycle) executed according to the CPU address, by the line specified by the CPU address in the selected Set state (steps S92 and S94). Through step S94 the line corresponding to the CPU address in the DRAM field in the selected state, the data of the memory cells that connected to the selected line are recorded, amplified and locked by the sense amplifier, the control flow returns to step S90 and the DRAM write transfer mode is running.

If it is determined in step S82 that the access has a cache Represents miss hit, the buffer write mode (BW cycle) executed (step S81). As a result, external write data to the corresponding buffer of the write data Transfer buffer circuit written. The tax flow stops  this state to the next access request waiting. If the next access request is created (step S83), it is determined in a similar manner to step S88 whether the same page is set or not. Is the same page the DRAM write transfer mode 1 (DWT1 cycle) performed (step S87). Therefore, the write data that has been stored in the write data transfer buffer circuit are transferred to the selected column of the DRAM field.

It is determined in step S85 that another page is set the DRAM precharge mode and the DRAM Active mode executed (steps S89 and S91), and that of the CPU address specified line is in the DRAM field in the selected state. Step S87 closes and that into the write data transfer buffer circuit written data is sent to the corresponding location of the DRAM Field. After steps S90 and S87, the Control flow returns to step S70.

b) Copy procedure without assignment

Figures 118 and 119 show flowcharts of the CDRAM's unassigned access operation in a write-through strategy cache. Described with reference to FIGS. 118 and 119, the Vorgangsfluß. Fig. 118 shows the process flow in the data reading operation. This is the same process as the write-through method with assignment as shown in Fig. 116, and therefore the corresponding steps are indicated by the same reference numerals and their detailed description is not repeated here.

Referring to the flowchart of Fig. 119, the write-through data write operation will be described.

A cache hit / miss is determined in step S100. If a cache hit is recorded, the Buffer write transfer mode (BWTW cycle) executed (step S102). With this BWTW cycle, external write data are stored in  the corresponding memory cell of the SRAM field is written, and the data block (one line) of the SRAM that contains the written ones Containing data is in the write data transfer buffer circuit written. In this state, the control waits for the next access.

At the next access request (step 104) determines whether the CPU address specifies the line that is is currently in the selected state in the DRAM field (Step 106). The CPU address sets the selected line in the DRAM field is fixed, the DRAM write transfer mode (TWT cycle) executed (step S108). Consequently, those in the Write data transfer buffer circuit stored data for corresponding column block of the selected row in the DRAM field transfer.

It is determined in step S106 that the CPU address is not the selected line of the DRAM field is set in the DRAM field the DRAM precharge mode (PCG cycle) is executed, the DRAM Field returns to the precharge state (step S107). Then it will be using the CPU address the DRAM active mode (ACT- Cycle), a line is selected in the DRAM field, and the data of the memory cells with the selected row connected, are detected, amplified and by the sense amplifier locked (step S112). Then step S108 and that in the write data transfer buffer circuit stored data will become the corresponding location of the selected line of the DRAM.

If it is detected in step S100 that there is a cache miss, the buffer write mode (BW cycle) is executed first, and external data is stored in the write data transfer buffer circuit written (step S101). Then it is detected whether the CPU address specifies the line that is selected in the DRAM field (Step S103). If so (that is, it will open up same page accessed), the DRAM Write transfer mode 1 / read mode (DWT1R cycle) carried out (Step S105). This means that the Transfer buffer circuit stored data for the corresponding  Place the selected line in the DRAM field and further to Transfer read data transfer buffer circuit.

If it is determined in step S103 that the same page the DRAM precharge mode (PCG cycle) performed (step S107), and then coincidence the DRAM active mode (ACT cycle) is executed with the CPU address (Step S109). As a result, the CPU Address specified page selected and the DWT1R cycle executed (step S105). Then the buffer read transfer mode (BRT cycle) executed, and the data contained in the read data Transfer buffer circuit have been saved too the line transferred from the CPU address in the SRAM Field is set.

As described above, in data write mode, the Hit process for another address quickly if data is in the SRAM field or the write data Transfer buffer circuit can be written. That enables one Access at high speed.

[Detailed structure of the bidirectional data transmission circuit]

Fig. 120 shows the structure of the bidirectional data transmission circuit. As shown in FIG. 120, the bidirectional data transfer circuit has a write data transfer circuit 3520 for transferring data to the DRAM section 3500 and a masking circuit 3530 for masking the transfer of write data to the write data transfer circuit 3520 . the write data transfer circuit has an intermediate write data register TDTBW for temporarily storing data and a write data transfer buffer TDBW, which receives data from the intermediate register TDTBW, for transferring the data to the DRAM section 3500 . Sometimes the write data transfer buffer DTBW also transfers data to the read data transfer buffer DTBR.

The masking circuit 3530 has an intermediate masking register TNR, a master masking register MR which receives the masking data from the intermediate masking register TMR, and a masking gate circuit 3540 which receives the masking data from the master masking register MR for masking the write data from the write data transfer buffer DTBW. The operation for masking the write data transfer will now be briefly described.

First, an operation when the block write mode is executed will be described with reference to FIG. 121.

In this case, externally created data are in a corresponding register of the intermediate register TDTBW accordingly the output written by the column decoder. Parallel to The data write to the intermediate register TDTBW Masking data of the corresponding register in the Intermediate mask register TMR reset. The deferred masking data allow passage of the Data. Set masking values block the passage of Data.

Referring to Fig. 122, the write data transfer process to the DRAM array will be described. When the DRAM write transfer mode 1 is set, the data stored in the intermediate register TDTBW is transferred to the write data transfer buffer DTBW. In parallel with this transfer, the mask values from the intermediate mask register TMR to the master mask register MR and data to the mask gate circuit 3540 are transferred. The mask gate circuit 3540 masks the write data from the write data transfer buffer DTBW in accordance with the applied mask data and transfers it to the DRAM field.

The data transfer from the intermediate registers TDTBW and TMR too the corresponding buffers DTBW and MR will be in the first cycle after setting the data transfer. At the end of masking data of the first cycle Intermediate mask register TMR all set. From the next  It is possible to put data into the cycle Write data transfer circuit (intermediate data register) to write according to the buffer write mode. Because that Masking register is formed, it is possible to only the write the required data into the DRAM field. If data are transmitted from the SRAM field, the masking data in the Intermediate mask registers all reset. In this case the data of the write data transfer buffer are all transferred to the DRAM Transfer field section. Referring to the special Signal diagrams become the process of transferring the write data described.

Figure 123 is a signal diagram of the operation of the bidirectional data transfer circuit when data transferred from the SRAM array is written into the DRAM array. As shown in FIG. 123, the DRAM active mode (ACT cycle) is executed in the DRAM section in the first cycle of the master clock signal K. As a result, a row selection operation is performed in the DRAM field. In the SRAM field, the buffer write transfer mode (BWT cycle) is determined in accordance with the conditions of the control clock signals CC0 #, CC1 # and the write activation signal WE #. As a result, the data of one row of memory cells (16 bits) selected in the SRAM field is transferred to the intermediate data register (value 0 to value 15). In the data transfer cycle from the SRAM field to the intermediate data register, the masking data (masking 1 to masking 15) of the intermediate masking register are all reset.

In the fourth cycle of the master clock signal K, the DRAM Write transfer mode 1 (DWT1 cycle) through the column address Strobe signal CAS # and the data transfer designation signal DTD # set. In the DWT1 cycle, the data (value 0 to Value 15), which are stored in the intermediate register, for Write data transfer buffer DTBW <0-15 <(DTBW0-DTBW15) transfer. At the end of the first cycle of the DWT1 cycle, the Masking data in the intermediate masking register all set. From the fifth cycle of the master clock signal K is the Data transfer from the SRAM field to the intermediate data register possible.  

After the latency of the DWT1 cycle has passed, those are Write data already from the write data transfer buffer DTBW transferred to the DRAM field according to the masking data been. In the seventh cycle of the master clock signal K is again the BWT cycle is set, and the masking data of the Intermediate mask registers are all reset. in the eighth cycle of the master clock signal K, the DRAM Write transfer mode 2 (DWT2 cycle) defined. In this case there is no data transfer between the intermediate data register and the write data transfer buffer. The in Write data transfer buffer stored data becomes selected memory block of the DRAM field.

After the ninth cycle of the master clock signal K, the NOP Mode (no operation) set, and the internal state of the CDRAM does not change.

When transferring write data from the SRAM field, the Masking data of the intermediate masking register all reset. In contrast, the data transmission from Write data transfer buffer to the DRAM field, that is, at the Data transfer from the intermediate data register to Write data transfer buffer, the masking data of the Intermediate mask register after the completion of this cycle (Clock signal cycle) all set.

Fig. 124 shows a signal diagram of the change in masking data when the buffer write mode is executed. As shown in FIG. 124, the DRAM active mode (ACT cycle) is executed in the first clock signal cycle of the master clock signal K. In contrast, the block write mode (BW cycle) is carried out in the SRAM section, and externally applied data (value 0) are written into the corresponding registers of the intermediate data register corresponding to the address bits As0 to As3. In parallel to data writing, the masking data (masking value 0) of the corresponding intermediate masking register are reset. A maximum of 16 data bits can then be repeatedly written to the intermediate data register (the intermediate data register and the write data transfer buffer have a width of 16 bits). When the respective data is written, the masking data of the corresponding intermediate masking register are reset.

In the fourth cycle of the master clock signal K, the DWT1 cycle is generated in the DRAM section. When this operating mode is set, data transfer from the intermediate data register to the write data transfer buffer is carried out in the first cycle (the fourth clock signal cycle of the master clock signal K). With the completion of the first cycle, the masking data of the intermediate masking register are all set. Then, the write data that has been transferred to the write data transfer buffer is transferred to the selected memory cell block of the DRAM array. After the data transfer from the intermediate data register to the write data transfer buffer, that is, in the second cycle of the DWT1 mode, it is possible to write data into the intermediate data register. As shown in Fig. 124, from the fifth cycle of the master clock signal K, the buffer write operation (BW cycle) is carried out again. In parallel to the data writing, the masking data of the corresponding intermediate masking register are reset.

When performing the above procedure, the Data transfer to the DRAM field by transferring the Masking data can be safely masked. Because the two - stage structure of the intermediate register and Write data transfer buffer is formed, it is possible Write data from outside or from the SRAM field itself during the Transfer data to the DRAM field. This allows access at high speed.

Fig. 125 shows the structure of the write data transmission system. As shown in FIG. 125, the write data transfer buffer circuit 3520 has an intermediate data register 4002 and a write data transfer buffer 4004 . The intermediate data register 4002 and the write data transfer buffer 4004 both have the structure of an inverter latch.

The write data transfer buffer circuit 3520 further includes a transfer gate 4010 which receives an output signal / SSA of the SRAM sense amplifier, a transfer gate 4012 which switches on depending on the buffer write transfer activation signal WWTE, a transfer gate 4018 which depends on the output signal SSA0 from the SRAM sense amplifier , a transfer gate 4020 which switches in response to the buffer write transfer activation signal BWTE, and transfer gates 4014 and 4016 which switch in response to the buffer gate write signal DYW which is generated in the buffer write mode only for the selected register. The buffer gate write signal DYW is generated only for that register in data writing which is subjected to data writing. The output signals SSA0 and / SSA0 of the SRAM sense amplifier correspond to the output signal of the first sense amplifier 1612 shown in FIG. 84.

The transfer gates 4010 and 4012 are connected in series. When both are turned on, they set the latch node / E of the intermediate data register 4002 to the ground potential level. The transfer gates 4018 and 4020 set the latch node E of the intermediate data register 4002 to the ground potential when the output signal SSA of the SRAM sense amplifier and the buffer write transfer activation signal BWTE both reach the "H" level. The output signals / SSA0 and SSA0 of the sense amplifier are complementary to one another. Therefore, when the buffer write transfer mode is set, the transfer gates 4012 and 4020 are both turned on and complementary data is latched to the latch nodes / E and E of the intermediate data register 4002 .

When the buffer write mode is set, the buffer gate write signal BYW is generated only for those data registers which are subjected to data write. The gates 4014 and 4016 are thereby switched through and the data on the internal write data lines DBW and / DBW are locked by the intermediate data register 4002 . Complementary data is transferred to the internal write data lines DBW and / DBW.

The write data transfer buffer circuit 3520 further includes a transfer gate 4022, which is turned on in response to the output of the latch node / E of the intermediate data register 4002, a transfer gate 4004, which is switched in dependence on the DRAM write transfer enable signal BWTE, a transfer gate 4026, the is switched on depending on the output signal of the latch node E of the intermediate data register 4002 , and a transfer gate 4024 which is switched on depending on the DRAM write transfer activation signal DWTE. The transfer gates 4022 and 4023 are connected in series. They transfer data representing the inverse of the data locked at the latch node / E of the intermediate register 4002 to the latch node / F of the write data transfer buffer 4004 depending on the DRAM write transfer activation signal DWTE. The transfer gates 4024 and 4026 are connected in series and transfer the data, which represent the inverse of the data at the latch node E of the intermediate data register 4002 , to the latch node F of the write data transfer buffer 4004 in response to the DRAM write transfer activation signal DWTE.

And the masking circuit 3530 has an intermediate masking register 4006 , a master masking register 4008 and a masking gate circuit 3540 . Registers 4006 and 4008 are both formed by inverter latches.

The masking circuit 3530 further comprises a transfer gate 4028 , which is dependent on the buffer gate write signal DYW, for setting the latch node / G of the intermediate masking register 4006 to the ground potential, a transfer gate 4030 , which is dependent on the buffer write transfer activation signal BWTE, for setting the latch -Node / G of the intermediate masking register 4006 to the ground potential, a transfer gate 4032 which is switched in response to the mask register setting command / MRS from the command register, a transfer gate 4034 which is switched in response to the buffer gate write signal WYW, and a transfer gate 4036 which is switched through depending on the DRAM write transfer activation signal DWTE.

The transfer gates 4032 , 4034 and 4036 are connected in series and switch through when the signal supplied to the respective gate reaches the "L" level. If the gates 4032 , 4034 and 4036 are all switched through, a signal with supply potential level is transmitted to the latch node / G of the intermediate masking register 4006 .

The masking circuit 3530 further comprises a transfer gate 4037 which is switched on depending on the value of the latch node / G of the intermediate masking register 4006 , a transfer gate 4039 which is switched on in response to the DRAM write transfer activation signal DWTE, and a transfer gate 4040 which is dependent on is switched through by the output signal at the latch node G of the intermediate masking register 4006 , and a transfer gate 4030 which is switched on in response to the DRAM write transfer activation signal DWTE. Transfer gates 4037 and 4039 are connected in series and transmit a ground potential signal to the latch node / H of master mask register 4008 when both are turned on.

The transfer gates 4038 and 4040 are connected in series and transmit a signal with level "L" (ground potential level) to the latch node H of the masking register 4008 when both are turned on. The intermediate mask register 4006 is set when its masking node / G is set to "H" and is reset when the masking node / G is at "L".

The masking gate circuit 3540 has a 3-input gate circuit 4042 which receives the DRAM write data activation signal DWDE, the output signal of the latch node / F of the write data transfer buffer 4004 and the output signal of the latch node / H of the masking register 4008 , an inverter circuit 4046 Inverting the output of gate circuit 4042 , a 3-input gate 4044 , the DRAM write data enable signal DWDE, the latched data at latch node S of write data transfer buffer 4004, and the latched data at latch node / H of masking register 4100 receives, and an inverter circuit 4048 for inverting the output signal of the gate circuit 4044 .

Gate circuit 4042 only sets its output signal to "L" when its three inputs all reach "H" (it represents a NAND circuit). The gate circuit 4044 only outputs a signal with level "L" if its three inputs are all at "H".

A write amplifier 3550 is formed between masking gate circuit 3540 and global IO lines GIOa and / GIOa. The write amplifier 3550 has n-channel MOS transistors 4052 and 4054 , which receive the output signal of the inverter circuit 4046 at their gates, and n-channel MOS transistors 4050 and 4056 , which receive the output signal of the inverter circuit 4048 at their gates. The transistors 4050 and 4054 are connected in series between the supply potential and the ground potential, while the transistors 4052 and 4056 are connected in series between the supply potential and the ground potential. The connection point between transistors 4050 and 4054 is connected to the global IO line GIOa, while the connection point between transistors 4052 and 4056 is connected to the global IO line / GIOa.

The operation will now be briefly described. When write data is to be transferred from the SRAM field, the buffer gate write signal DYW is not generated, but is kept in the "L" state. The data on the SRAM bit line pair SBL is amplified by the SRAM sense amplifier and transmitted to the gates of the transfer gates 4010 and 4016 . The sense amplifier output signal SSA0 is assumed to be "H". In this case, the transfer gate 4010 is blocked and the transfer gate 4018 is switched through.

When the output of the SRAM sense amplifier has stabilized, the buffer write transfer enable signal BWTE rises to "H" and the transfer gates 4012 and 4020 are turned on. Because the transfer gate 4010 is blocked and the transfer gate 4018 is switched through, the potentials “L” and “H” are transferred to the latch nodes E and / E of the intermediate data register 4002 and locked there.

In the masking circuit 3530 , the transfer gate 4030 switches on depending on the rise of the buffer write transfer activation signal BWTE and the potentials at the latch nodes / G and G of the intermediate masking register 4006 reach the levels "L" and "H", respectively. The mask register set bit / MRS is assumed to be "L". The transfer gates 4032 , 4034 and 4036 are switched through. When the transfer gate 4030 turns on in response to the buffer write transfer activation signal DWTE, the potential of the latch node / G becomes slightly lower than the potential at the latch node G. This drop in the potential is amplified by the inverter in the intermediate masking register 4006 and accordingly reaches the potentials the latch nodes G and / G the levels "H" and "L".

The sequence of operations described above resets the masking data in the intermediate masking register 4006 in synchronism with the data transfer to the intermediate data register 4002 during the data transfer from the SRAM field to the write data transfer buffer circuit .

In the buffer write mode, that is, when external data is to be written into the write data transfer buffer circuit, the buffer gate write signal BYW is generated only for the corresponding write data transfer buffer. In this case, external write data is transferred to the intermediate data register 4002 via the transfer gates 4014 and 4016 , while the corresponding intermediate mask register 4006 is reset.

Around the DRAM write transfer enable signal (DWTE), which indicates the data transfer from the write data transfer buffer to the DRAM field, is now generated (by setting the DRAM write transfer mode). As a result, transfer gates 4023 , 4024 , 4039 and 4038 turn on. The potentials at the latch nodes E and / E of the intermediate data register are now at "L" and "H" (the SRAM sense amplifier output signal SSA0 is at "H"). As a result, transfer gate 4022 turns on, transfer gate 4026 blocks, and latch nodes F and / F of data transfer buffer 4004 reach levels "H" and "L", respectively.

In the master masking register 4008 , the potential of the latch node / G is at "L", the transfer gate 4037 is blocked and the transfer gate 4040 is turned on . Therefore, the latch nodes H and / H are at "L" and "H", respectively.

Transfer gate 4036 is disabled while DRAM write transfer enable signal WRTE is being generated. The transfer gate 4030 is also locked. Although the potential of the latch node / G of the intermediate mask register 4006 is locked by the inverter latch, it is placed in an electrically floating state during this period. When the DRAM write transfer enable signal DWTE falls to "L", the transfer gate 4036 turns on, the supply potential level signal is transferred to the latch node / G, and the masking value stored in the intermediate masking register 4006 is set (the potential at the latch node / G is on "H").

After data transfer to the write data transfer buffer 4004 and master mask register 4008 , the DRAM write data activation signal DWDE is generated. As a result, the data stored in the write data transfer buffer 4004 and the mask data stored in the master mask register 4008 are applied to the mask gate circuit 3540 . Now the potential at the latch node F of the write data transfer buffer 4004 is at "H" and the potential at the latch node F is at "L". The potential at the latch node / H of the masking register 4008 is "H". As a result, the output signal of the gate circuit 4042 reaches the "H" level and the output signal of the gate circuit 4044 reaches the "L" level. The output signals of circuits 4042 and 4044 are inverted by inverter circuits 4046 and 4048 . As a result, in the write driver (amplifier) 3550, the transistors 4050 and 4056 are turned on and the transistors 4052 and 4054 are blocked. The potential on the global IO line GIOa reaches level "H" and the potential on the global IO line / GIOa level "L".

When the potential at the latch node / H of the master mask register 4008 is "L" to mask the data transfer, the outputs of the gate circuits 4042 and 4044 both reach the "H" level and the outputs of the inverter circuits 4046 and 4048 reach the level "L". As a result, transistors 4050 , 4052 , 4054 and 4056 of write amplifier 3550 are all blocked, the potential on global IO lines GIOa and / GIOa does not change, and the data from the write data transfer buffer circuit is not transferred.

The sequence of operations described above can securely transfer write data at high speed. After the data transfer from the intermediate register to the write data transfer buffer, the masking data of the intermediate masking register are always kept in the set state. Even in the buffer write mode, after the data transfer to the master masking register, that is to say after the BWTE signal has been generated, the masking data of the intermediate masking register 4006 are kept in the set state. The signals of this sequence of processes are shown in FIG. 126.

In Fig. 126, SWL denotes the SRAM word line, SBL the SRAM bit line pair, and DWL the DRAM word line. The dashed lines show the signals when writing buffer.

Fig. 127 shows a structure for the read data transfer buffer circuit. As shown in FIG. 127, the read data transfer buffer circuit has sense amplifiers 5004 and 5008 , which are dependent on the DRAM preamplifier activation signal DPAE, for amplifying the potential on the global IO lines GIOa and / GIOa, a preamplifier 5006 for further amplifying the data which have been amplified by the sense amplifiers 5004 and 5008 in response to the DRAM preamplifier enable signal DPAE, a slave data register 5000 for latching the data which have been amplified by the preamplifier 5006 , and a master data register 5006 for receiving the data which are stored in the slave data register 5000 , depending on the DRAM read transfer activation signal DRTE.

The sense amplifier 5004 has a p-channel MOS transistor 5040 , which receives the signal on the global IO line GIOa at its gate, an n-channel MOS transistor 5044 , which receives the signal on the global IO line GIOa at its gate receives, and an n-channel MOS transistor 5040 , which becomes conductive in response to the DRAM preamplifier activation signal DPAE. The transistors 5040 , 5052 and 5044 are connected in series between the supply potential and the ground potential. An amplified output signal is emitted from the connection node between transistors 5040 and 5042 .

The sense amplifier 5008 has a p-channel MOS transistor 5041 and an n-channel MOS transistor 5045 , which receive the signal on the global IO line / GIOa at their gates, and an n-channel MOS transistor 5043 , which in FIG Depends on the DRAM preamplifier activation signal DPAE. The transistors 5041 , 5043 and 5045 are connected in series between the supply potential and the ground potential. The signal on the global IO line / GIOa that is amplified is output by the connection node between transistors 5041 and 5043 .

The preamplifier 5006 has p-channel MOS transistors 5060 and 5062 , which are connected in parallel between the supply potential and a node J, and p-channel MOS transistors 5064 and 5066 , which are connected in parallel between the supply potential and a node / J, on. Transistors 5060 and 5066 receive the DRAM preamplifier enable signal DPAE at their gates. The gate of transistor 5062 is connected to node / J and the gate of transistor 5064 is connected to node J.

The slave data register 5000 has the structure of an inverter latch. The p-channel MOS transistors 5068 and 5070 are formed between the output nodes J and / J of the preamplifier 5006 and the latch nodes N and / N of the slave data register 5000 and are selectively dependent on the signal potential of the nodes J and / J switched through to transmit the supply potential to the nodes N and / N.

For the slave data register 5000 are n-channel MOS transistors 5072 and 5074 , which are switched on in response to the DRAM preamplifier activation signal DPAE, and n-channel MOS transistors 5076 and 5078 , which have the signals at their gates at nodes J and / J received, educated. The transistors 5072 and 5076 are connected in series between the latch node N of the slave data register 5000 and the ground potential. The transistors 5074 and 5078 are connected in series between the latch node / N and the ground potential.

The mask data register 5002 has the structure of an inverter latch. For masking data register 5002 are n-channel MOS transistors 5080 and 5082 , which are turned on in response to the DRAM read transfer activation signal DRPE, and n-channel MOS transistors 5084 and 5086 , which have the signals at their gates at the latch nodes N and / N of the slave data register 5000 received, formed. And transistors 5080 and 5084 are connected in series between the latch node N of the master data register 5002 and the ground potential. The transistors 5082 and 5086 are connected in series between the latch node / N and the ground potential.

The read data transfer buffer circuit further comprises inverter circuits 5052 and 5054 for inverting and amplifying the potentials at the latch nodes N and / N of the masking data register 5002 and transfer gates 5058 and 5056 , which are dependent on the buffer read transfer activation signal, for transmitting the output signals of the inverter circuits 5052 and 5054 to the SRAM bit lines SBLa and / SBLa. The signals at the latch nodes N and / N of the master data register 5002 are transmitted to the first sense amplifier via a selector ( 1013 ) shown in FIG. 84 and signal lines Buf and / Buf. The signal lines Buf and / Buf form a path for reading data from the read data transfer buffer in the buffer read mode.

The operation will now be described. If the DRAM Read transfer mode is set to one line and one Memory cell block selected in the DRAM field, and accordingly the data read from the DRAM memory cell change Signal potentials on the global IO lines GIOa and / GIOa.

When the DRAM preamplifier activation signal DTAE is subsequently generated, the sense amplifiers 5004 and 5008 and the preamplifier 5006 are activated. It is assumed that the signal potential on the global IO line GIOa is "H", while the signal potential on the global IO line / GIOa is "L". In this case, the potentials at nodes J and / J are "L" and "H", respectively. The signal potential transmitted to nodes J and / J is amplified by transistors 5062 and 5064 at high speed. Transistors 5060 and 5066 have been disabled in response to the DRAM preamplifier enable signal DPAE. Transistors 5060 and 5066 are used to precharge nodes J and / J to the supply potential. Transistors 5062 and 5064 serve to keep nodes J and / J precharged at the same potential (when the DRAM preamplifier enable signal is "L").

The signal transmitted to nodes J and / J is transmitted to the slave data register 5000 via transistors 5068 , 5070 , 5076 , 5078 , 5072 and 5074 . Transistors 5072 and 5074 have been turned on in response to the DRAM preamplifier enable signal DPAE.

Now the potential of node J is at "L" and the potential of node / J is at "H". Therefore, transistors 5068 and 5078 are on and transistors 5070 and 5076 are off . Therefore, the potentials at the latch nodes N and / N of the slave data register 5000 are "H" and "L", respectively. The sequence of these operations completes the data transfer to the slave data register in the read data transfer buffer circuit.

The DRAM read transfer activation signal is then generated. As a result, transistors 5080 and 5082 turn on, and the data stored at latch nodes N and / N of slave data register 5000 is transferred to latch nodes N and / N of master data register 5002 . Because the potential at the latch node N is "H", the transistor 5084 switches on and the transistor 5086 blocks. As a result, the signal potentials at latch nodes N and / N reach levels "L" and "H", respectively. The sequence of these operations completes the storage of data in the master data register 5002 in the read data transfer buffer circuit. The signal potentials at the latch nodes N and / N can be read via the signal lines Buf and / Buf. More specifically, after the latency has passed, the data stored in the read data transfer buffer can be read at high speed by a buffer read mode operation.

At the time of data transfer to the SRAM field, the buffer read transfer activation signal BRTE is generated. As a result, the output signals of the inverter circuits 5052 and 5054 are transmitted to the SRAM bit lines SBLa and / SBLa via the gates 5058 and 5056 . In the structure shown in Fig. 127, the inverter circuits 5052 and 5054 can have the structure of a 3-state inverter circuit which is activated in response to the buffer read transfer activation signal BRTE.

FIG. 128 shows a signal diagram of the read data transfer buffer circuit shown in FIG. 127. The global IO lines GIOa and / GIOa are shown in FIG. 127 in such a way that they are precharged to an intermediate potential (Vcc / 2; Vcc represents the supply level). These lines can also be precharged to the level of the supply potential, as indicated by the dashed line in FIG. 128. In Fig. 128, the precharge potential of the SRAM bit line SBLa and / SBLa is shown as an intermediate potential. In this case too, the lines can be precharged to the level of the supply voltage using a clamp circuit, as shown by the dashed line. The length of time that the DRAM bit line is held in the selected state can be determined by the latency. The timing of the generation of the DWDE signal is determined by the latency. The generation period of the DPAE signal can be determined by the master clock signal. The same applies to the signals of the diagram according to FIG. 126.

Because the read data transfer buffer circuit also the 2- stage latch circuit structure with slave data register and Master data register, data transmission can be secure be executed and the latency control (control of the Time span that is necessary for stable data in the SRAM Field or the data input / output connector DQ may appear) be carried out easily and safely.

Fig. 129 shows a circuit structure for executing control related to data transfer. As shown in Fig. 129, the SRAM control circuit 6000 generates a BWT signal that is dependent on the internal control clock signals CC0, CC1 and the write enable signal WE, setting the data write mode for the write data transfer buffer circuit, a signal BRT, which is an operation for Reading data from the read data transfer buffer circuit for the data input / output port (or the SRAM array) and a signal W / R indicating whether data writing or reading is to be performed. The SRAM driver circuit 6006 generates the necessary control signals, namely the buffer write transfer enable signal BWTE, the buffer read transfer enable signal BRTE and similar signals in response to the BWT and BRT signals, and drives the sense amplifier and selects a row in the SRAM field .

Column decoder 6002 decodes block address bits As0 to As3 and generates a signal to select a corresponding bit position. The gate circuit 6004 generates, in response to the W / R signal from the SRAM control circuit 6000 which specifies the data input / output operation, and the inverted signal of the mask activation signal M and the buffer gate write signal BYW by selectively passing a bit selection signal from the column decoder 6002 . The gate circuit 6004 allows the output of the column decoder 6002 as a buffer gate write signal BYW through only when data writing is set (in the BW mode). The bit selection signal RYW from the column decoder 6002 is also used for the bit selection of the data output system.

It can use a structure in which the column decoder 6002 is activated only when an operation mode for performing data input / output with the environment such as the SRAM read mode, the SRAM write mode, the buffer read mode, the buffer write mode, etc. under control of the SRAM control circuit 6000 is executed. In the SRAM driver circuit 6002 , the master clock signal K is applied because a structure is used in which the transmission control signal is generated depending on the clock signal at the time of data transmission. This structure effects latency control. The length of the latency is set beforehand in the command register.

The DRAM control circuit 6008 determines the set mode in accordance with the master clock signal K, the row address strobe signal RAS, the column address strobe signal CAS and the data transfer determination signal DTD and generates a signal DWT indicating the DRAM write transfer mode DRT, which indicates the DRAM read transfer mode, etc. If the DWT1 mode and the DWT2 mode are set, the signals DWT and DRT are both generated. Depending on the signals DWT and DRT, the DRAM driver circuit 6009 generates the necessary signals, that is to say the DRAM preamplifier activation signal DTAE, the DRAM read transfer activation signal DRTE, the DRAM write transfer activation signal DWTE and the DRAM write data Activation signal DWDE. The DRAM driver circuit 6009 also drives the row and column selection of the DRAM array (namely, it raises the potential of the selected word line, drives the DRAM sense amplifier, etc.).

The mask register setting signal / MRS shown in Fig. 125 is set in the command register setting cycle in the command register. The inverted mask activation signal / M shown in Fig. 129 is applied from the mask activation terminals N0 to N3 when data is written.

Embodiment 3 [Connection arrangement and definition of the signals]

Fig. 130 shows the connection arrangement of the CDRAM according to the third embodiment. As shown in Fig. 130, the CDRAM is housed in a 70 port, 400 mil TSOP (Type II) package. The housing has a connection distance of 0.65 mm and a housing length of 23.49 mm. The signal input / output can be carried out with an LVTTL periphery. The LVTTL level is lower than the ordinary TTL level. The CDRAM can be connected directly to a TTL compatible device. The CDRAM can be connected directly to an external data processing unit, such as a CPU. More specifically, the CDRAM has a controller for determining a cache hit / miss, as will be described later.

The master clock signal TLQ is fed to the connection with the number 27. The CDRAM takes over the external signals synchronously to the master clock signal CLK and the clock frequencies of the internal processes are determined by the master clock signal. The ports numbered 11, 13, 14, 16, 19, 21, 22, 24, 47, 49, 50, 52, 55, 57, 58 and 60 are used from data input / output ports DQ0 to DQ15. For example, the CDRAM has a dynamic memory field with a storage capacity of 2 ²⁰ words _* 16 bits and a static RAM with a 2 ¹⁰ words _* 16 bit structure.

The address signal bits A0 to A21 are the connections with the Numbers 2 to 5, 37 to 45 and 61 to 69 are fed. The Address signal bits A0 to A21 include a memory address and a bank address to determine the SRAM field or DRAM Field. If the storage system is using a plurality is formed by CDRAMs, the memory system can be in four banks can be divided. If it has a 1-bank structure, the address signal bits A0 to A19 become the memory address is used and the address signal bits A20 and A21 are not used.

If the number of banks is 2k, the address signal bits become A0 to A7 and A9 to A20 are used as the memory address while the Address signal bit A8 is used as the bank address. In this case the address signal bit A21 is not used. Is the number of banks equal to 4, the address signal bits A0 to A7 and A10 to A21 used as the memory address, and the address signals A8 and A9 are used as bank address.

The byte activation signals BE0 # and BE1 # become the Connections with the numbers 28 and 29 fed. The Byte activation signal BE0 # controls the least significant bytes (DQ0 to DQ7) and the byte activation signal BE1 # die higher order bytes (DQ8 to DQ15) when writing data is performed. When reading data, the Byte activation signals BE0 # and BE1 # ignored and all 16 bits are driven by connections DQ0 to DQ15.

The connection with the number 6 is an address status signal ADS # fed. The address status signal ADS # corresponds to this Chip activation signal E # of the first embodiment. Located this signal ADS # in the active state (at the "L" level in the following embodiment) with the rising edge of the Master clock signal CLK are the external control signal and  Addresses taken over, and the CDRAM enters the Data transfer cycle for transferring data between the SRAM field and the DRAM field.

A memory / IO signal M / IO #, which is the connection with the number 8 is supplied, the read / write signal W / R #, which is connected to the terminal with the number 9 and the data / code signal D / C #, which is fed to the connection with number 7, Art of the process according to their combinations. This Signals M / IO #, D / C # and W / R # are accepted if that Address status signal ADS # is active.

i) M / IO # equals D / C # equals W / R # equals 0 (equals "L") No reaction and wait for the next address cycle.

ii) M / IO # equals D / C # equals 0 and W / R # equals 1 (equals "H") In this case too, no reaction and wait for the next one Address cycle.

iii) M / IO # is W / R # is 0 and D / C # is 1 In this case the content of the command register is read (to the data input / output connections).

iv) M / IO # is 0 and D / C # is W / R # is 1 In this case, predetermined values are in the command register written and a certain operating mode is determined.

v) M / IO # is 1 and D / C # is W / R # is 0 In this case, a code, such as a command, is made out read the memory.

vi) M / IO # is W / R # is 1 and D / C # is 0 In this case there is no reaction and the cycle returns to Address cycle Ca back to one Wait for access request.

vii) M / IO # is D / C # is 1 and W / R # is 0 In this case, data is read from the memory.

viii) M / IO # equals D / C # equals W / R # equals 1 In this case, data is written into the memory.

The ADC1 / CME # signal is sent to the port number 32 created. The signal CME # is a command register Activation signal. If the command register read command or the Command register write command is supplied and this signal  Read or write is activated in the next cycle the content in the command register. If the Command register read command or the command register Write command is supplied, the command register Activation signal more specifically CME # to "H" and it is in the next cycle set to the active state "L". The signal ADC1 is an address control signal and indicates a bank address.

A block end signal (burst load signal) BLAST # becomes the terminal fed with the number 31. This block end signal BLAST # gives the last of the data transfer cycles of the CPU. There is namely, that when reading or writing data from or to Memory and when writing data to the command register of the last value is passed. If the BLAST # signal is activated, the next cycle is the address cycle Ta to go to the next Address details to wait.

The connection with the number 30 becomes a data hold / sleep signal DH # / SB # supplied. In the data cycle Td, the data waiting cycle Tdw or the data hold cycle Tdh (the cycles become later ) the signal DH # / SB # is used as a data hold signal DH # uses and controls the output buffer. If that Data hold signal DH # is activated, the CDRAM enters the Data holding cycle Tdh and holds the output data until the end the clock signal cycle.

In the address cycle Ta, this signal is called the sleep signal SP # uses and controls sleep mode. That leaves the sleep signal SP # continuously active for 32 clock signal cycles, the CDRAM occurs into a sleep cycle Ts. In the sleep cycle Ts it becomes Sleep signal SP # treated as an asynchronous signal that is not with the clock signal is synchronized.

The connection with the number 34 is the reset signal RST # fed. The reset signal RST # resets the CDRAM. At the Reset process, the CDRAM (i) resets the values in all Command registers to default values, (ii) begins Initialization of the DRAM field and (iii) represents the valid bit of the tag memory back. The reset signal RST # is  adopted asynchronously to the master clock signal CLK. If the signals If DS # and SB # are active, the reset signal RST # is ignored. A signal ADC0 / REF # is given to the connector with number 33 fed. The refresh signal REF # gives the Self-refresh cycle. The signal REF # is considered Input signal or as an output signal (the structure will later described in detail). Whether the signal REF # as an output signal or is used as an input signal is replaced by the Command register set. When the refresh signal REF # is set as the input signal, this signal is used with the rising edge of the master clock signal CLK sampled, and the self-refresh mode starts with the next one Clock signal cycle. Is the refresh signal REF # as Output signal, the signal REF # is set by a internal refresh timer controlled and in sync with Master clock signal CLK output. The refresh signal REF # in this output state controls other CDRAMs in the Storage system, whose refresh signal REF # as an input signal is set. Therefore, the CDRAM memory system can Refresh in synchronism with a CDRAM formed in it execute, and thus during normal operation Self-refresh can be performed as described later becomes.

The signal ADC0 indicates the bank address. The signal ADC0 is together with the address control signal ADC1 described above is sampled when the ADS # signal is activated.

The signals above provide all input signals to the CDRAM (except when the refresh signal REF # in the Output state is offset). The CDRAM has one in it formed controller and includes an output signal to the Communicate the state of internal operation of an external unit.

The block ready signal BRDY is connected to the connection with the no. 26 issued. The block completion signal BRDY # indicates that in the CDRAM the data transfer cycle has been completed and that the CDRAM can be addressed.  

A signal LNE # / KEN # is from the connection with the number 10 submitted. The cache activation signal KEN # indicates that in the CDRAM is performing a data transfer cycle and data in the CPU can be cached. More specifically said displayed that the external CPU the addressed data in a can store the internal cache formed in it. If data in an area to be read that is not for a cache is available (the CDRAM has an area that is not as Cache can be used, and an area called cache can be used as will be described later) at least one waiting cycle is necessary for this signal to be deactivate.

An activation signal for a local memory LME # indicates that the CDRAM has been selected. This activation signal is used as a hit signal or as a bus direction control signal used.

[Internal structure]

Fig. 131 is a block diagram schematically illustrating the internal structure of the CDRAM according to the third embodiment of the present invention. As shown in FIG. 131, a CDRAM 7000 has an external control unit 3100 , which is shown in FIG. 111. More specifically, the CDRAM 7000 has a DRAM array 7001 , an SRAM array 7002 , a bidirectional data transfer circuit (DTB) 7003 for transferring data between the DRAM array 7001 and the SRAM array 7002 , an address buffer / processing circuit 7004 , the external one Address signal bits A0 through A21 and processes them to generate internal address signals, a row address buffer 7006 which receives the internal address signal bits A8 through A19 from the address buffer / processing circuit 7004 , a row decoder 7008 which decodes the addresses output from the row address buffer 7006 by one row in the DRAM Field 7001 , a column address buffer 7030 that receives address signal bits A0 through A7 from address buffer / processing circuit 7004 for generating internal column addresses, a latch circuit 7032 for latching internal column address signals from column address buffer 7030, and a column decoder 7034 that receives the address signals the latch circuit 7032 decoded to put a corresponding column block in DRAM array 7001 in a selected state.

The CDRAM 7000 further includes a tag memory (DG) 7036 for storing the addresses of data stored in the SRAM field 7002 , that is, the tag address, a determination circuit 7038 for comparing the address signal bits A10 to A19 from the address buffer / Processing circuit 7004 with the tag address of the tag memory 7036 for determining a cache hit / miss, a determination circuit 7020 for comparing the internal row address which is locked by the row address buffer 7006 , with the address signal bits A8 to A19 from the address buffer / processing circuit 7004 for detecting a page hit / miss, a return address latch 7024 for storing the tag address from the tag memory 7036 in the event of a cache miss, and a DRAM control and cache / refresh control section 7026 for performing various necessary control operations depending on the page hit / miss hit and cache hit / miss hit by various external control signals and the determination circuits for generating external control signals LME # / KEN # and BRDY #.

The DRAM control and cache / refresh control section 7026 controls the driving of the DRAM array 7001 , the driving of the SRAM array 7002 , the transfer operation of the bidirectional transfer circuit (DTB) 7003, and the operation of changing the latch data of the latch circuits 7008 and 7032 . In the event of a cache miss and a page hit, the address latched in latch 7032 is changed to the address supplied by column address buffer 7030 . In the event of a cache miss and a page miss, the address held in latches 7008 and 7032 is changed. The address latched in latch 7008 is changed to the return address that is currently being applied by return address latch 7024 (for the purpose of writing back). Similarly, the data latched in latch 7032 is replaced by the address signal latched by return address latch 7024 (when writing back). The line decoder 7008 has the function of locking the created address. Consequently, one line in the DRAM field 7001 is always in the selected state, as a result of which the sense amplifiers of the DRAM field 7001 can be used as a quasi-page and furthermore enables page-note transmission. Since the latch circuit 7032 is formed, in the page note transfer, the data transfer can be carried out by selecting the DRAM column block, and a fast write-back operation can also be performed.

Although it has not been described in detail in connection with the above terminal arrangement, there are supply voltage terminals VccQ and ground potential terminals VssQ for the supply potential Vcc and the ground potential Vss, which are used only by the data input / output section in the central region of the chip. Fig. 131 shows supply voltage terminals VccQ (0 to 3) and ground potential terminals VssQ (0 to 3) between the data terminals and the supply voltage Vcc and the ground potential Vss, which are supplied to the other circuit sections.

The DRAM control and cache / refresh control section 7026 samples external control signals with the rising edge of the master clock signal CLK and performs the necessary operation control according to the combination of these signal states. It also carries out the necessary data transfer operation and the change of the latch addresses in accordance with the cache hit signal and the page hit signal from the detection circuits 7038 and 7020 .

Because a tag memory 7036 is formed for storing the tag address in the CDRAM and the circuits for determining a cache hit / miss and page hit / miss are built internally, a memory system with a desired bank structure can easily be created be created. The hit / miss operation can be performed at high speed.

[Command types]

As described above, the CDRAM takes various external control signals with the rising edge of the master clock signal CLK (samples them) and performs the necessary operation according to the states of the external control signals. These external control signals are all applied by an external data processing unit, such as a CPU. Therefore, the DRAM control cache refresh control section 7026 shown in Fig. 131 has a function of decoding instructions supplied from the external CPU and controlling the necessary operations.

Figures 132 and 133 show various commands and the states of the external control signals at this time. In Figs. 132 and 133, the reference character "V" is the status "valid", the reference character "X" to state "not important", reference symbol "L" to logic "low level", and the reference character "H" to "logically high level ". Furthermore, the reference symbols "Hi-Z" denote the "high impedance state", "DIS" the "deactivation state" and "INA" the "activation state". In the command register read mode CNRR and command register switch mode CNRW, in the data input / output section DQ, the data input / output ports DQ0 to DQ7 are used, and the other data input / output ports DQ8 to DQ15 are set in the high impedance state. At the input / output terminal DQ, the reference symbol "RD" indicates the read data, while the reference symbol "WD" indicates the write data.

Furthermore, a shadow RAM designates an area which is called shadow Table is available, for example to form a Address conversion table for converting virtual Memory addresses in real memory addresses. With that, on a simple way to create a virtual address space.

Various operations are described below.  

[Read mode (block mode, cache mode)]

The read command (block, cache) is set when the N / IO # and D / C # signals are set to "H" and the W / R # signal is set to "L" when the address status signal ADS # drops. As shown in Fig. 134, in this mode of operation, the output data DOUT is stabilized and sequentially output in synchronism with the rise of the master clock signal CLK from the next clock signal cycle. When the BLAST # signal drops to "L", indicating the completion of the block read mode, the data input / output terminal DQ is placed in the high output impedance state from the next clock signal cycle (when the next cycle is an address cycle). In this state, the local memory activation signal LME #, the cache activation signal KEN # and the block completion signal BRDY # are set to "L" at the time of the data output.

The cycle Ta shown in Fig. 134 represents a preparation cycle for the data input / output cycle, and an external address is sampled with the rising edge of the master clock signal CLK in the data hold cycle or the next data cycle.

If the address status signal ADS # is activated and that Memory / IO signal M / IO # is "H", the CDRAM enters the Data cycle Td on. The CDRAM leads in this data cycle Td a data input / output. When the CDRAM in the data cycle Td occurs, the CDRAM maintains this state until the Block completion signal BLAST # is activated. Will the signal BLAST # fed, the signals LME # and BRDY set to "H" and the signal KEN # set to "L" to the CPU display invalid data.

The local memory activation signal LME # and that Block ready signal BRDY # are in a state correspondingly high impedance after having once moved to "H" have been placed while inactivated while the Cache activation signal KEN # directly from the active state  changes in a state corresponding to high impedance. The reason is that the external signal lines for the Local memory activation signal LME # and that Block ready signal BRDY # are pulled to "H" and because as will be described later, the "H" level is necessary by driving a number of signal lines with high Maintain speed. The cache activation signal KEN # becomes high at the "L" level Impedance offset. The determination of a cache Hit / miss hit executed at high speed. Cacheable / non-cacheable data is stored in the CPU with a One cycle delay detected.

The block mode means an operating mode in which successive addresses are addressed one after the other, and when an address is supplied, the Memory cells with the subsequent address positions accessed sequentially.

[Read mode (block mode, non-cache-bar)]

As shown in FIG. 135, in this mode of operation, similar to the operation shown in FIG. 134, the read command is applied in the clock signal cycle 1. However, because the value to be accessed by the external CPU does not exist in the cache, data is read that is transferred from the DRAM field. Therefore, in the TDW cycle, the cache enable signal KEN # rises to "H" to indicate a cache miss and to notify the external CPU that the value should not be cached. Because no valid data is being transmitted at this time, the block ready signal BRDY # also rises to "H". When the required data are all prepared, that is, from the clock signal cycle 3, data are provided in succession as output. At this time, because the output data DOUT represents the value that is not in the cache area, the cache activation signal KEN # falls to "L" from the next cycle, that is, from cycle 4. The block ready signal BRDY # drops to "L" to indicate that valid data is output in block mode from the initial output value.

The cycle Tdw in the clock signal cycle 1 shows one Data waiting cycle, which means that the controller must wait, until all the necessary data is available.

[Read mode (no block mode, cache-bar)]

As shown in Fig. 136, in this mode of operation, no data transfer (to the CPU) is performed in the block mode. Similar to the modes of operation shown in FIGS . 134 and 135, an external address is adopted depending on the drop in the address status signal ADS #. In the next data cycle Td, the block completion signal BLAST # is set to "L". It is therefore shown that a data word has been addressed. The data input / output terminal DQ enters the data cycle Td in the next cycle from the address cycle Ta. In order to indicate at this point in time that the output value Dout represents a valid value, the local memory activation signal LME # and the block ready signal BRDY # both fall to "L" and because of a cache hit the cache activation signal KEN # also falls to " L ".

[Read mode (no block mode, cache-bar, data hold mode)]

As shown in Fig. 137, the read command is supplied in cycle 1 in this mode of operation. Because the read command is applied, 2 valid data are output in the next clock signal cycle (cache hits). Because there is no block access, the block completion signal BLAST # falls to "L" in cycle 2.

The data hold / sleep signal DH # / SP # is used for at least 30 T Cycle periods kept at "L". This turns the data hold mode and the data output in cycle 2 will be DOUT kept in this state. The output data becomes one Clock signal cycle after the data hold / sleep signal DH # / SP #  has reached the inactive state "H" into a state correspondingly high impedance.

[Read mode (no block mode, non-cache-bar)]

As shown in FIG. 138, the read command i 99999 00070 552 001000280000000200012000285919988800040 0002004337740 00004 99880n cycle 1 is supplied in this operating mode. At this time, because access to the non-cacheable area is being performed, memory cell data is output from the main memory, that is, the DRAM array. Therefore, in cycle 2, it enters the data wait cycle Tdw and the output value DQ is an invalid value. Valid data DOUT is output in cycle 3. Because the access takes place in the non-block mode, the block completion signal BLAST # falls to "L" and reading of a data word is completed.

In the next cycle 4, the block completion signal BLAST # is set to "H" raised and a new read command is fed. It will valid values DOUT output in cycle 6. Because also to this When the access is not run in block mode the block completion signal BLAST # is set to "L". With the The local memory access to the respective value Activation signal LME # the level "L", and that Block ready signal BRDY # is only in the cycle in which the valid data is output, to "L". Because of of the non-cacheable data read process, the cache Activation signal KEN # for both output values at level "H".

[Read mode (no block mode, non-cache-bar, hold mode)]

As shown in Fig. 139, a read command is supplied in this mode of operation. In cycle 2, the data waiting cycle Tdw enters the data cycle Td, and valid data from cycle 3 onwards are output. At this time, the block completion signal BLAST # is set to "L" and a data word is output. At the same time, by setting the data hold / sleep mode signal DH # / SP # to "L" for at least 30 T (T is a clock signal cycle), the valid data are continuously output as output values. The cache activation signal KEN # reaches the "H" level when the next clock signal cycle occurs after the valid data has been output.

[Missed reading mode (block mode, cache-bar)]

As shown in Fig. 140, a read command is first applied. In the event of a cache miss, the valid data is not output in the next clock cycle. After a predetermined number of clock signal cycles have elapsed (which is determined by the latency and will be described later), the valid value DOUT is output. When the block termination signal BLAST # falls to "L", the output is put into the high impedance state after the output of the last output value. The cache enable signal KEN # is set to "L" to indicate that there is a cacheable value.

[Miss hit read mode (no block mode, cache bar)]

As shown in Fig. 131, after a lapse of a predetermined period of time, valid DOUT values are output when a read command is issued and the access causes a cache miss. The block complete signal BLAST # assumes the address cycle Ta after a word has been output. Because a cache miss occurs again, the CDRAM enters the data wait cycle Tdw, and after a predetermined period of time, valid data is output.

[Missed reading mode (no block mode, cache-bar, hold mode)]

As shown in Fig. 142, a cacheable read command is first supplied, and if a cache miss occurs, data transfer is performed. In this case, valid data is output after a predetermined period of time has passed. Because the value is cache-bar, the cache activation signal KEN # reaches the level "L" with the transition from the data wait cycle Tdw to the data cycle Td. The block ready signal BRDY # only reaches level "L" when valid data is output. If the signal DH # / SP # is held at "L" for a predetermined period of time of a maximum of 30 T, the CDRAM enters the data hold mode so that the valid data is held. If the signal DH # / SP # is raised to "H", the output value in the next clock signal cycle is brought into a state of correspondingly high output impedance.

[Write mode (block mode)]

As shown in Fig. 143, in the address cycle Ta, the address status signal ADS # is set to "L", and the signals M / IO #, T / C # and W / R # are set to "H", so that the data write mode is set is. It is not important here whether the data write process is cache-bar or non-cache-bar. In both cases, the data is written into the SRAM field or the data transmission circuit, and therefore the valid data DIN is accepted at the same time and written successfully. The cache enable signal KEN # reaches the "L" level, which indicates that the cache data is successfully written in the CPU. If the block termination signal BLAST # reaches the "L" level, the high impedance state is set after the local memory activation signal LME # and the block ready signal BRDY # both rise to "H" with the rise of the next master clock signal CLK. The cache activation signal KEN # is set in a state corresponding to high impedance starting from the state "L". As shown in this figure, data from the address ADD supplied in cycle 1 is successively written to neighboring addresses.

[Write mode (no block mode)]

As shown in Fig. 144, a write command is supplied in cycle 1. Because it is not a block mode, the block completion signal BLAST # drops to "L" when the valid data is taken over in the next clock cycle. As a result, the local memory activation signal LME # and the block ready signal BRDY # both rise to "H", and together with the cache activation signal KEN # they are brought into a state of correspondingly high impedance in the next clock signal cycle.

[Miss Write Mode (Block Mode)]

As shown in Fig. 145, a write command is first applied. However, due to the cache miss, the data write process does not begin until the data of the memory cell of the requested address is cached. After the end of this waiting time, the data are written one after the other. In this case, the time of starting data writing is determined by the latency, which will be described later.

When the block completion signal BLAST # has reached "L" level, the block write process has been completed.

[Miss Write Mode (No Block Mode)]

As shown in Fig. 146, a write command is applied in cycle 1, that is, in address cycle Ta. In the event of a cache miss, after a predetermined period of time has elapsed (in the second clock signal cycle in FIG. 146), the requested memory cell has been set to the selected state, which enables data writing. When the valid value is written, the external control signals LME #, KEN # and BRDY # reach the level "L".

[Initialization when switching on]

As shown in Fig. 147, the reset signal RST # reaches the "L" level when turned on. FIG. 147 shows an operation sequence for setting the CDRAM in the operating state based on the sleep cycle Ts as an example. The sleep cycle Ts represents an operating cycle in which the operation of each circuit except the internal memory cell refresh circuit of the internal voltage generating circuit is stopped. This allows the power consumption to be reduced. The internal master clock signal is not generated and the input signals are not accepted, that is, the input signals are not sampled.

Then an initialization cycle Ti is carried out. In this Initialization cycle, the reset signal RST # on the Active state "L" set, and the signal DH # / SP # goes to "H" set. By holding the signal DH # / SP # on the inactive Level "H" for at least 15 T periods is the CDRAM Initialization carried out. In this initialization process become the values of the command registers described above initialized, the DRAM is initialized and the in the bidirectional transmission circuit held data also initialized. The first access is not allowed up to at least 100T periods from the beginning of the Initialization cycle Ti have passed. This will ensured that the internal circuits in the Return to the initial state.

[CPU reset (CDRAM is not reset)]

As shown in Fig. 148, at the time of the CPU reset, the reset signal RST # is kept in the active state "L" when initialization is performed with a reset of the CPU and without a reset of the CDRAM. In this state, the signal DH # / SP # is kept at "L" in order to safely avoid initialization. When the reset of the CPU is released, the reset signal RST # rises to "H". Then the signal DH # / SP # is raised to the inactive level "H".

At this time, Ti is in the initialization cycle, that is, when the CPU reset is enabled, switching the Signal DH # / SP # locked, that is, it is impossible to do this Set the signal to "H" once, and then set this signal to Lower "L" when the reset signal RST # rises to "H". This prevents the CDRAM from being initialized. Of the Operation when leaving sleep mode is identical to this.  

[Setting the sleep mode]

As shown in FIG. 149, to set the sleep mode, the reset signal RST # and the refresh signal REF # are both set to "H" and the data hold / sleep mode signal DH # / SP # to "L". If the signal DH # / SP # is kept at "L" for at least 32 T periods, the CDRAM enters the sleep mode. In this state, no internal operation is carried out and only the self-refresh operation is active.

[Return from sleep mode]

To exit the sleep mode, the reset signal RST # and the refresh signal REF # are both set to "L" and the signal DH # / SP # which is at "L" is raised to "H", as shown in FIG. 150. Switching the signal DH # / SP # when rising is blocked. This prevents the CDRAM from being initialized. The first access is not allowed until at least 15 T periods have passed since the signals DH # / SP #, RST # and REF # were all set to "H" in order to safely put the internal circuits into an operating state.

[Command register read / write mode]

The operating mode for addressing the command register includes a "command register index set" command CMIS, one "Command register read" command CMRR for reading data from the Command register and a "command register write" command CMR for writing data to the command register. The command index serves to identify the majority of the educated Command register. The read / write of the command register will later along with the structure and operation of the Command register described in detail.

Whether the data or an index is accessed is determined by the address bit A0 shown in Fig. 151. The address status signal ADS # and the signal M / IO # are both set to "L". The W / R # signal determines whether data reading or data writing is to be carried out. If the register index is to be set, the signal W / R # can be "H" or "L".

In the next cycle, the command register enable signal CNE # set to "L". Consequently, access to the Command register executed. After the command register Activation signal CME set to the active state "L" data writing / reading into and out of Command register executed.

FIG. 152 is a table showing the state transition of the different cycles. The cycle Tc1 represents a command cycle 1 which is set when the address status signal ADS # is activated and the signal M / IO is at "L". After this cycle Tc1, the command register activation signal CME # is monitored. As a result of this monitoring, the CDRAM enters the Tc2 cycle when the CME # signal is activated. If the signal CME # is inactive at this point in time, the CDRAM returns to the address cycle Ta.

The second command cycle Tc2 is after that described above executed first command cycle Tc1. In this cycle a Write or read to or from the command register carried out. At this point the command to be addressed is set by the command register index setting command. To the An address is used to set the command register index. The signal conditions for the respective state transitions are as follows.

A: (transition from address cycle Ta to data cycle Td): This Transition is realized when the ADS # signal is active State is, the signal M / IO # is "H", the device in the selected state, the reset signal RST # is inactive State is and the block ready signal BRDY # in the active Condition is.  

B: This state shows a transition from the address cycle Ta to Data waiting cycle Tdw. It is executed when the ADS # signal is in the active state, the signal M / IO # is at "H", which Device in the selected state, the reset signal RST # is inactive and the signal BRDY # is inactive Condition is.

C: This state transition shows the transition from Data wait cycle Tdw for data cycle Td. He is running if the signal DH # is inactive, the reset signal RST # in the inactive state and the signal BRDY # in the active Condition is.

D: This state transition repeats the data cycle Td. This State is realized when the data hold signal DH # in inactive state, the block completion signal BLAST # in the inactive State, the reset signal RST # in the inactive state and that Block ready signal BRDY # is in the active state.

E: The transition from the data cycle Td to the data waiting cycle Tdw executed when the signal DH # is inactive, that Block completion signal BLAST # in the inactive state Reset signal RST # in the inactive state and the signal BRDY # is inactive.

Q: The continuation of the data waiting cycle Tdw is realized when the signals DH #, RST # and BRDY # are all inactive Condition.

G: The return from the data cycle Td to the address cycle Ta becomes executed when the signals DH # and RST # are both inactive Are state and the block completion signal BLAST # the active Condition reached.

H: The transition from the data cycle Tdw to the data holding cycle Tdh is executed when the data hold signal DH # is activated and the reset signal RST # is in the inactive state.  

I: The transition from the data holding cycle Tdh to the data cycle Td executed when the signals DH #, BLAST # and RST # are all in the are inactive and the block ready signal BRDY # im active state.

J: The transition from the data holding cycle Tdh to the data waiting cycle Tdw is executed when the signals DH #, BLAST #, RST # and BRDY # are all inactive.

K: The transition from the data hold cycle Tdh to the address cycle Ta executed when the signals DH #, RST # are both inactive State and the block completion signal BLAST # is activated.

L: The transition from the address cycle Ta to the first command cycle Tc1 is set to the by setting the address status signal ADS # active state, setting the memory / IO signal M / IO # to "L" and by setting the reset signal RST # to performed inactive state.

M: The transition from the first command cycle Tc1 to the second Command cycle Tc2 is set by setting the command register Activation signal CME # to the active state and through Setting the reset signal RST # to the inactive state realized.

N: The transition from the first command cycle Tc1 to the address cycle Ta is carried out by deactivating the signals CME #, RST #.

O: The transition from the second command cycle Tc2 to the address cycle Ta is executed when the reset signal RST # in the inactive State is moved.

P: The address cycle Ta is maintained if that Address status signal ADS # and the reset signal RST # both in the inactive state.

Q: The transition from different cycles to Initialization cycle Ti is set by the Reset signal RST # realized in the active state.  

R: The transition from the initialization cycle Ti to the address cycle Ta is set inactive by setting the reset signal RST # Condition realized.

S: The transition from the address cycle Ta to the sleep cycle Ts becomes realized when the sleep mode signal activates SP # and that Reset signal RST # is deactivated. At this point in time the signal SP # for at least 32 T clock signal periods on the be kept in an active state.

T: The sleep cycle Ts is maintained if that Sleep mode signal SP # is in the active state. The Sleep mode signal SP # is sampled asynchronously to the clock signal.

U: The return from the sleep cycle Ts to the address cycle Ta becomes realized when the sleep mode signal SP # is deactivated. When sleep mode is exited to access allow are at least 15 T periods from when the sleep mode signal SP # is deactivated, required.

[Command register]

Figs. 153A and 153B show truth values of control signals for executing read / write data of the command register and the operations of the respective cycles in a table.

As shown in Fig. 153A, the instruction register access cycle is implemented using the M / IO #, D / C #, W / R # and CME # signals as well as the address signal bit A0. This shows in detail the states of the respective control signals in the signal diagram according to FIG. 151. When the command register is addressed, the signal D / C # is set to "1" and the signal M / IO # is set to "L". If the command register activation signal CME # is set to "L", the signal which was applied in the previous clock signal cycle is accepted and the specified process is carried out. If the address signal bit A0 is 0, the command register index setting cycle CMIS is set. If the address signal bit A0 is 1 and the write / read signal W / R # is at 0, the command register read cycle CMRR is set. If the address signal A0 is 1 and the write / read signal W / R # is "1", the command register write cycle CMRW is set.

If the command register activation signal CME # is "1" the command register does not work at all.

As shown in Fig. 153B, one by one Command register index setting cycle CMIS and the Command register write cycle CMRW executed when data is in the Command registers are to be written, that is, if a predetermined mode should be set. By the Command register index setting cycle CMIS is among the Command register indices 00H to 1CH according to the value to the Input / output terminals DQ0 to DQ7 a command register selected. The indices 00H that follow the command register to 1CH are given in hexadecimal notation.

In the command register write cycle CMRW a Data input / output terminals DQ0 to DQ7 supplied value at selected register index. By repeating the The process described above can write data for each required command registers are executed.

When reading data stored in the command register the instruction register index setting cycle CMIS and the instruction register read cycle CMRR executed. Consequently, be the stored data of the selected command register index read. If all the required contents of the command register should be read, the process described above repeated.

[Command register index 00H]

As shown in Fig. 154, the command register with index 00H is 8 bits wide. Bit 7 is used to set the input terminal or the output terminal of the self-refresh control terminal REF #, which will be described later. If bit 7 is set to 0, the REF # connector works as a signal input connector. If bit 7 is 1, the REF # connector is used as the signal output connector. If this bit 7 is "1", the state of the REF # connector is controlled by a built-in refresh timer. That is, when the REF # terminal acts as an output terminal, a refresh request signal is generated by the internal refresh timer.

Bit 6 is used to cache operation at a To set write hits. The bit sets whether a Write back if a write hit is to be carried out or not.

Bit 5 is used to cache operation during a write To set a miss, namely whether an assignment was made to be or not.

Bits 3 and 4 are used to set the Refresh interval used. The refresh interval is determined according to the frequency of the master clock signal and the Operating mode (sleep mode etc.) to a suitable value set.

Bit 2 is used to set the bus size. The bus size is used to set a shadow RAM address that will be described later. For the bus size are a 32 bit bus and 64-bit bus prepared.

Bits 0 and 1 are used to determine the number of memory Banks used. The addressing architecture is changing according to the number of memory banks.

[Index 01H]

Fig. 155 shows the structure of the command register with the index 01H. in the following description it is assumed that each instruction register is 8 bits wide. Bits 5 through 7 are used to set the frequency of the master clock signal. 33 MHz, 40 MHz, 50 MHz and 66 MHz are available as frequencies.

Bits 2 through 4 are used to set the number of Wait cycles used. You set the waiting time until Output of valid data in the access cycle. If an operation without a waiting cycle, data will be in the next cycle issued, in the access cycle. Bits 2, 3 and 4 represent the Wait state for the block cycle, the write cycle or the Reading cycle. Bits 0 and 1 represent the block length and the Block type. 4 is prepared as standard for the block length. The block type includes an interleave type, in which different data are created alternately, and one sequential type in which the same processing device accesses. The gear type is used if one Image processing device and the CPU in Alternately access image processing system. That will be later describe.

[Indices 02 to 03H]

The structure of the command registers with the indices 02 to 03H is shown in Fig. 156. The command registers with the indices 02H and 03H are used to set the non-cacheable area. The non-cacheable area means a DRAM field area for which the data of the DRAM field are not stored as a cache in the SRAM field, but for which the CPU directly addresses the DRAM field.

Bit 7 of the command register with index 02H is used for setting used, above the CPU address area (0C0000 to 0C7FFh) cache should be bar or non-cache-bar. Bits 4 to 6 of the Command registers with index 02H are used to set the size of the non-cacheable memory block. 64 kbit, 128 kBit, 256 kBit and 512 kBit are available as block sizes.

Bits 0 to 3 of the command register with index 02H and data bits 0 to 7 of the command register with index 03H are used to determine the start address of the non-cacheable memory block. Here, the CDRAM address architecture is changed in accordance with the bus size, which is defined by bit 2 of index 002 according to FIG. 154. The start address of the non-cacheable memory block, which is set by the command register with the indices 02 and 03H, corresponds to the command register address which has been described with respect to bit 2 of the command register with index 00H.

[Indices 04H to 05H]

The structure of the command registers with the indices 04H to 05H is shown in Fig. 157. The command registers of indices 04H and 05H are used to set the non-cacheable area. In the instruction registers with the indices 02H and 03H, the non-cacheable area is defined by the address signal bits A21 to A14 (or A20 to A13). This area can be set as desired in the CPU address area 0C000 to 0C7FFFh. The command registers with the indices 04H and 05H shown in Fig. 157 can set the non-cacheable area in any area. Bits 4 through 6 of the command register with index 04H are used to determine the size of the non-cacheable memory block. Bits 0 to 3 of the command register with index 04H and bits 0 to 7 of index 05H are used to determine the start address of the non-cacheable memory block. In this case, the non-cacheable area defined by the indices 04H and 05H is determined by the address signal bits A14 to A21 (or A13 to A20).

[Indices 06H to 07H]

The structure of the indices 06H to 07H is shown in Fig. 158. As shown in Fig. 158, the command registers with indexes 06H and 07H are used to set the test mode. The supported test mode has a refresh counter test and a test mode in which all address areas are configured as a non-cacheable area. The refresh counter test is a test mode in which it is determined whether or not the counter for generating the refresh address for the refresh operation of the DRAM array operates normally. The address area is made entirely non-cacheable in order to check whether the memory cells of the DRAM field are defective or not. The command register with index 07H is reserved for future functional expansions.

[Indices 10H to 1CH]

The command registers with the indices 10H to 1CH are used to control the read / write of the shadow RAM area as shown in Figs. 159 and 160. The CPU address area 0DC00h to 0FFFFh is prepared as a shadow RAM area. The CPU address area is assigned to the respective index. The activation / deactivation of reading / writing of the respective CPU address area is set by the values of bits W and R in the command register index.

[Read / write latency]

The number of clock cycles required to read or write a valid value after access, that is, into latency, is shown in Fig. 161. The frequency instruction is set by bits 5 through 7 of the index 01H register described above with reference to FIG. 155. The length of the latency is set according to the respective clock frequency. In read mode, data is output in the clock signal cycle after access when there is a hit, and then data is output in succession in each clock signal cycle. In the event of a cache miss, a predetermined number of clock cycles are required before valid data is output.

"Not overwritten" and "overwritten" indicates the deleted or set state of the write indicator bit. This is because it indicates whether the data stored in the SRAM cache is different from the data of the corresponding memory cell of the DRAM field. If the write indicator bit is set, indicating the overwritten state, the contents of the SRAM field must be written back to the DRAM field. In parallel to the external access, data transmission between the SRAM field and the DRAM field is carried out in the CDRAM (see page mode transmission and write-back mode, which have been described above). The number of clock cycles required for this data transfer is given in brackets () in Fig. 161. If misses continue to occur, it is necessary to wait for the previous miss access to complete.

The latency is always the same in write mode regardless of whether access to a cache hit or Cache miss results because the data goes straight to Data transmission gates are written.

[Set / hold time]

In CDRAM, data input / output is synchronized with the master Clock signal CLK executed. Therefore, the response time and the Hold time of the input signal with respect to the rising edge of the master clock signal CLK.

Fig. 162 shows the response time and the hold time of the input signals. Fig. 163 shows the stabilized states of the output signal. The output signal becomes valid after a lapse of a predetermined period from the rise of the master clock signal CLK, and becomes invalid after a predetermined period of time from the rise of the master clock signal CLK.

[Output circuit]

As shown in Fig. 164, a plurality of CDRAMs are generally used to form a memory system. As shown in Fig. 164, CDRAMs CR00 to CR33 are arranged in 4 rows _* 4 columns that form 4 banks. Bank # 0 is formed by CDRAMs CR00 to CR03, bank # 1 by CDRAMs CR10 to CR13, bank # 2 by CDRAMs CR20 to CR23 and bank # 3 by CDRAMs CR30 to CR33. Each of the CDRAMs has an 8-bit bus 7501 ( 7501 generally denotes the reference numerals 7501 a to 7501 b).

The 8 bit data buses 7501 a to 7501 d are connected to 32 bit data bus 7501 e. The CDRAMs are each connected to a control bus 7500 ( 7500 generally denotes the reference numerals 7500 a to 7500 e). The control buses 7500 a to 7500 d are connected to a main control bus 7500 e.

As described above, the CDRAM generates itself Control signals. That means it creates that Block ready signal BRDY #, the cache activation signal KEN #, the local memory activation signal LME # and that Refresh determination signal REF # when this is Output signal is configured. The sections to spend these signals are structured so that they correspond to a OR logic are connected to the signal lines. The Block ready signal BRDY # is used as an example. This signal becomes active at "L" when the CPU is above it is informed that a valid value is output so that the CPU and the applied signal processed and the applied Data in a cache section in the CPU corresponding to that Active state ("L" level) of the cache activation signal KEN # saves.

If a CMOS inverter is used in the output section, a transistor switches through in such a case, so that a current constantly flows through the signal line. This increases the power consumption of the CDRAM. If a 3-state buffer with a clocked inverter is used for the signal output section, clock signal control becomes necessary. This leads to a complicated circuit structure and an enlargement of the device. Therefore, an open drain structure as shown in Fig. 165A is used as an output section for generating control signals. The signal line is raised to the supply potential Vcc by a pull-up resistor R. As shown in FIG. 165A, output transistors OTA and OTB are connected to a signal line 9010 in parallel with each other. The output transistors OTA and OTB turn on depending on the output designation signals Φ1 and Φ2 in the CDRAMs CRA and CRB, respectively, to discharge the signal line 9010 . A pull-up resistor R is formed on the signal line 9010 . It is assumed that the CDRAMs CRA and CRB do not output signals at the same time. The transistors OTA and OTB do not switch through simultaneously. These memories belong to different banks of the structure shown in Fig. 164. The operation of the circuit shown in FIG. 165A will be described with reference to the signal diagram in FIG. 165B.

It is assumed that a read request is supplied to the CDRAM CRA and valid data is output. In this case the signal Φ1 first rises to "H". This makes the output transistor OTA conductive. As a result, the potential SigA of the signal line 9010 , which has been raised to the supply potential Vcc by the pull-up resistor R, is rapidly discharged via the output transistor OTA. When the data output operation is completed, the signal Φ1 drops to "L". As a result, the signal line 9010 is raised to the level of the supply potential Vcc by the pull-up resistor R. The value of the resistor R is relatively high and its power consumption is therefore low.

The CDRAM CRB is then accessed and the signal Φ rises to "H". As a result, the output transistor OTB turns on to discharge the signal line 9010 to the ground potential level. After the completion of the predetermined processing, the signal Φ2 falls to "L", and the signal line 9010 is raised again to the level of the supply potential Vcc.

By using the output section described above the necessary signals, for example the BRDY # signal a simple circuit structure can be transferred to the CPU.

Although the signal line 9010 is charged by the pull-up resistor R, there is a stray capacitance C on the signal line 9010 . Therefore, a time period determined by the RC time constant is necessary until the signal SigA on the signal line 9010 rises from "L" to "H".

The CPU determines whether the next access is possible and whether valid data corresponding to the state of the signal SigA is present on the signal line 9010 . If the rise in signal SigA on signal line 9010 is moderate and if the rising edge of master clock signal CLK is found to be "L", incorrect data may be accepted. In this case, because the CPU determines whether the next access is possible according to the state of the SigA signal, it becomes impossible to address the memory in another bank by switching the banks. This prevents quick operation. If the pull-up resistance R is made smaller, the signal line 9010 can be charged at high speed. In this case, however, a large current flows through the signal line 9010 . This increases the power consumption of the storage system.

Fig. 166 shows a CDRAM structure with an improved output section according to the present invention. As shown in FIG. 166, the output section of the CDRAM has an output transistor 9011 for discharging the signal line 9010 and a transistor 9012 for charging the signal line 9010 for a predetermined period of time. The output section of the CDRAM CRA has an output transistor 9011 a, which is made conductive in accordance with a signal Φ1D, and a p-channel MOS transistor 9012 a, which is rendered conductive in response to a signal Φ1L. The signal Φ1L is held at "L" for a predetermined period of time and only in response to the fall of the signal Φ1B. The CDRAM CRB similarly has an output transistor 9011 b, which is made conductive depending on a signal Φ2D, for discharging the signal line 9010 and a p-channel MOS transistor 9012 b for charging the signal line 9010 for a predetermined period of time and only in Dependence on a signal Φ2L. The master clock signal CLK is supplied to the CDRAMs CRA and CRB via a signal line 9009 . The operation of the output section of FIG. 166 will be described with reference to the signal diagram in FIG. 167.

First, it is assumed that the CDRAM CRA is put into the operating state and executes predetermined processing. At this time, predetermined processing (indicated as in the figure) is carried out from the rising edge of the master clock signal CLK, the signal Φ1D rises to "H" after a lapse of a predetermined period of time to discharge the signal line 9010 to the ground potential level . After a predetermined period of time has elapsed (the length of this period of time changes depending on the data holding time, the block length and similar sizes), the signal Φ1D then falls to "L", the rising edge of the master clock signal CLK being used as a trigger. The drop in the signal Φ1D is used as a trigger and the signal Φ1L drops to "L" and is held for a predetermined period of time. Consequently, transistor 9011 a blocks and transistor 9012 a switches on. The signal line 9010 is thus charged at high speed via the transistor 9012 a. After a predetermined period of time has elapsed , the transistor 9012 a is blocked.

At this time, the output signal does not change for a predetermined period of time from the rising edge of the master clock signal CLK, as shown in FIG. 162. More specifically, the pulldown transistor 9011 switches from the off state to the on state after a predetermined period of time has passed since the rising edge of the master clock signal CLK. Therefore, the transistor 9011 b does not turn on during this time even if the transistor 9012 a is turned on. Therefore, no signal collision occurs, no current flows from transistor 9012 a to transistor 9011 b, and signal line 9010 is charged at high speed. Because the signal Φ1L is generated using the signal Φ1D as a trigger, the transistors 9011 a and 9012 a do not switch on simultaneously. Therefore, no forward current flows in the CDRAM CRA. Because the transistor 9012 a changes to the blocking state after a predetermined period of time has elapsed , its power consumption is quite low.

The CDRAM CRB is then addressed by the external CPU in accordance with the state of the signal Sig on the signal line 9010 , the transistor 9011 b switches through in a similar manner and discharges the signal line 9010 . Then the transistor 9011 b is blocked. Then the signal Φ2L is generated, the transistor 9012 b turns on and discharges the signal line 9012 for a predetermined period of time at high speed.

Each CDRAM operates using the rising edge of the master clock signal as a trigger. Parameters of various signals are set with the rising edge of the master clock signal CLK as a reference. Therefore, the period of time when pull-up transistors 9012 a and 9012 b are kept in the conductive state can be set precisely.

Fig. 168 shows a circuit structure for generating control signals ΦD and ΦL. As shown in Fig. 168, the control signal generation system includes a processing circuit 9020 for generating an adjustment signal after the lapse of a predetermined period of time according to an applied command, an adjustment / reset flip-flop 9021 which is set in response to the adjustment signal from the processing circuit 9020 and is reset with the rising edge of the clock signal CLK, an inverter circuit 9022 to which the output signal of the flip-flop 9021 inverts and a single pulse generation circuit 9023 , which depends on the output signal from the inverter circuit 9022 , for generating a single pulse with a predetermined pulse width. The control signal ΦD is generated by the set / reset flip-flop 9021 . And this signal turns on transistor 9011 to discharge the output line. The single pulse ΦL from the single pulse generation circuit 9023 turns on the transistor 9012 to charge the output signal line .

The signal ΦD with the rising edge is shown at in FIG. 168 reset the master clock signal CLK. Depending on the transition of the signal ΦD to the reset state, a single pulse ΦL is generated for a predetermined period of time. The processing circuit 9020 changes its operation in accordance with the signal output from the output section shown in FIG. 166. The set / reset flip-flop 9021 is reset with every rising edge of the master clock signal CLK. However, a circuit structure can also be used in which a reset signal is generated by another processing circuit after completion of processing depending on the rising edge of the master clock signal CLK. The adjustability of the adjust / reset flip-flop 9021 is greater than the reset ability .

Fig. 169 shows another structure for the control signal generation system. As shown in Fig. 169, the control signal generation system includes a flip-flop 9025 which receives a signal from the inverter circuit 9022 shown in Fig. 168 at its set input and the master clock signal CLK at its reset input. The flip-flop 9025 is reset depending on the drop in the master clock signal CLK. The control signal ΦL is generated at its complementary output / Q. The operation of the circuit shown in FIG. 169 will be described with reference to the signal diagram in FIG. 170.

If the signal ΦD is at "H", the output signal of the inverter circuit 9022 is at "L". in this state the signal ΦL is kept in the reset state. In other words, it is kept at a "H" level. If the signal ΦD falls to "L", the output signal of the inverter circuit 9022 rises and the flip-flop 9025 is set. Depending on this, the signal ΦL is set and reaches the level "L". When the master clock signal CLK drops, the flip-flop 9025 is then reset and the signal ΦL rises to "H". An edge-triggered flip-flop can be used as the flip-flop 9025 , which is set depending on the rise in the setting input signal and reset depending on the fall in the master clock signal. The resilience of the flip-flop 9025 can be greater than the adjustability. If this is the case, the flip-flop 9025 is reset depending on the drop in the master clock signal CLK even if the signal supplied to its setting input S is in the active state "H".

As described above, when the output signal of the circuit connected in the form of an OR logic to the signal line 9010 is a signal that is output in synchronism with the master clock signal CLK, the signal line can be charged in accordance with the clock signal for synchronization. Therefore, the signal line can be raised to the pull-up potential with high speed and low power consumption.

In the structure described above, the signal line 9010 is raised to the level of the supply potential Vcc. The signal line 9010 can be pulled down to the ground potential level. In this case, the structure is such that a signal line connected in the form of an OR logic is charged to the supply potential by the driver transistor of the output stage, and the signal line is discharged to the ground potential level via the driver transistor in the output stage. This is because the polarity of the transistors in the example described above are changed.

[Procedure for Setting Test Modes]

As shown in Fig. 158, a test can be performed using the command registers with the indexes 06h and 07h by setting the test mode. For example, the refresh counter can be checked and the DRAM field can be addressed directly. In this case, there are several test modes that the user does not need. For example, a reference voltage (Vcc / 2) is generally applied to a cell plate, which is an electrode of a storage capacitor of a dynamic memory cell, and it is necessary to ensure the breakdown voltage of the storage capacitor by measuring its breakdown property by varying the cell plate voltage. In this case, an acceleration test is performed with the cell plate voltage raised above the generally applied reference voltage (Vcc / 2). It is desirable that the device not enter such a test mode, even if a user operates the memory with incorrect timing. A structure for such an operation is described.

Fig. 171 shows a method for setting a test mode in the CDRAM according to the present invention. As shown in Fig. 171, the test mode is set when the command register setting cycle (Tc1 or Tc2) is repeated twice in succession. At this time, the command register activation signal CME # is set to the inactive state "H" in the second cycle. In this case, the command register is not accessed. The address applied at this time, that is, the address bit supplied at the time the test mode is set, is used as a signal for specifying the test mode. This makes it possible to set a desired test mode among a plurality of test modes and it becomes possible to activate only one specific test mode.

To exit test mode, the same command register Setting command created again. In this case too first command cycle Tc1 or the second command cycle Tc2 executed. The signal CME # is kept at "H".

As described above, the test mode is only taken according to the signal timing, and a special one Test mode is set according to the address key (one Combination of the predetermined address signal bits) called. Therefore can be compared to a method of calling a Test mode by applying a signal that over the Supply voltage Vcc is raised, the test mode easier and be called with greater reliability. Furthermore, the test mode can be used easily after the Device has been formed on a chip.

Because the test mode according to the command register Setting mode is taken, other commands can be desired  than that for the instruction register setting operation during the Test operation can be created so that the CDRAM a desired Circuit operation.

In a semiconductor memory device with an instruction register, the method for entering the test mode can use the instruction register setting cycle. For example, in CDRAM, which is the truth table of signals as shown in Fig. 94, the command register can be set by using the signals RAS #, CAS # and DTD #. In this case, the instruction for setting the instruction register is applied with the rising edge of the external clock signal K, as shown in Fig. 172. In other words, the external control signals ext.CS #, ext.RAS #, ext.CAS # and ext.DTD # are also set to "L". This command is applied sequentially for two clock signal cycles. The test mode is entered by the command register setting cycle of the second clock signal, and the test mode executed at this time is set by the external address signal ext.Ad. Instead of a structure in which a test mode is selected from a plurality of test modes, a structure can be used in which only a specific test mode is activated in accordance with a predetermined address key. A structure can be used in which the remaining test modes are executed in accordance with the test mode set in the command register.

According to the specification of the product in general blocked the entry of other commands for one to three cycles, when an instruction register setting instruction is supplied. Because the Test mode is taken at such an operating time, which is locked according to the specification can be a incorrect call of the test, the incorrect operation of the CDRAM can be prevented.

Fig. 173 shows an example of the structure of a test mode setting circuit. As shown in Fig. 173, the test mode setting command detection circuit 9030 which receives an external control signal, for detecting the entry of a command register set command, a counter 9032 for counting the detection signals from the command detection circuit 9030, a Adreßschlüssel- detection circuit 9035, which is dependent on a dual counter signal from the counter 9032, mismatch to detect for comparing the fed at this time the address signal with a predetermined key to a match /, and a test circuit 9034, in response to a coincidence detection signal from the Adreßschlüssel- detection circuit 9035 is activated to set a desired test mode to. The test circuit 9034 is deactivated in response to a triple counter signal from the counter 9034 . The command register 9033 is activated in response to a command detection signal from the command detection circuit 9030 . In this structure according to the third embodiment, access to the command register 9033 is only permitted when the command activation signal CME # is activated.

If the instruction detecting signal is applied twice in successive clock cycles, the counter 9032 generates a count-up signal and supplies it to the detection circuit 9035 to Adreßschlüssel-. After counting up, it deactivates test circuit 9034 depending on the next command detection signal applied. The test circuit 9034 enables predetermined test operation depending on the key detection signal from the address key detection circuit 9035 . For example, when a cell plate test is to be performed, a reference voltage source connected to the cell plate, that is, a node connected to the reference potential generating circuit that generates the potential Vcc / 2, is connected to an external supply terminal. This enables the cell plate voltage to be raised in a simple manner. A structure can be used in which the connection of the node for the test is switched to an internal voltage generation circuit and the internal voltage generation circuit generates a predetermined voltage under the control of the test circuit 9034 for the test. The test circuit 9034 may include such an internal voltage generation circuit for the test.

Fig. 174 shows another structure for the test mode setting circuit. As shown in Fig. 174, a counter 9042 detects the instruction register setting instruction from an instruction detection circuit 9040 and counts the number thereof . A test mode setting circuit 9044 is activated in response to a two count-up signal from the counter 9042 and sets a predetermined test mode according to the address supplied at that time. More specifically, the test mode setting circuit 9044 has a function of decoding the address signal and setting a predetermined test mode. The circuit structure of the test circuit 9042 is designed to implement the test mode set by the test mode setting circuit 9044 . The test circuit 9044 is similar to the test circuit 9034 shown in Fig. 173rd

When in Figs. 173 and 174 shown structure, a structure may be used wherein a test mode designating signal of a predetermined instruction register read twice the count-up signal from the counter 9032 corresponding to 9033, and the test circuit is supplied. In this case, a predetermined test mode is previously set in the command register 9033 .

Fig. 175 shows an example of the structure of the counter shown in Figs. 173 and 174. As shown in Fig. 175, the counter 9032 ( 9042 ) has a single pulse generation circuit 9050 , which is dependent on the command detection signal Φ from the command detection circuit , for generating a pulse having a predetermined pulse width (2 clock signal cycles), a counter circuit 9054 for counting the Command detection signal Φ, a set / reset flip-flop 9056 , which receives the double count-up signal C2 from the counter circuit 9054 at its set input S and the triple count-up signal C3 from the counter circuit 9054 at its reset input R, and a gate circuit 9052 which receives an output signal from the flip-flop 9056 and receives an output signal from the single pulse generation circuit 9050 .

For example, gate circuit 9052 is an OR gate. If the output signal from the gate circuit 9052 is "H", the counter circuit 9054 is put into the operating state. The operation of the counter circuit shown in FIG. 175 will be described with reference to the signal diagram of FIG. 176.

If a command register setting command is supplied as the master clock signal CLK rises, the command detection signal Φ rises. Depending on the command detection signal Φ, the single pulse generation circuit 9050 generates a single pulse and the output signal of the gate 9052 rises to "H". As a result, the counter circuit 9054 is activated and counts the command detection signal Φ supplied at this time. The count value thus reaches the value 1.

The output signal of the single pulse generation circuit 9052 has a pulse width of 2 clock signal periods (this is indicated by the broken line in Fig. 176). If a command detection signal Φ is subsequently supplied during this period, the counter circuit 9054 generates the double increment signal C2. This sets the flip-flop 9056 and its output signal Q rises to "H". Depending on the rise of the output signal Q of the flip-flop 9056 , the pulse generation of the single pulse generation circuit 9050 is blocked. Namely, the output signal of the single pulse generation circuit 9050 drops to "L". The gate 9052 continuously outputs a "H" level signal corresponding to the Q output of the flip-flop 9056 . The counter circuit 9054 is thus kept in the active state.

When the third command detection signal Φ is applied, the single pulse generation circuit 9050 does not generate a pulse. In response to the third command detection signal Φ, the counter circuit 9054 raises the double increment signal C3 to "H". As a result, the output signal Q of the flip-flop 9056 drops to "L" and the counter circuit 9054 is reset. Depending on the drop in the Q output signal of the flip-flop 9056 , the single pulse generation circuit 9050 is activated again.

If the command detection signal Φ is not applied twice in succession, the output signal of the single pulse generation circuit 9050 drops depending on the second clock signal from the first application of the command detection signal Φ, as shown by the broken line in FIG. 176. In response, the counter value of the counter circuit 9054 is reset. With this, a successive double supply of the command detection signal, that is, the successive double application of the command register setting command can be reliably detected.

[Refresh control]

As shown in Fig. 154, the seventh bit of the command register with index 00h can set the REF # port as an input port or an output port. The input / output structure of the REF # connector will now be described.

It is assumed that the CDRAM is arranged in n banks, as shown in Fig. 177. As shown in Fig. 177, banks 0 through bank n each have a 4-byte word structure with bytes 0 through 3, and in each bank the REF # terminals of the CDRAMs are connected together. In each bank, the REF # terminal of a CDRAM is configured as an output terminal and the REF # terminals of the remaining CDRAMs are set as input terminals. As a result, the refresh can be carried out under the control of a CDRAM in each bank.

Fig. 178 shows a structure for the section related to the refresh of the CDRAM. For an easier understanding of the refresh process, an example is described in Fig. 178 in which memory access is determined by the row address strobe signal ext.RAS # which is a commonly used external control signal in a standard DRAM. The CDRAM according to the third embodiment has a controller and performs the sampling of external control signals in accordance with an address status signal ADS #. The internal RAS signal is generated as required according to the result of the scan. The structure will be briefly described later. The following simply shows a state in which RAS buffer 6030 generates an internal RAS signal ΦRAS # corresponding to the external row address strobe signal ext.RAS # as a memory access signal (this applies to the first to third embodiments). When the internal row address strobe signal (internal RAS signal) ΦRAS # is at the active level "L", the DRAM field is active.

As shown in Fig. 178, the refresh control system, a master circuit 8010 for generating a refresh request, a master / slave switch 8040 corresponding to transmit the refresh request from the master circuit 8010 to a refresh terminal 8000 a master / slave-setting indicator M / S # from the command register, and a slave circuit 8020 , which is dependent on the refresh request to the port 8000 , to perform the refresh operation.

The master circuit 8010 has a self-refresh timer 8012 for generating the refresh request ΦREFs # at predetermined time intervals and a first arbitration means 8014 for arbitrating the refresh request ΦREFs # from the self-refresh timer 8012 and the internal RAS signal ΦRAS # from the RAS buffer 8030 . If the internal RAS signal ΦRAS # is active and a refresh request ΦREFs # is applied, the first arbitration means 8014 issues a refresh request ΦREF # if the internal RAS signal ΦRAS is deactivated. At this time, as will be described in detail later, the first arbitration means 8014 issues a refresh request ΦREFs # in synchronism with the master clock signal CLK.

The master / slave switch 8040 transmits the refresh request from the first arbitrator 8014 to the refresh port 8000 when the master / slave indicator M / S # indicates the master status. When the slave state is set, the 8040 switch is placed in a high output impedance state. This blocks the transmission of the output signal from the first arbitration means 8014 .

The slave circuit 8020 has a second arbitration means 8022 for performing an arbitration of the refresh request that is supplied from the connector 8000 (from outside or from the same chip) and a precharge completion signal ΦPR, and a self- refresh control circuit 8024 that is from the refresh request ΦREFa # dated Arbitration means 8022 is dependent on performing the necessary control for the refresh. The self-refresh control circuit 8024 has an address counter for specifying the line to be refreshed. When the refresh request ΦREFa # is applied, it performs the row selection process of the DRAM and a sense amplifier activation using the refresh address from the refresh address counter as the row address. The self- refresh control circuit 8024 generates the internal RAS ΦRASa #, which has a predetermined width (the width includes at least the time required to complete the row selection and the detection process in the DRAM field), depending on the refresh request signal ΦREFa #. The RAS buffer 8030 performs a logic operation with the external row address strobe signal ext.RAS # and the internal RAS signal ΦRASa # and generates the internal RAS signal ΦRAS #.

The second arbitration means 8022 transmits the refresh request internally or from the off-chip via the port 8000 to the self-refresh control circuit when the precharge completion signal ΦPR of the RAS buffer 8030 is activated, indicating that the precharge of the DRAM field is complete. The second arbitration means 8022 supplies a mask signal ΦMask # to the RAS buffer 8030 simultaneously with the transmission of the refresh request ΦREFa # to the self- refresh control circuit 8024 .

In accordance with the mask signal ΦMask # generated by the second arbitration means 8022 , the RAS buffer 8030 masks the external row address scan signal ext.RAS # and blocks external accesses. With reference to the signal diagrams of Fig. 179 and 180, the operation will now be described, the master circuit 8010 and the slave circuit 8020, shown in FIG. 178.

Referring to FIG. 179, the operation is the master circuit 8010 described first. If the internal RAS signal ΦRAS # is "L" in the active state, the DRAM field is accessed from the outside and the DRAM field is active. If a refresh request ΦREFs # is applied by the self-refresh timer 8012 , the first arbitration means 8014 transmits the refresh request ΦREFs # in synchronism with the master clock signal CLK when the signal ΦRAS # is at the inactive level "H". The changeover switch 8040 has been put into the operating state in accordance with the indicator M / S #, so that it transmits the refresh request from the first arbitration means 8014 to the connection 8000 and to the slave circuit 8020 . Thus, the refresh request for the other CDRAM is issued from the 8000 connector.

At this time, the first arbitration means 8014 delivers an external refresh request depending on the (in synchronism with) the increase in the external master clock signal ext.CLK. With the rise of the master clock signal CLK, which is used as a trigger, the external refresh request REF # returns to the inactive state and the first arbitration means 8014 deactivates the internal refresh request ΦREFs #. The self- refresh timer 8012 is thus reset again and a new counting process begins. With this structure, the refresh request can always be generated synchronously with the external master clock signal CLK. In the master chip (the chip in which indicator M / S # sets port 8000 as the output port), the second arbiter 8022 arbitrates the refresh request from the switch 8040 . The second arbitration means 8020 generates a mask signal ΦMask # depending on the refresh request that is applied by the switch 8040 . The first arbitration means 8014 generates the refresh request in synchronism with the master clock signal CLK after the internal RAS signal ΦRAS # is deactivated. The masking signal ΦMask # therefore has the function of masking a newly created access request.

When a refresh request is supplied, the second arbitration means 8022 generates a refresh request ΦREFa # when the precharge completion signal ΦPR from the RAS buffer 8030 is deactivated and the precharge is complete. The self-refresh control circuit 8024 executes the refresh operation in accordance with the refresh request ΦREFa #. More specifically, the count from the address counter is selected by a multiplexer and applied to the DRAM row decoder so that the DRAM row decoder is activated and the sense amplifier is driven. The internal RAS signal ΦRAS, which is generated at this time, has a predetermined width. That is, the self-refresh control circuit generates a single pulse signal having a predetermined width as an internal RAS signal ASRASa # depending on the refresh request ΦREFa #.

When a predetermined period of time has passed, the Refresh process completed and the mask signal ΦMask # is deactivated. This allows the acceptance of an external one Access.

In the slave chip (a chip in which the port 8000 is set as an input port by the indicator M / S #), the refresh operation is carried out in accordance with the refresh request externally applied through the port 8000 . Therefore, the refresh operation from the slave chip can be performed synchronously and in accordance with the refresh request from the master chip. At this time, because the refresh request is supplied in synchronism with the master clock signal, a plurality of CDRAMs are simultaneously subjected to the refresh process without being affected by timing fluctuations.

Because first and second arbitration circuits 8014 and 8022 are formed, the refresh operation can be performed with arbitrated activation of the DRAM field. The self-refresh can thus be carried out even in the normal operating mode. The structure of various sections is described below.

Fig. 181 shows a circuit structure for generating the precharge completion signal ΦPR #. This circuitry is contained in RAS buffer 8030 shown in FIG. 178. As shown in Fig. 181, the precharge completion signal generation system has a delay circuit 9060 which delays the rise of the internal RAS signal ΦRAS # by a predetermined period of time. In the structure shown in Fig. 181, the precharge completion signal ΦPR rises to "H" after a predetermined period from when the internal RAS signal ΦRAS # rises to the inactive level "H". This indicates the completion of the precharge, as shown in Fig. 182. The precharge completion signal ΦPR is set to the inactive level "L" at approximately the same time that the internal RAS signal ΦRAS # changes to the active state "L".

Fig. 183 shows another structure of the precharge completion signal generation system. As shown in Fig. 183, a counter 9064 is activated depending on the rise of the internal RAS signal ΦRAS #, counts the master clock signal CLK for a predetermined period of time and raises the precharge completion signal ΦPR to the active state "H", which indicates the completion of the summons. In this case, the precharge completion signal can be generated in the form of a single pulse. A signal obtained by AND operation of the internal RAS signal ΦRAS # and the precharge completion signal ΦPR can be generated as the precharge completion determination signal. If this AND operation is to be used, the precharge completion signal ΦPR is held in the inactive state "L" when the internal RAS signal #RAS # is in the active level "L", that is, when the DRAM array is in the active state is.

The delay time provided by the rise delay circuit 9060 and counter 9064 can be as long as the RAS precharge time.

Fig. 184 shows an example of the structure of the first arbitration means of Fig. 178. As shown in Fig. 184, the first arbitration means 8014 has an inverter circuit 8068 for inverting the refresh request (ext.REF #) from the switch 8040 , a set / reset -Flipflop 8062 , which receives the output signal from the inverter circuit 8061 at its setting input S and the output signal of the inverter circuit 8068 at its reset input RD, a 2-input AND circuit 8063 which outputs the output signal Q from the flip-flop 8062 and that receives internal RAS signal ΦRAS #, a latch circuit 8064 , which takes over and locks the output signal from the AND circuit 8063 depending on the rise of the master clock signal CLK, and a flip-flop 8066 , which has the output signal Q at its setting input S. Latch circuit 8064 receives on. The external refresh request ext.REF # is generated by the flip-flop 8066 (it is applied to the refresh terminal 8000 via the switch 8040 ).

The flip-flop 8066 is reset by an output signal of the gate circuit 8067 , which receives the master clock signal CLK at its true input and the output signal / Q of the flip-flop 8066 at its false input. More specifically, the flip-flop 8066 is reset with the rise of the next clock signal CLK after the external refresh request ext.REF # is generated (when it reaches the "L" level), and the external refresh request ext.REF # is reset. The operation will now be briefly described.

When the refresh request ΦREFs # is applied by the self-refresh timer 8012 (see Fig. 178), the flip-flop 8062 is set (at this time, the external refresh request ext.REF # is still inactive level "H"). If the internal RAS signal ΦRAS # reaches the inactive state "H", the gate circuit 8063 passes the output signal Q of the flip-flop 8062 . The latch circuit 8064 takes over the output signal from the gate circuit 8063 in synchronization with the rise of the master clock signal CLK and locks it. The refresh request is therefore accepted and latched by the latch circuit 8064 in synchronism with the rise of the next clock signal CLK when the internal RAS signal ΦRAS # is deactivated. The output signal Q of the latch circuit 8064 thus rises to "H", the flip-flop 8066 is set and its output signal / Q reaches the level "L". This creates the refresh request. If the refresh request ext.REF # assumes the active state "L", the gate circuit 8067 resets the flip-flop 8066 depending on the rise of the next master clock signal CLK. This resets the output signal / Q of the 8066 flip-flop from "L" to "H".

Due to the structure described above, the external refresh request is only generated when the internal RAS signal ΦRAS # is inactive. When the external refresh request ext.REF # reaches the active state, the flip-flop 8062 is reset by the inverter circuit 8068 and the output signal Q of the flip-flop 8062 drops to "L". Then the output signal Q of the latch circuit 8064 reaches the "L" level. The 8066 flip-flop is not set at all and is held in the reset state.

The refresh request ΦREFs #, which is issued by the self-refresh timer 8012 , represents a single pulse with a predetermined width. A reset is not necessary.

FIG. 185 shows an example of the structure of the second arbitration means shown in FIG. 178. As shown in FIG. 185, the second arbitration means 8022 has a latch circuit 8070 , which accepts and latches the external refresh request ext.REF # in synchronism with the rise of the master clock signal CLK, and a flip-flop 8072 , which is dependent on the complementary output signal / Q of latch 8070 is set to. The mask signal ΦMask # is emitted from the complementary output / Q of the flip-flop 8072 .

The second arbitration means 8022 further comprises a gate circuit 8074 , which receives the mask signal ΦMask # and the precharge completion signal ΦPR, and a counter 8076 , which is activated in response to the refresh request signal ΦREFa # from the gate circuit 8074 , for counting a predetermined number of the master clock signal CLK on. After a predetermined number of master clock signals CLK have been counted, the counter 8076 resets the flip-flop 8072 . The counter 8076 sets the time period of the refresh operation. The operation will now be briefly described.

When the external refresh request ext.REF # drops to the active state "L", the latch circuit 8070 takes over the external refresh request ext.REF # in synchronization with the rise of the clock signal CLK and locks it. As a result, the complementary output signal / Q of the latch circuit 8070 rises to "H". This will set the 8072 flip-flop. The masking signal ΦMask # thus changes from the complementary output signal / q of the flip-flop 8072 to the active state "L".

After the mask signal ΦMask # has reached the active state "L", the gate circuit 8074 generates a refresh request ΦREFa # when the precharge completion signal ΦPR has reached the active state "H". The counter 8076 counts a predetermined number of clock signals CLK depending on the refresh request REFa #. After counting the predetermined number, it resets flip-flop 8072 . As a result, the mask signal ΦMask # is reset to "H", the output signal of the gate circuit 8074 also reaches the level "H" and the refresh request ΦREFa # assumes the inactive state.

In the structure shown in Fig. 185, the refresh request ΦREFa # generated by the first arbitration means is at the active level "L" during the refresh operation. A structure can be used in which it is generated in the form of a single pulse. More specifically, a structure can be used in which a single pulse generation circuit is formed in the output portion of the gate circuit 8074 and the counter 8076 is activated in response to the output signal of the single pulse generation circuit. Although not shown, the count of counter 8076 is reset to the initial value when a predetermined count has been reached.

Fig. 186 shows an example of the special structure of the RAS buffer and the refresh control circuit. As shown in Fig. 186, 8030, the RAS buffer, a gate circuit 8080 which receives the external RAS signal ext.RAS # and the mask signal ΦMask #, and a NOR circuit 8082, which at the first input the output signal of the gate circuit 8080 receives on. The NOR circuit 8082 receives at its second input the internal RAS signal ΦRASa # which is generated by the refresh control circuit 8024 .

The refresh control circuit 8024 has a refresh detection circuit 8090 for detecting a refresh in response to the refresh request signal ΦREFa #, a pulse generation circuit 8094 which is dependent on the refresh detection signal ΦREFa # from the refresh detection circuit 8090 , for generating a pulse signal with a predetermined refresh signal ΦRASrez #, (width operation) 8092 , which depends on the rise (deactivation) of the internal RAS signal ΦRASa # from the pulse generation circuit 8094 , to increment the count by 1, and a multiplexer 8096 to select either the count of the address counter 8092 or an external address in accordance with the internal RAS signal ΦRASa # from the pulse generating circuit 8094 .

The output signal of the 8096 multiplexer is fed to the DRAM row decoder. At this point, the output of the 8096 multiplexer can be fed to the DRAM row decoder via an address buffer. The external RAS signal generated by gate circuit 8082 is applied to a DRAM-RAS driver circuit 8096 . The DRAM-RAS driver circuit 8096 carries out activation of the DRAM row decoder, selection of the word lines, activation of the sense amplifiers, etc.

In the structure shown in FIG. 186, it is not necessary to form the refresh detection circuit and the pulse generation circuit 8094 when the refresh request signal ΦREFa # is kept active during the refresh operation time, as shown in FIG. 185. The refresh detection circuit 8090 and the pulse generation circuit 8094 are necessary when the refresh request signal ΦREFa # is generated in the form of a single pulse.

The address counter 8092 may be structured so that the count value is put into an output activation state by the refresh detection circuit 8090 in response to the refresh detection signal RA.

The circuit structure shown in FIG. 186 is formed in the DRAM control and cache / refresh control section 7026 in the CDRAM according to the third embodiment, which is shown in FIG. 131. The control section 7026 does not receive the external RAS signal ext.RAS # directly. In this case, a structure can be used in which a circuit for detecting the return to the address cycle Ta is formed in the control section 7026 and the arbitration is performed depending on the detection of the return to the address cycle Ta instead of the external RAS # signal.

The control section 7026 shown in FIG. 131 has the structure of the external control device 3100 shown in FIG. 111. Therefore, because access to the DRAM array is being performed, an access control signal is generated by controller 3108 (see FIG. 111) to the DRAM array. Therefore, the structure is such that the internal RAS signal applied by this control section 7026 is supplied to the gate circuit 8080 of Fig. 186 instead of the external control signal.

In the structures according to the first and second embodiments, where different operations according to the combination of States of external signals when the clock signal rises will be set, an active command detection signal instead of the external address scanning signal ext.RAS # supplied. The external control signals used at this time differ depending on the control signals that can be used in the respective embodiments.

In the third embodiment, a structure can be used at which the address status signal ADS #, which at the time the refresh request is masked instead of the signal RAS # is used.

Fig. 187 shows a further structure of the refresh control portion. As has already been described, the CDRAM enters sleep mode when the signal SP # is held in the active state "L" for a predetermined period or longer. The internal circuit does not work in sleep mode. The CPU therefore does not access it. In this state, self-refresh is carried out. The structure for this process is described below.

As shown in Fig. 187, the refresh control section has inverter circuits 8702 and 8704 which invert the sleep determination signal Sleep, an AND circuit 8700 which receives the output signal from the inverter circuit 8702 and the master-slave indicator M / S # 8708 which receives the output signal from the inverter circuit 8704 and a refresh request signal supplied from either the refresh terminal 8000 or the selection switch 8040 , a gate circuit 8706 which receives the refresh request ΦREF # from the first arbitration means 8014 and the sleep mode determination signal Sleep, and a gate circuit 8710 which receives the output signals of gate circuits 8706 and 8708 . A refresh request signal is transmitted from gate circuit 8710 to second arbitration means 8020 .

The gate circuit 8706 outputs an active signal when the refresh request ΦREF # is in the active state "L" and the sleep mode determination signal Sleep is at the active level "H". Gate circuit 8708 provides a signal "H" when the external refresh request signal ext.REF # is in the active state and the signal supplied by inverter circuit 8704 reaches the inactive level "H". Gate circuit 8710 outputs a "L" signal when one of the output signals from gate circuits 8706 and 8708 reaches "H" level. Gate circuit 8700 controls the output state of switch 8040 . The operation is briefly described below.

In normal operating mode, the sleep mode determination signal Sleep is inactive and the gate circuit 8700 passes the indicator M / S #. Therefore, the switch 8040 is put into a high output impedance state or a state in which the refresh request ΦREF # is passed according to the indicator M / S #. Because the sleep mode determination signal Sleep is at the inactive level "L", the output signal of the gate circuit 8706 is fixed at "L". Gate circuit 8708 receives the "H" level signal at its positive input via inverter circuit 8704 and operates as a buffer. In this case, therefore, the gate circuit 8710 generates a refresh request in accordance with the refresh request ext.REF # supplied from the terminal 8000 or the switch 8410 , and the second arbitration means 8020 carries out the arbitration necessary for the refresh. Therefore, a refresh is carried out in both master and slave mode.

When the sleep mode is set, the sleep mode determination signal Sleep rises to "H", the output signal of the gate circuit 8700 reaches the "L" level, and the changeover switch 8040 , regardless of whether the chip is a master or a slave, becomes the state of high output impedance transferred. Because gate circuit 8708 receives a "L" level signal at its positive input via inverter circuit 8704 , its output is fixed at "L". The gate circuit 8706 operates as a buffer in response to the sleep mode designation signal Sleep which is "H" and generates the refresh request in accordance with the refresh request FREF # generated by the first arbitration means 8014 . The logic of the refresh request generated by gate circuit 8706 is inverted by gate circuit 8710 and applied to second arbitration means 8020 as a refresh request with negative logic.

Therefore, in the sleep mode operation, the refresh is carried out in accordance with the refresh request generated by the self-refresh timer in the chip. There is no external access to a CDRAM in sleep mode. It is therefore not necessary to carry out the internal processes synchronously. At this point, port 8000 is placed in a high output impedance state. It is not necessary to transmit another external refresh request ext.REF #, the charging / discharging of this signal line can be avoided, and therefore the power consumption in sleep mode can be reduced.

Figure 188 shows another example of the memory system structure. In the example of the storage system described above (see Fig. 177), the refresh operation is carried out bank by bank. In the structure shown in Fig. 188, all refresh ports are connected to each other regardless of the banks. In this case, all of the CDRAMs CR00 to CRN4 of the memory system carry out the refresh operation synchronously. In this example as well, the same effect as in the embodiment described above can be achieved. The CDRAM has been described above. However, a structure for realizing refresh using the master / slave structure can be applied to any synchronous semiconductor memory device in which external signals are adopted in synchronism with the clock signal. The structure is not limited to the CDRAM.

[Data transmission method]

In the DRAM control signal truth table shown in Fig. 94, the instructions for data transfer from the write data transfer gate DTBW to the DRAM array include an instruction DWT1 for performing data transfer between the master register and the intermediate register of the data transfer circuit DWTB and a command DWT2, which blocks the data transfer between the master register and the intermediate register. A new transfer command is formed here.

Command DRT1: The command is intended to transfer data between the Master register and the intermediate register (hereinafter referred to as slave Register) in the write data transfer circuit simultaneously with the data transfer process from the DRAM field to the read data Execute transfer circuit DTBR.

Command DRT2: The command is intended to transfer data between the Master register and the slave register of the write data Block transmission circuit and a data transmission from Execute DRAM field for read data transfer circuit DTBR.

By forming the two DRAM Read transfer commands can write back and write quickly Data transmission can be made compatible in page mode. It will the data transfer process using these commands described.

The commands mentioned below are used with the same meaning as the commands shown in Fig. 94.

As shown in Fig. 189, an active command ACT is first applied to the DRAM, and a line corresponding to the CPU address is selected in the DRAM. A DRAM read transfer command 1 is then supplied to the DRAM. At the same time, a buffer write transfer command BWT is applied to the SRAM. In the DRAM field, a row selection process is carried out in accordance with the active command ACT, and then, in accordance with the DRAM read transfer command 1 DRT1, the data block B1 of the selected row is transferred to the read data transmission circuit DTBR. The command DRT1 specifies the data transfer from the slave register of the write data transfer circuit DTBW to the master register. Therefore, the SRAM data block A1, which has been transferred from the SRAM field to the slave register STW in accordance with the BWT command, is subsequently transferred to the master register MTW. It should be noted that the data transfer between the SRAM array and the data transfer circuits DTBW and DTBR is performed by the SRAM driver section, while the data transfer between the DRAM array and the data transfer circuits DTBW and DTBR is controlled by the DRAM driver section.

To simplify the description, Fig. 189 shows a state in which data is transferred from the DRAM field to the slave register STR of the read data transfer circuit DTBR in accordance with the command DRT1. Whether the data transfer according to this command is carried out immediately depends on the frequency of the clock signal used (latency).

As shown in Fig. 190, the DRAM-NOP instruction DNOP (no operation) is applied, and a buffer write transfer instruction BWT1 is supplied to the SRAM. In this cycle, the DRAM continuously executes the previous command and the DRAM data block B1 is latched to the read data transfer circuit DTBR.

Another line is selected in the SRAM and the corresponding one Data block A2 becomes the slave register STW of the write data Transfer circuit DTBW transferred and locked there.

As shown in Fig. 191, the DRAM-NOP instruction DNOP is again supplied to the DRAM and a buffer read transfer instruction BRTR is applied to the SRAM. The previous operating state is retained in the DRAM. In the SRAM, the data block B1, which is stored in the master register MTR of the read data transfer circuit DTBR, is stored in the selected line of the SRAM field. At this point, the line in which the data block A1 has previously been stored is selected in the SRAM field. Data block B1 is therefore stored instead of data block A1. The necessary data, that is to say the data requested by the CPU, are output in parallel with this storage process.

Due to the sequence of operations described above, a Cache miss hits the data requested by the CPU with high Transfer speed to SRAM field and read immediately so that the access delay for a cache Missed hits can be significantly reduced. This process is used as a fast write-back mode, as above has been described. By selecting two data blocks A1 and A2 the block size of the cache can be doubled. In order to the cache size can be increased.

As shown in Fig. 192, a DRAM read transfer command 2 DRT2 is supplied in the DRAM and a command * is applied to the SRAM. The command * can be any command except the BWT buffer write transfer command and the BRTW buffer write transfer / write command. In the DRAM, a data block B2 which exists in the same line as the data block B1 but belongs to a different data block is selected and transmitted to the read data transfer circuit DTBR. A desired operation is performed for the DRAM. However, the content of the write data transfer circuit DTBW is not changed by the command *.

As shown in Fig. 193, the DRAM-NOP instruction DNOP is supplied to the DRAM and the instruction * is applied to the SRAM. The DRAM data block B2 is therefore stored in the master register MTR in the read data transfer circuit DTBR.

As shown in Fig. 194, the DNOP instruction is applied to the DRAM and the buffer read transfer instruction BRT is applied to the SRAM. At this time, the line in which the data block A2 has been stored is set to the selected state in the SRAM. Corresponding to the BRT, the data block B2 which has been stored in the master register MTR of the read data transfer circuit DTBR is transferred to the SRAM field. Consequently, data blocks A1 and A2 are replaced by DRAM data blocks B1 and B2 in the SRAM field. The block size of the cache can namely be two lines (32 bits) of the SRAM.

As shown in Fig. 195, a precharge command PCG is applied to the DRAM. The command * is applied to the SRAM. With the precharge command PCG, the DRAM field returns to the precharge state. Subsequently, as shown in Fig. 196, the active command ACT is applied to the DRAM and the command * to the SRAM. The row in which the SRAM data blocks A1 and A2 are to be stored is selected in the DRAM field in accordance with the tag address. The command * is supplied to the SRAM, and data is not rewritten into the write data transfer circuit DTBW.

As shown in Fig. 197, the DRAM write transfer command 2 DWT2 is supplied to the DRAM. The command * is applied to the SRAM. The DBT2 command carries out a data transfer between the slave register STW and the master register MTW in the write data transfer circuit DTBW. As shown in Fig. 197, in this cycle in which the DWT2 instruction is applied, data transfer from the master register MTW to the DRAM column is not performed, and therefore the transfer operation is shown by a broken line.

As shown in Fig. 198, the DNOP instruction is supplied to the DRAM and the * instruction is applied to the SRAM. Consequently, the data block A1, which has been stored in the master register MTW of the write data transfer circuit DTW, is stored in the corresponding column of the DRAM.

Then, as shown in Fig. 199, the DRAM write transfer command 1 DWT1 is applied to the DRAM and the command * is supplied to the SRAM. The command DTW1 represents an operating mode for transferring the data from the slave register STW of the write data transfer circuit DTBW to the DRAM field via the master register MTW. Therefore, in this example, the data block A2 is transferred to the selected line of the DRAM field. At this time, the DRAM field contains the same line as the line selected by the previous DWT2 command in the selected state, and therefore data block A2 is stored at a different position in this line, in which data block A1 is stored has been filed.

As shown in Fig. 200, the DRAM-NOP instruction DNOP is supplied in the DRAM. As a result, writing of data block A2 for the selected row and column of the DRAM is completed. At this point, the command for the SRAM can be any command (unimportant). Therefore, the precharge command PCG is supplied to the DRAM. With this precharge command, the DRAM returns to the precharge state.

Through the sequence of operations described above, the Data blocks A1 and A2 of the SRAM field corresponding to the page mode be written back. The fast write back mode and the Page mode can both be used.

A structure can be used where the line according to the address requested by the CPU in the DRAM corresponding to a page hit / miss upon completion of the preload is selected.

It becomes a special operational sequence in the event of a cache miss described.

Fig. 201 shows a signal diagram of the operation in the case of a cache miss when the write indicator bit is set. Fig. 201 shows an operational sequence for a clock signal at 66 MHz. The T1 cycle involves the occurrence of a cache miss where the address sampled as the address status signal ADS # falls does not match the tag address. Because the write indicator bit is set, the contents of the cache differ from the contents of the main memory. If a cache miss occurs, the contents of the cache must therefore be written back to main memory.

The following procedure is used when reading with page hits carried out. If there is an access request and it is turns out a cache miss and page hit the DRT1 and BWT commands are generated in the cycle. As a result, data transfer from the SRAM field to Write data transfer circuit performed. Because the command DRT1 is applied in the write data transfer circuit a data transfer from the slave register to the master register carried out. According to the DRT1 command, data from the Transfer DRAM field to the read data transfer circuit.

The commands DRT2 and BRTR are executed in cycle 5. The previously according to the command DRT1 in the read data Data stored in the transfer circuit becomes the SRAM field transferred and the data requested by the CPU read. At this point, data will be processed according to the Command DRT2 from the DRAM field to the read data transfer circuit transfer. There is no data transmission between the slave Register and the master register of the write data Transfer circuit carried out. In cycles 6 to 8, this becomes SRAM is given an SR command and data is sequential read. In cycle 7, a precharge command is sent to the DRAM applied so that the DRAM field returns to the precharge state.

In cycle 9, the command BWT is supplied and data is transferred from the SRAM field to the slave register of the write data transfer circuit transfer. Consequently, in the write data Transfer circuit stored two data blocks.

In cycle 10 commands ACT and BRT are created, in the DRAM field a row selection process is performed while corresponding the BRT command corresponding to the DRT2 command in cycle 5 in  the data block stored in the read data transfer circuit corresponding line of the SRAM field is stored.

In cycle 13 the command DWT2 is executed and the data that in the master register of the write data transfer circuit have been saved will be saved in the appropriate place selected row of the DRAM field. In cycle 15 the command DWT1 created, and the data in the slave register the write data transfer circuit are stored on the corresponding position of the DRAM field. So that will the write back process is completed. The DRAM field can start Cycle 16 are addressed, and in cycle 17 there is an instruction created for the DRAM field.

If the page miss is read, the following will occur Operation carried out.

In response to a cache miss, the instructions become PCG and BWT fed. As a result, the DRAM field returns to Precharge status back. Data is transferred from the SRAM field to the slave Transfer register of the write data transfer circuit. Then the ACT command is created in cycle 6 and a line in the DRAM selected. In cycle 8, the command DRT1 is created, and the Data of the corresponding position of the selected line of the DRAM are transferred to the slave register of the read data transfer circuit the master register is saved. The data transfer between the registers is in the write data transfer circuit executed.

The commands DRT2 and BRTR are created in cycle 10. According to the BRTR command, be in the appropriate place of the SRAM field stores the data corresponding to the Command DRT have been transmitted. According to the command DRT2 data is transferred to the read data transfer circuit. To At this point in time, no data transmission between the Master register and the slave register of the write data Transfer circuit executed. Then the command SR fed and data are read one after the other. In cycle 12  the PCG precharge command is created. Consequently, the DRAM Field back to precharge state.

The BWT command is created in cycle 14 and in cycle 15 the commands ACT and BRT are supplied. This will make rows of the DRAM field and the SRAM field is selected, and the SRAM Cell data are stored in the write data transfer circuit (slave Register). In accordance with the BRT command the data corresponding to the DRT2 command of cycle 10 have been stored in the read data transfer circuit for Position of the line transferred according to the DWT command (Cycle 14) has been selected. In the DRAM there is one line selected, and in cycle 18 and the following, the DWT2 and DWT1 commands executed. The data in the Write data transfer circuit have been saved saved one after the other.

The following procedure is used when writing with Page- Missed hit. First the commands PCG and BW and data are fed into the write data transfer circuit written. The DRAM field returns to the precharge state. in the Cycle 6, an ACT command is created and a line in the DRAM selected. Then the command DWT1 is fed in cycle 9, and the data written in the write data transfer circuit have been selected for the corresponding position Transfer the line of the DRAM field.

When writing with a page hit, the commands BW and DWT1 created. The data created at this time become the master and slave register of the write data Transfer circuit transfer.

Fig. 202 shows a signal diagram of the operation sequence when a 50 MHz clock signal is applied. In Fig. 202, the sequence of operation for a miss-write operation and a miss-read operation is under the same conditions as in the example of FIG. 201, that is, when the Schreibindikatorbit is set illustrated. In the operation sequence shown in Fig. 202, the DRAM-NOP period (no operation) is shorter than in the example of Fig. 201. The order of generation of the commands DRT1 and DRT2 differs from the signal diagram of Fig. 201. If the buffer write transfer command BWT once applied, the DRAM read transfer command is supplied twice. Therefore, a similar process can be realized regardless of which of the DRT1 and DRT2 commands are generated earlier. More specifically, the data transfer from the DRAM field to the read data transfer circuit is carried out together with the data transfer from the SRAM field to the write data transfer circuit when the commands DRT2 and BRT are applied.

When the commands DRT1 and BRTR are supplied, the data stored in the read data transfer circuit is written to the corresponding location of the SRAM field, and then the new DRAM cell data is transferred to the read data transfer circuit. At this time, data transfer from the slave register to the master register is carried out in the write data transfer circuit. When the BWT command is created (cycle 8), data is then stored in the slave register of the write data transfer circuit. Therefore, the SRAM data is stored in the write data transfer circuit which is transferred in cycles 3 and 8 according to the BWT command. Therefore, an operation similar to that shown in Fig. 201 can be realized.

Fig. 203 shows an operation sequence when the master clock signal has a frequency of 40 MHz. The signal diagram of FIG. 203 is similar to that of Fig. 201. There is realized a similar operation except that the DRAM NOP period (no operation) differs due to the difference in clock frequency. Fig. 204 shows a sequence of operation when the master clock signal CLK has a frequency of 33 MHz. The sequence of operations shown in FIG. 204 is similar to the sequence of operations in FIG. 202, and the only difference concerns the DRAM-NOP period (no operation). The difference results from the different frequency of the master clock signal.

As described above, the DRAM-NOP time period differs (no operation) depending on the frequency of the master clock signal, because the internal data transfer time is determined by the latency becomes. The length of the latency can vary according to the frequency of the Clock signal can be set.

Fig. 205 shows a truth table of the control signals for setting the DRAM read transfer command. As shown in Fig. 205, the signals RAS #, CAS # and DTD # are all set to "H" for the DRAM-NOP instruction (no operation). The signal CMd # is at "H". For the DRAM read transfer command 1 DWT1, the signals RAS # and DTD # are set to "H" and the signal CAS # to "L". For the DRAM read transfer command 2 DRT2, the signals RAS # and CAS # are set to "H" and the signal DTD # to "L". The method of generating these commands is only an example and other combinations of signal states can be used.

The write data transfer circuit DTBW and the read data transfer circuit DTBR each have similar structures to those shown in FIGS . 125 and 127.

The control signal generation system has a structure similar to that shown in Fig. 129. In the write data transfer circuit shown in FIG. 125, the signal DWTE for controlling the data transfer from the intermediate register 4002 , that is to say the slave register, to the master register 4004 is activated / deactivated according to the commands DRT1 and DRT2.

In the third embodiment of the CDRAM with a controller, controller 7026 generates a signal in accordance with the external control signal, the cache hit signal, and the page hit signal. This can be realized when the signals supplied to the internal DRAM driver section and the SRAM driver section are generated to satisfy signal logic similar to that shown for the first and second embodiments.

Fig. 206 shows a further structure of the data transfer circuit. As shown in Fig. 206, the write data transfer circuit DTBW has N stages on registers # 1 to #N. In this example, registers # 1 to #N have a shift register structure and perform locking and moving for the data created. With this structure, the block size of the cache can be increased to N times. The reason is because N data blocks can be successively transferred between the DRAM field and the SRAM field according to the page mode. Data transfer in the write data transfer circuit DTBW is performed by expanding the structure of the two stages of registers described above.

In the write data transfer circuit DTBW shown in FIG. 206, a similar effect is achieved not only by the shift register structure, but also by a register with a FIFO structure (first in / first out).

[Image processing system]

Fig. 207 shows an example of the image processing system using the CDRAM according to the present invention. As shown in Fig. 207, the image processing system includes a CPU 9500 as an external processing unit for processing data, a CDRAM 9530 , an image display unit 9520 for displaying data on a monitor, and a high-speed video interface 9510 for controlling access to the CDRAM the image display and the access between the CPU and the CDRAM. The CPU 9500 is connected to the high-speed video interface 9510 via a data bus 9505 .

The DRAM 9530 has an SRAM area 9540 for storing video data (data of one scan line) and a DRAM area 9550 .

The DRAM area 9550 has a video area 9560 for storing video data. Data transfer is performed between the SRAM 9540 and the video area 9560 . The CPU 9500 operates at an operating frequency of 33 MHz. The high-speed video interface 9510 operates at 66 MHz and controls access to the CDRAM 9530 of the CPU and the image display unit 9520 . The data transmission (corresponding to the commands DRT and BRT) from the DRAM area 9550 to the SRAM area 9540 transfers video data from the DRAM field 9550 to the SRAM field 9540 . Under the control of the high-speed video interface 9510 , the CPU 9500 directly accesses the data transfer circuit in accordance with the buffer read instruction BR and the buffer write instruction BW on the data transfer circuit formed in the CDRAM 9530 . The image display unit 9520 accesses the SRAM area 9540 . The high-speed video interface 9510 is interleaved through this.

Fig. 208 schematically shows the principle of operation of the image processing system shown in Fig. 207. In the return time of the video data (horizontal and vertical return time), a transfer of video data from the DRAM area 9550 to the SRAM area 9540 is carried out. The CPU 9500 can not address the CDRAM 9530 during this period. Outside of the ramp-down time, a so-called "image refresh" can be carried out, in which video data is changed by the CPU which accesses the CDRAM 9530 . Namely , the CDRAM 9530 can implement an operation similar to a video RAM that includes an optional access port and a serial access port.

The control process of the high speed video interface 9510 will be described.

Fig. 209 shows a signal diagram of the operation of the video data processing system when the CDRAM is operating in the "transparent output mode". In Fig. 209, CK33 represents the operating speed of the CPU and CK66 represents the operating speed of the high-speed video interface 9510 which the CDRAM 9530 addresses. Video data is transmitted to the image display unit 9520 at a speed of 15.5 MHz. Access to the video data is performed using the SR command. In Fig. 209, cycle T1 denotes a video access cycle and T2 denotes a CPU access cycle.

As shown in Fig. 209, a video address VIDEO0 is created in the first cycle by the command SR, and in accordance with this address, video data is output on the CDRAM bus as the next clock signal CK66 rises. This data is transmitted to the image display unit 9520 via the high-speed video interface 9510 .

An access is then carried out by the CPU. At this time, the commands DWT and BW are supplied, the DRAM write transfer operation and the buffer write operation are executed, the data from the CPU are written to the data transfer circuit, and the written data is transferred to the DRAM field. Then the video access is performed and video data VIDEO1 is read by the SR command from the SRAM field 9540 . In CDRAM 9530 , data transfer is carried out in accordance with the command from the CPU. In the next cycle, the DRT command is applied, data is transferred from the DRAM to the data transfer circuit, and the block read operation is carried out. The valid data are output by this block read mode. The valid data of this block read mode are output after three clock cycles have elapsed. Note that the CDRAM 9530 is accessed in accordance with the clock signal CK66 while the CPU issues an access request in accordance with the clock signal CK33. Then, video data and the CPU data are sequentially output in accordance with the BR and SR commands.

Because the CPU and the image display unit alternately access the CDRAM of this interlocking arrangement, the CPU can perform the DRAM without interrupting access (except for the transmission period of the video data from the DRAM area 9550 to the SRAM area 9540 ). This enables data processing at high speed.

Fig. 210 shows a signal diagram of the operation of the image processing system when the CDRAM outputs data in the register output mode. In the register output mode, data is output with a delay of one clock cycle, as has already been described with reference to FIG. 66. In the transparent output mode, outputs are made in the cycle that follows the access cycle. Therefore, when the register output mode is used, the next address can be applied while the previous data is output, as shown in Fig. 210. Therefore, the CPU and the image display unit can access the CDRAM alternately at the same speed. Namely, the CPU data and the video data can be input / output at the same speed.

In transparent output mode, valid data is output with the rise of the next clock signal when an address is created. If the CPU data and the video data are addressed alternately at the same speed, a data collision results. The video data VIDEO0 and the CPU data 486-0 are now used as an example in FIG. 210. If the CDRAM is operating in the transparent output mode and an address VIDEO1 is applied, video data VIDEO1 is output in the next clock cycle. At this time, write data 486-0 is created by the CPU. Therefore, the CPU data collide with the video data. In the register output mode, the data is output with a delay of one clock cycle, and therefore the data can be written safely and without data collision even when the CPU writes data to the CDRAM. An image processing system that operates at a higher speed can thus be formed.

Figure 211 shows a comparison of the operating speed of a standard DRAM and CDRAM. It is assumed that data is to be written which is arranged in 16 rows _* 16 columns, as shown in Fig. 211 (a). As shown in Fig. 211 (b), in the standard DRAM, it is necessary to write the data one by one by switching the signal CAS after activating the signal RAS. When a row of data is written, the DRAM field is precharged and the data must be rewritten according to the RAS and CAS signals.

As shown in Fig. 211 (c), data in CDRAM is successively written to the data transfer circuit in accordance with the buffer write command BW, the DRAM active command ACT is applied to the DRAM, the written data collectively becomes the row of the DRAM field in accordance with the command DWT is transferred and the remaining lines are written to. If the next line is to be accessed, the line selection process of the DRAM can be carried out at the same time as the data writing to the data transfer circuit in accordance with the BW command. The RAS precharge time is therefore not required at all externally. Thus, data can be written at high speed.

In the description regarding Fig. 211, 8 bits are treated as a cache block, that is, as a transfer size.

Fig. 212 shows a comparison of the data writing operation when there is a page boundary in a rectangular area. The lines of the DRAM field differ at the page boundary. In this case, as shown in Fig. 212 (a), there is a page boundary at the interface between the data D1 area and the data D2 area, and the data D1 and data D2 are stored in different DRAMs. Word lines saved. In this case, as shown in Fig. 212 (b), in the standard DRAM, the data D1 is first written using the signals RAS and CAS until the page limit is reached. Then the DRAM is preloaded and the remaining data D2 and D3 of the first line must be written in accordance with the signals RAS and CAS. A similar procedure must be carried out in the area of the second line. Therefore, the DRAM field must be preloaded both at the page boundary and when changing the rows in the arrangement with 16 rows _* 16 columns. Therefore, the RAS precharge time prevents high speed data processing.

As shown in Fig. 212 (c), in the CDRAM, after the data has been written in accordance with the buffer write command BW, data is written in accordance with the commands DWT and BWTW, and in parallel the precharge command PCG of the DRAM field is applied and the data can be written one after the other according to the buffer write command BW. In parallel to writing data to the data transfer circuit in accordance with the buffer write command BW, a DRAM line can be selected into which the data D2 and D3 are to be written. By transferring the commands DWT and BWTW at the end of this line section, data can be written to the desired DRAM line. Therefore, when switching the rows with the arrangement with 16 rows _* 16 columns, a precharge must be carried out, which requires a waiting time, but with the arrangement with 16 rows _* 16 columns no RAS precharge time is necessary at the page boundary, so data can be written at high speed.

Fig. 213 shows a signal diagram of the operation when data arranged in 16 rows _* 16 columns is to be read from the DRAM field. It is assumed that the data groups D1 and D2 arranged as in Fig. 213 (a) are read. The data D1 and D2 are blocks that each form a transmission unit.

Fig. 213 (b) shows a data reading sequence when a synchronous semiconductor memory device (SDRAM) is used. The synchronous semiconductor memory device SDRAM can read data in synchronism with the clock signal at high speed. The synchronous semiconductor memory device has a serial register in the data input / output section and enables data input / output to and from the serial register in synchronism with the clock signal. When reading data, the internally selected memory cell data is stored collectively in the serial register, and then the data is read out successively from the serial register in synchronism with the clock signal. If the number of serial registers is 8, it is necessary to store new data in the serial register every time 8 data bits are read. Therefore, the CAS signal for loading data into the serial register is generated. If data are to be read from the serial register one after the other after data has been loaded into the serial register, another line can be preloaded in the DRAM field and set to the selected state. Therefore, when a synchronous semiconductor memory device SDRAM is used, data can be read more or less continuously.

As shown in Fig. 213 (c), in the CDRAM, the necessary data is transferred to the data transfer circuit according to the ACT and DRT commands, and the data is transferred to the SRAM field from the data transfer circuit according to the BRTR command, and then data can be safely transferred accordingly read the command SR. In this case too, precharging and activation can be carried out in the DRAM field when data is read from the SRAM field. Therefore, the data reading can be performed at the same speed as in a synchronous semiconductor memory device SDRAM.

Fig. 214 shows a signal diagram of the operation of the SDRAM and CDRAM in data reading when a page boundary exists. As shown in Fig. 214 (a), it is assumed that the WRAP length (data length that can be read continuously) in the synchronous semiconductor memory device (hereinafter simply referred to as SDRAM) is 8. As shown in Fig. 214 (b), the RAS precharge state is assumed at the page boundary in the SDRAM, and then the DRAM field is activated again. With this, data is stored in the read register (serial register formed in the data output area), then data is read one by one, and then it is necessary to read data one by one by transferring new data by switching the signal CAS. Therefore, in this case there is a significant RAS preload time and the RAS-CAS delay time at each page boundary.

As shown in Fig. 214 (c), in the CDRAM, even with a page boundary in the middle of the arrangement, it is possible to read data one by one by transferring the data to the data transfer circuit and to preload and close the DRAM field in parallel activate. There is no precharge influence from the DRAM field, so that the data can be read at a higher speed than in the SDRAM.

Fig. 215 shows a signal diagram of the operation for the read-modify-write operation. As shown in Fig. 215 (a), it is assumed that the data are arranged in 16 rows _* 16 columns and all are overwritten according to the read-modify-write mode. As shown in Fig. 215 (b), the read command and the write command are output in the SDRAM depending on the drop of the signal CAS. Therefore, two clock signals are required for the read command and the write command. If the read-modify-write process is to be carried out for the data of a line, there is therefore a waiting time between the write process and the execution of the read process. This prevents the data from being changed quickly.

In contrast, in CDRAM the data can be written by writing data from the DRAM field to the SRAM field via the transfer circuit and through alternately performing data reading from the SRAM field and the Data writing to the transfer circuit can be changed. The all data required for the write data Transfer circuit written after the data accordingly the command DRT has been transmitted to the read data transfer circuit are. Then the data that is in the write data Transfer circuit have been written according to the Transfer the BWT command to the DRAM field. Therefore, in the DRAM field the data is rewritten at high speed if there is no page boundary in one line.

Figure 216 shows a signal diagram of the operation when data occupying a triangular area is to be written. It is assumed that the video data containing the data D1 and D2 and arranged in a triangular shape in the range of 16 rows _* 16 columns should be written as shown in Fig. 216 (a). At this time, as shown in Fig. 216 (b), data must be written in the SDRAM and DRAM by switching the signals RAS and CAS according to the respective line. Therefore, there is a RAS precharge time and a RAS-CAS delay time in each line.

On the other hand, in the CDRAM, the RAS-CAS delay time can be reduced compared to the SDRAM and DRAM because the data can be written to the data transfer circuit according to the command BW and the row selection process of the DRAM field can be carried out in parallel, as in Fig. 216 ( c) is shown. However, the precharge time of the DRAM field remains. Therefore, data writing can be performed at a higher speed.

By using the CDRAM according to the present invention, implemented an image processing system as described above be the processing of data at high speed executes.

Because the present invention is structured so that the Operational control of the DRAM section and the SRAM section is executed independently, and on a bidirectional transfer circuit for transferring data between the SRAM field and the DRAM field directly from the outside can be accessed as described above Semiconductor memory device implemented as Cache memory in a storage system or as video memory can be used for graphics applications and with high Performance and high operating speed works.

The essential characteristics of the present Effects brought about by the invention are as follows.

• 1) If the DRAM field is active, different DRAM Column blocks are formed in succession. thats why it is possible to continuously display a line of data (a page of Data) by the sense amplifier in the DRAM field, a Data transfer between the DRAM section and the independent driven SRAM section using the page mode of the Execute DRAM, resulting in high data transfer Speed is performed, and therefore the access time reduce significantly in the event of a cache miss.  
• 2) A data transmission circuit for data transmission between the SRAM field and the DRAM field is controlled by a latch Circuit for the temporary storage of data formed. Therefore it becomes possible to access the data directly Input / output data transfer circuit from outside. Consequently the data input / output of the DRAM field can be carried out, without affecting the data stored in the SRAM. Therefore a semiconductor memory device that is not formed only as a cache system, but also for graphics applications is useful.
• 3) The data transfer circuit has a write buffer circuit for transferring data to the DRAM and a read data Transfer buffer for receiving data from the DRAM field, the is formed separately. Each of them becomes one Latch circuit formed. Therefore, the data transfer executed in parallel between the DRAM field and the SRAM field become. This enables high-speed data transmission Speed.
• 4) The bidirectional data transfer circuit has one Write transfer circuit with a plurality of latches for Transfer data to the DRAM field and it is one Masking circuit for masking the data transmission for the respective latch of the write transfer circuit formed. Therefore only the necessary memory data of the DRAM field changed so that the data stored in the DRAM field easily overwritten at high speed can.
• 5) The bidirectional data transfer circuit has one Intermediate register means for temporarily storing created Data, a buffer circuit for receiving the data from the Intermediate register created data and for transferring the data to the DRAM field, an intermediate masking register for storing Masking data, which is an independent masking of the Enables data transfer to the DRAM field for each data bit, and a master masking register that holds the masking data from the Intermediate masking register synchronous with the data transfer from  Intermediate data register to receive buffer register, for masking the data transfer from the buffer register to the DRAM field. Because the masking data of the intermediate masking register in Depends on whether the data comes from outside or from the SRAM field can be created selectively, are only the data to be transferred to the DRAM field with high Pass speed.
• 6) The masking data of the intermediate masking register become all reset when data is transferred from the SRAM field, while only the masking data corresponds to that Intermediate masking register, which is used to write data to the external applied data are subject to Intermediate mask registers are reset so that only the required data safely and easily to the DRAM field be transmitted.
• 7) Because the data transfer is carried out when that Intermediate data register and the intermediate masking register dated Buffer registers or master masking registers are separated, can repeat the same data in the memory cell blocks of the DRAM. So a process like "fill" run at high speed. Therefore one can Get semiconductor memory device for Graphics processing is effective.
• 8) Because a DRAM field, an SRAM field and a bidirectional Data transmission circuit for data transmission between the SRAM field and the DRAM field are formed and the operation with respect to the DRAM field regardless of the operation that the SRAM Field and data input / output concerns, independently executed by a separate control circuit can be a data input / output that a High-speed mode, such as the page mode of the DRAM connects to be executed. Furthermore, a successive data writing, such as the Block write mode, performed at high speed become.  
• 9) Because a signal indicating the selection / non-selection of the Controls semiconductor memory device, and a signal to Data input / output locks can be formed separately a semiconductor memory device are formed, in which a Memory expansion capability and fast bank switching can be implemented.
• 10) Because there are two control signals for data input / output are formed and the activation / deactivation of the Input / output circuit according to the result of an AND Formation of these two input / output control signals is controlled can easily switch banks with high Speed to be implemented. If the Semiconductor memory device both the DRAM section and has the SRAM section, the cache formed by the SRAM can Size can be changed easily.
• 11) The bidirectional data transmission circuit has one Read data transfer buffer with a latch circuit for temporarily storing and locking data from the DRAM field and a write data transfer buffer that transfers data directly from the SRAM Field or the data input / output port receives. This implements a semiconductor memory device when before reading data from the DRAM field in the Read data transfer buffer Data at high speed entered / output and a write-through of the cache with can run at high speed.
• 12) In the DRAM field you can use the data latch function the DRAM sense amplifier can write data without writing to it DRAM field to be run in write-through mode, that is, a Write data without assignment in the event of a cache miss. This enables data writing in accordance with the Block write mode can be run at high speed. Furthermore, one can immediately after the data writing Hit operation for a different address, so that a semiconductor memory device with a cache that with works at high speed.  
• 13) In a semiconductor memory device with a cache Memory that works in write-through mode is on High speed access by using the latch data of the DRAM sense amplifier possible. Therefore one can Semiconductor memory device with a short waiting time received even in the event of a cache miss.
• 14) In the semiconductor memory device with It is not necessary to write back a cache Missed data in the SRAM field because the data in the DRAM sense amplifiers locked data can be used. This makes data writing at high speed and one Data writing possible in block write mode.
• 15) In the cache with write-back mode, the locked data of the DRAM sense amplifier can be used. This results in a semiconductor memory device with a Cache, which has a short waiting time in the event of a cache miss having.
• 16) Because the transmission / non-transmission of clock signals the control circuit that drives the DRAM section and to a second control circuit for controlling the SRAM section and the Data input / output carried out independently of one another clock signal transmission to the DRAM section be stopped while the SRAM section is operating. Thereby the power consumption in the DRAM section can be significant can be reduced. So you can get one Semiconductor memory device with low power consumption achieve.
• 17) As command data for the command register, the data for Set the input / output port arrangement of the Semiconductor memory device, the operating mode and the like Sizes stores, predetermined bits of the Column selection address of the DRAM used. Therefore can Command data without increasing the number of control connections can be entered. Command data for setting the mode for Data writing from the data transfer circuit to the DRAM field  can be fed simultaneously in the operating mode determination cycle become. Therefore, a desired mode of operation can be easily Way and set at high speed without Increase load for external devices.
• 18) Because the address bits for selection in the DRAM field are all as Command data are taken over and part of the command data for Set test mode setting / reset and Setting the type of data transfer mode to the DRAM field in Test mode operation can be used on command data simple way using a memory tester can be set. This can cause a Semiconductor memory device for the simple and a test can be performed with high reliability without increase the load on the memory tester, be implemented.
• 19) Because the self-refresh of the DRAM field at the same time executed with the command register setting mode, the time required to determine the mode can be reduced, and it may be a semiconductor memory device that has a High speed access enables to be implemented.
• 20) In the command data setting mode, only the operation becomes Store command data in the command register does not affect the operation of the DRAM field at all. Thereby the command data can be changed easily, even if the DRAM is working.
• 21) Because the masking data for masking the Data transfer to the DRAM field set after switching on the masking values are set.
• 22) Because the peripheral circuit by applying a predetermined number of master clock signals after the Switching on is initialized, the states of the internal Circuits safely to a predetermined initial state can be set.  
• 23) It is a first control section for controlling the operation of the DRAM field and data transfer between the DRAM field and the bidirectional data transmission circuit as well second control section for controlling the operation of the SRAM array and the data transfer between the SRAM field and the bidirectional data transmission circuit or the external Access to the SRAM field formed separately. The first and second control sections work independently of each other. As a result, a semiconductor memory device with Multiple functions are formed with high Speed works.
• 24) Because a second transistor element is driven around the first node to a predetermined potential only for one to drive predetermined period of time when the first Transistor element that drives the signal line is inactive, the external signal line can then operate at a high level Speed driven to a predetermined potential level if a structure is used in which the first Transistor element is connected in the manner of an OR logic. This makes high-speed access with a simple Circuit structure enables.
• 25) Because a special test mode is used when a predetermined state of an external signal twice or several times in succession in sync with the external clock signal test mode can be created by the timing condition be realized, so that the test mode on simple and safe Way is set.
• 26) Because a special test mode is used when external signals of a predetermined combination of states continuously for a predetermined period of time in synchronization with external clock signal are applied and leave the test mode becomes when the external signals of this predetermined State combination can be supplied, the test mode be taken easily and safely. During this Time period may be a desired command from the storage device can be fed, and the test can be run while  the semiconductor memory device in a desired one Operating mode works. Because leaving test mode can be executed in synchronism with the clock signal Leave to be set by the timing conditions, so that the test mode can be safely reset.
• 27) Because the refresh control terminal by the Mode setting means as an input port or as an output port can be set under the control of a Storage device a plurality of Semiconductor memory devices are refreshed so that the Self-refresh mode during normal operation can be executed.
• 28) Because the refresher according to one contained Self-refresh timer depending on one Sleep mode determination signal is executed, it is not necessary a refresh request to others To send semiconductor memory devices so that the Power consumption for charging / discharging signal lines can be reduced.
• 29) When transferring data from the DRAM field to the first Data transmission device can be in the second Transmission device for transmitting data from the SRAM field to the DRAM field selectively transfer data between latches in of the second transmission device so that a quick write back using page mode can be carried out. This enables the enlargement of the Block size of the cache, the page mode and the fast Write-back mode can run concurrently, and it high speed access can be realized while the waiting time in the event of a cache miss is reduced.
• 30) Because in the transfer circuit for transferring data from SRAM field to the DRAM field a plurality of latches is formed and the transfer process between the latches in the second Transfer device is selectively executed when data from DRAM field are transmitted to the first transmission device,  can increase the cache block size and cache hit rate be improved. Furthermore, the data transmission between the SRAM field and the DRAM field corresponding to the page mode be carried out. The fast write-back process for one Cache miss can also be done in accordance with the Page mode are executed. That enables one High speed data transfer.
• 31) Because the second transmission device in the Write data transfer circuit N stages of FIFO storage means the block size of the cache can be increased.
• 32) Because the CDRAM works in register output mode and the Access by the CPU and the image processing unit for the Access to the CDRAM are interlocked, the access work through the CPU and the access for the video display not against each other, the CDRAM can run at high speed can be addressed, and therefore an image processing system be realized, the fast processing of the image data enables.

Claims (41)

1. semiconductor memory device, characterized by a DRAM field ( 102 ; 7001 ) with a plurality of dynamic memory cells which are arranged in a matrix of rows and columns,
first control means ( 128 , 110 , 112 ; 1452 ; 6008 , 6009 ) having row selection means ( 110 ) dependent on a first address for selecting a row in the DRAM array and column block selection means ( 112 ) derived from a second Address dependent, for selecting a column block having a plurality of columns of the DRAM dependent on an external control signal for driving the DRAM field, the column block selection means being able to repeatedly select different column blocks while the row selection means is in an active state and one row selects
an SRAM array ( 104 ) with a plurality of static memory cells arranged in a matrix of rows and columns,
second control means ( 132 , 118 , 120 ; 6000 , 6006 , 6002 , 6004 ) with memory cell selection means ( 118 , 120 ) dependent on a third address which is applied independently of the first and second addresses for selection a plurality of memory cell blocks in the SRAM field, which is dependent on an externally supplied second control signal for driving the SRAM field and is independent of the first control means, and
data transfer means ( 106 ), dependent on a data transfer specification, for performing block transfer of data between the selected column block of the DRAM array and the selected memory cell block of the SRAM array. 2. semiconductor memory device, characterized by a DRAM field ( 102 ) with a plurality of dynamic memory cells which are arranged in a matrix of rows and columns,
an SRAM array ( 104 ) with a plurality of static memory cells arranged in a matrix of rows and columns,
a first selection means ( 110 , 112 ) for the simultaneous selection of a plurality of memory cells in the DRAM field,
a second selection means ( 118 , 120 ) for the simultaneous selection of a plurality of memory cells in the SRAM field, a data transfer means ( 106 ) with a plurality of latch means ( 140 , 142 , 144 ) for temporarily storing applied data for simultaneously carrying out a data transfer between the selected plurality of memory cells of the DRAM array and the plurality of selected memory cells of the SRAM array, and
access means ( 134 , 136 , 138 , 120 ; 1434 , 1438 , 1514 , 1516 , 1518 ) for accessing the latch means in the data transfer means corresponding to an address applied to input / output data. 3. A semiconductor memory device according to claim 2, characterized in that the data transmission means ( 106 ), a read transfer means ( 140 ; 1510 ; 1610 ; 5000 , 5002 ) for receiving data transmitted from the DRAM field, and a write transfer means ( 142 , 144 , 146 ; 3520 , 3530 ) for transferring data to the DRAM field, the read transfer means and the write transfer means each having a plurality of latch means ( 4002 , 4004 , 4006 , 4008 , 5000 , 5002 ) for temporarily storing applied data. 4. A semiconductor memory device according to claim 2, characterized in that the data transmission means ( 106 ) a write transfer means ( 142 , 144 , 146 ) with a plurality of latch means ( 142 , 144 ) for temporarily storing applied data for transferring the applied data to the DRAM Field and a masking means ( 146 ), which is formed corresponding to each latch means of the write transfer means, for masking the data transfer to the DRAM field by the respective latch means. 5. A semiconductor memory device according to claim 2, characterized in that
the data transmission means ( 106 ) comprises a plurality of latch means ( 1510 , 1520 ) for temporarily storing applied data,
buffer means ( 4004 ) receiving data from the latch means for transferring the data to the DRAM field,
intermediate masking means ( 4006 ), formed corresponding to each of the plurality of latch means, for storing masking data indicating whether the transmission of the data stored in the corresponding latching means to the DRAM field should be masked,
masking means ( 4008 ) which receives the masking data from the intermediate masking means in synchronism with the data transfer from the latch means to the buffer means, for masking the data transfer from the buffer means to the DRAM field, and
control means ( 6006 , 6009 ), dependent on an operating mode specification indicating whether the latch has received data from the SRAM array or externally supplied write data, for setting masking data of the intermediate masking means. 6. A semiconductor memory device according to claim 5, characterized in that
the control means ( 6006 , 6009 )
means ( 6009 ) for resetting all of the masking data of the intermediate masking means when the operating mode setting indicates data transfer from the SRAM field to the data transfer means, and
means ( 6006 ) for resetting only the masking data corresponding to the latch means receiving the external write data when the operating mode determination indicates that external write data is supplied to the data transfer means. 7. The semiconductor memory device according to claim 5 or 6, characterized in that the control means ( 6006 , 6009 ) further comprises means ( 6009 ) which is dependent on an operating mode specification which indicates that the same value is to be transmitted repeatedly to the DRAM field, for separating the latch means ( 4002 ) from the buffer means ( 4004 ) and for separating the intermediate masking means ( 4008 ) from the master masking means ( 4006 ). 8. A semiconductor memory device according to claim 2, characterized in that
the data transmission means ( 106 )
slave latch means ( 4002 ) for temporarily storing data created by the SRAM field or external write data supplied by the access means,
master latch means ( 4004 ) for temporarily storing data created by the slave latch means,
slave masking means ( 4006 ) for storing masking data indicating that the data stored in the slave latch means should or should not be masked for transmission to the DRAM field,
a master masking means for temporarily storing masking data from the slave masking means, and
comprises driver means ( 3540 , 3550 ) for transferring data from the master latch to the DRAM field corresponding to the masking data from the master masking means. 9. A semiconductor memory device according to claim 8, characterized by
a first control means ( 6000 , 6006 ) for controlling the data transfer from the SRAM field to the slave latch means ( 4002 ), and
a second control means ( 6008 , 6009 ), which is formed independently of the first control means, for controlling the (synchronous) data transmission from the slave latch means ( 4002 ) to the master latch means ( 4004 ) and from the slave masking means ( 4006 ) to the master masking agent ( 4008 ). 10. A semiconductor memory device according to claim 9, characterized in that the first control means ( 6000 , 6006 ) has means ( 6000 , 6004 ) for activating the data writing to the slave latch means by the access means. 11. A semiconductor memory device according to claim 2, characterized in that the data transmission means ( 106 ) a slave latch means ( 5000 ) for temporarily storing data from selected memory cells of the DRAM array ( 102 ), and a master latch means ( 5002 ) for temporarily storing data from the slave latch for transmission to selected memory cells in the SRAM field or for access. 12. A semiconductor memory device, characterized by a DRAM field ( 102 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns,
an SRAM array ( 104 ) with a plurality of static memory cells arranged in a matrix of rows and columns,
data transfer means ( 106 ) having a plurality of read transfer means ( 140 ; 1510 ) for receiving data transferred from the DRAM array and temporarily storing the data to transfer data between the DRAM array and the SRAM array,
a first control means ( 128 , 108 , 112 ) for selecting a memory cell in the DRAM field for transferring the data of the selected memory cell to the read transfer means,
second control means ( 6000 , 6002 , 6004 ), operating in parallel with and independent of the first control means, for selecting a static memory cell in the SRAM array for input and output of data to or from the selected static memory cell, and
a third control means ( 6000 , 6006 ), which operates independently of the first control means, for transferring data from the read transfer means to the SRAM field. 13. A semiconductor memory device, characterized by a DRAM field ( 102 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns,
an SRAM array ( 104 ) with a plurality of static memory cells arranged in a matrix of rows and columns,
data transfer means ( 106 ) for performing bitwise transfer between the DRAM field and the SRAM field,
a data input / output means ( 134 , 136 , 138 ) for transferring data between the SRAM field or the data transfer means and an external data input / output node (DQ; D, Q),
a first control means ( 1424 , 1464 , 1450 , 1452 ) dependent on a first control signal for setting at least the DRAM field, the SRAM field, the data transmission means and the data input / output means to an unselected standby state, and
second control means ( 1490 , 1494 ) dependent on a second control signal for controlling the activation and deactivation of only the data input / output means. 14. A semiconductor memory device according to claim 13, characterized in that the second control signal (DQC) comprises a control signal (DQC0) of a first type and a control signal (DQC1) of a second type, and the second control means ( 1490 , 1494 ) means for generating a Control signal for controlling only the data input / output means ( 1100 ) by a logical AND formation of the control signal of the first type and the control signal of the second type. 15. A method of driving a semiconductor memory device
a DRAM array ( 102 ) having a plurality of dynamic memory cells arranged in a matrix of rows and columns, a sense amplifier means ( 114 ) which detects the data of the memory cells connected to a selected row of the DRAM array , amplified and locked, an SRAM array ( 104 ) with a plurality of static memory cells arranged in a matrix of rows and columns, a read transfer means ( 1510 ) with means ( 5000 , 5002 ) for locking applied data from the DRAM array , and a write transfer means with latch means ( 4002 , 4004 ) for temporarily storing data which are supplied from a selected memory cell in the SRAM field or externally applied data, characterized by the steps

• a) Selecting a row in the DRAM field, and reading, amplifying and locking the data of the memory cells connected to the selected row by the sense amplifier means, and in data read mode:
• b) determining whether the data requested by an external device is stored in the SRAM field or not,
• c) selecting a corresponding memory cell of the SRAM field corresponding to an applied address and reading the data of the selected memory cell if the result of the determination in step (b) indicates that the required data are present in the SRAM field,
• d) determining whether or not the created address specifies the selected line of the DRAM field if the result of the determination in step (b) indicates that the requested data is not available in the SRAM field,
• e) Selecting a plurality of columns in the DRAM field, transferring the data of the selected plurality of columns to the read transfer means, selecting the corresponding memory cell in the SRAM field corresponding to the address applied, transferring the data from the read transfer means to the selected cells in the SRAM field and further selecting a memory cell in the SRAM array specified by the applied address to read data from the selected memory cell when the result of the determination in step (d) indicates that the applied address determines the selected row of the DRAM array ,
• f) if the result of the determination indicates that the created address determines a line which is different from the selected line of the DRAM field:
• g) initializing the DRAM field and the sense amplifier means and then selecting a corresponding line in the DRAM field corresponding to the address that has been created,
• h) selecting a plurality of columns in the DRAM field corresponding to the address applied and transmitting the data of the selected plurality of columns to the read transfer means after the corresponding row in the DRAM field has been selected,
• i) Selecting memory cells in the SRAM field corresponding to the address applied simultaneously with or in parallel with the data transfer to the read transfer means, transferring data from the read transfer means to the selected memory cells and further selecting a memory cell in the SRAM field and reading the data of the selected memory cell in parallel therewith .

16. A method of driving a semiconductor memory device with
a DRAM array ( 102 ) having a plurality of dynamic memory cells arranged in a matrix of rows and columns, a sense amplifier means ( 114 ) which detects the data of the memory cells connected to a selected row of the DRAM array , amplified and locked, an SRAM array ( 104 ) with a plurality of static memory cells arranged in a matrix of rows and columns, a read transfer means ( 1510 ) with means ( 5000 , 5002 ) for locking applied data from the DRAM array , and
a write transfer means ( 1520 ) with latch means ( 4002 , 4004 ) for temporarily storing data which are supplied from a selected memory cell in the SRAM field or of externally applied data, characterized by the steps
Selecting a row in the DRAM array, and reading, amplifying and locking the data of the memory cells connected to the selected row by the sense amplifier means, and
in data writing mode:

• i) if there is a memory cell in the SRAM field with the address to which access by an external device is required,
• a) writing data into the corresponding memory cell of the SRAM field corresponding to the address created and writing the data into the write transfer means,
• b) selecting a column in the DRAM field and transferring the data between the selected column and the write transfer means if the address created defines the selected row of the DRAM field,
• c) initializing the DRAM field and the sense amplifier means, selecting a row and a column in the DRAM field according to the address applied, and then transferring data between the selected column of the DRAM field and the write transfer means when the address applied determines a line which is different from the selected row of the DRAM field,
• ii) if there is no memory cell in the SRAM field with the address to which access is required by the external device,
• d) writing data into the write transfer means according to the address created,
• e) selecting a column in the DRAM field corresponding to the address applied and transferring data from the write transfer means to the selected line if the address specified defines the selected line in the DRAM field, and
• f) Initializing the DRAM field and the sense amplifier means and then selecting a row and a column in the DRAM field according to the address created, and transferring the data from the write transfer means to the selected column if the address created does not specify the selected line in the DRAM field .

17. The method according to claim 16, characterized in that the determination in steps (e) and (f) whether the applied Address specifies the selected line in the DRAM field, is postponed until a next access is requested. 18. A method of driving a semiconductor memory device having a DRAM array ( 102 ) with a plurality of dynamic memory cells arranged in a matrix of rows and columns, a sense amplifier means ( 114 ) which receives the data of the memory cells associated with a selected row of the DRAM field are connected, detected, amplified and locked, an SRAM field ( 104 ) with a plurality of static memory cells arranged in a matrix of rows and columns, a write transfer means ( 1520 ) with a plurality of latch means ( 4002 , 4004 ) for transferring data to a block of a plurality of columns in the DRAM field, and a read transfer means ( 1510 ) with a plurality of latch means ( 5000 , 5002 ) for receiving data from the block of the plurality of columns, which are selected in the DRAM field, characterized by the steps

• a) selecting a row in the DRAM array, and reading, amplifying and locking the data of the memory cells connected to the selected row by the sense amplifier means, and
• A) in data reading mode
• i) if there is no data in the SRAM field to which access is required by an external device,
• ii) determining whether a write indicator bit is set which indicates that the data stored in the SRAM field and the data stored in the DRAM field which are defined by the same address differ;
• iia) selecting a plurality of memory cells of the SRAM field in accordance with an applied address, transferring and storing the data of the selected memory cells to and in the write transfer means,
• iib) if the created address indicates the selected line in the DRAM field:
• iib1) selecting a block of a plurality of columns corresponding to the address created from the selected row of the DRAM field and transmitting the data of the block of the selected plurality of columns to the read transfer means,
• iib2) selecting a plurality of memory cells in the SRAM field corresponding to the address applied for further transferring the data which have been transferred to the read transfer means to the selected memory cells,
• iib3) selection and reading of corresponding data from the data which have been transmitted to the reading transfer means in accordance with the address which has been created,
• iic) if the created address indicates a line that differs from the one selected in the DRAM field:
• iic1) initializing the DRAM field and the sense amplifier means and then selecting a row and a block of a plurality of columns in the DRAM field according to the address applied, and transmitting the data of the selected column block to the read transfer means,
• iic2) selecting a plurality of memory cells in the SRAM field according to the applied address, transferring data from the read transfer means to the selected memory cells, and selecting and reading data transferred to the read transfer means according to the applied address,
• iii) if the write indicator bit is cleared:
• iiia) when the applied address specifies the selected row in the DRAM field, selecting a block of columns from the selected row and transferring the data of the block to the memory cells of the SRAM field selected by the applied address and further reading data which are to be stored in a memory cell in the SRAM field corresponding to the address applied, selecting a row and a plurality of columns in the DRAM field corresponding to the address applied, and transferring the data from the plurality of columns to memory cells which are created by the Address are set in the SRAM field, and reading data to be stored in a memory cell in the SRAM field set by the applied address, and
• B) in data writing mode
• Ba) accessing the SRAM field in accordance with the created address and writing data into the corresponding static memory cell if there is a memory cell in the SRAM field which is determined by the created address,
• Bb) setting the write indicator bit,
• Bc) if the SRAM field does not have the memory cell specified by the address created by the external device:
• Bc1) writing data to the write transfer means according to the address created,
• Bc2) selecting columns from the selected row corresponding to the created address and transferring data from the write transfer means to the selected column if the created address specifies the selected row in the DRAM field,
• Bc3) initializing the DRAM field and the sense amplifier means and selecting a row and columns in the DRAM field corresponding to the applied address if the applied address specifies a line different from the line selected in the DRAM field,
• Bc4) Transfer from the write transfer means to the selected column.

19. A semiconductor memory device which accepts an externally applied control signal in synchronism with an externally applied clock signal in a pulse train for generating an internal control signal, characterized by
a DRAM array ( 102 ) with a plurality of dynamic memory cells arranged in a matrix of rows and columns,
first control means ( 128 ), which is dependent on the clock signal, for accepting a first external control signal for generating a control signal for driving the DRAM field,
an SRAM array ( 104 ) with a plurality of static memory cells arranged in a matrix of rows and columns,
an input / output means ( 134 , 138 ) for inputting and outputting data from and to outside the storage device,
data transfer means ( 106 ) for exchanging data with the input / output means and for transferring data between a selected memory cell of the DRAM field and a selected memory cell in the SRAM field,
a second control means ( 132 ) for accepting an externally applied second control signal in dependence on the clock signal for generating a control signal for driving at least the SRAM field or the data transmission means,
a first clock signal gate ( 126 ) dependent on a first clock signal mask signal to block transmission of the clock signal to the first control means, and a second clock signal gate ( 130 ) dependent on a second clock signal mask signal to block transmission of the clock signal to the second control means. 20. A semiconductor memory device that accepts an externally applied signal in synchronism with a clock signal that is applied in the form of pulses.
characterized by a DRAM field ( 102 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns,
an SRAM array ( 104 ) with a plurality of static memory cells arranged in a matrix of rows and columns,
data transfer means ( 106 ) for transferring data at least between a selected memory cell of the DRAM array and a selected memory cell of the SRAM array , an instruction register means ( 9033 ) for storing instruction data for setting a specific operating mode of the semiconductor memory device and the arrangement of data input and Data output ports of the semiconductor memory device, and
means ( 9030 ) dependent on the clock signal for storing a predetermined number of bits of an address for selecting a column of the DRAM field as command data in the command register means. 21. A semiconductor memory device that accepts an externally applied signal in synchronism with a clock signal that is applied in the form of pulses.
characterized by a DRAM field ( 102 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns,
an SRAM array ( 104 ) with a plurality of static memory cells arranged in a matrix of rows and columns,
data transmission means ( 106 ) for performing at least one data transmission between a selected memory cell of the DRAM field and a selected memory cell of the SRAM field,
command register means ( 9033 ) for storing command data for specifying at least one particular operating mode of the semiconductor memory device, and
means ( 400 ) dependent on a combination of the states of external control signals applied in synchronism with the clock signal, each signal being supplied to an address input node for selecting a row and a column of the DRAM field as a command value part of it is used as data for specifying the type of data transfer mode to the DRAM field in the data transfer means and as data for specifying a test mode of the semiconductor memory device to store the value in the command register means. 22. A semiconductor memory device according to claim 21, characterized by means ( 404 , 406 ) for performing self-refreshing of the DRAM array when the test mode is set. 23. The semiconductor memory device according to claim 21 or 22, characterized by means ( 9030 ), which is dependent on a combination of the states of external control signals, for executing an adjustment of only the command data in the command register means. 24. Semiconductor memory device, characterized by a DRAM field ( 102 ) with a plurality of dynamic memory cells which are arranged in a matrix of rows and columns,
an SRAM array ( 104 ) with a plurality of static memory cells arranged in a matrix of rows and columns,
write transfer means ( 142 , 144 ; 1520 ) for temporarily storing applied data and for transferring the stored data to a selected memory cell of the DRAM field, masking data register means ( 4006 , 4008 ) for storing masking data for masking the data transfer from the write transfer means to the selected one Memory cell of the DRAM field, and
control means ( 400 , 402 ) dependent on power on for setting all masking data of the masking data register means to a state which masks the data transmission. 25. The semiconductor memory device according to claim 24, characterized by means ( 400 ), which is dependent on switching on, for repeatedly executing the reset operation of a peripheral circuit according to a predetermined number and for activating the control means. 26. A semiconductor memory device, characterized by a DRAM field ( 102 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns,
an SRAM array ( 104 ) with a plurality of static memory cells arranged in a matrix of rows and columns,
data transfer means ( 106 ) for transferring data between a selected memory cell of the DRAM array and a selected memory cell of the SRAM array,
first control means ( 128 ), dependent on a first address and a first control signal, for controlling the operation of the DRAM array and the data transfer process between the DRAM array and the data transfer means, and
a second control means ( 132 ), which is formed independently of the first control means and operates independently of the first control means, is dependent on a second control signal and a second address which is applied independently of the first address, for controlling the driving of the SRAM field, the data transfer process between the SRAM array and the data transfer means, and the data input / output operation between the data transfer means and the environment of the device. 27. A synchronous semiconductor memory device which operates in synchronism with a clock signal, characterized by a first transistor element ( 9011 ) for driving a first node ( 9010 ) to the potential of a first level, and a second transistor element ( 9012 ) which is deactivated by the deactivation of the first transistor element is dependent on driving the first node to the potential of a second level only for a predetermined period of time. 28. Synchronous semiconductor memory device that accepts an external signal in synchronism with a clock signal, characterized by
a first transistor element ( 9011 ), which is connected between a first supply node and an output node , for driving the output node to the potential level of the first supply node as a function of a driver signal,
a second transistor element ( 9012 ), connected between the output node and a second supply node , for driving the output node to the potential level of the second supply node, and
a control means ( 9022 , 9023 ; 9022 , 9025 ), which is dependent on the deactivation of the driver signal, for activating the second transistor element for a predetermined period of time from the transition of the clock signal to an active state. 29. A method of driving an output circuit having a first transistor element ( 9011 ) and a second transistor element ( 9012 ) connected in series between a first supply and a second supply, in a synchronous semiconductor memory device that has an external signal in synchronism with an external clock signal in the case of a unidirectional transition this clock signal takes over, characterized by the steps:
Activating the first transistor element in order to drive an output node to the potential level of the first supply as a function of a drive signal,
Deactivating the first transistor element, and
Activating the second transistor element in response to the deactivation of the first transistor element in order to drive the output node for a predetermined period of time from the time of the unidirectional transition of the external clock signal. 30. Synchronous semiconductor memory device capable of executing a predetermined test mode and taking an external signal in synchronism with a clock signal, characterized by detection means ( 9030 , 9032 , 9040 , 9042 ) for detecting synchronously with the clock signal that an external signal with a predetermined state is twice or several times in a row, and
test mode setting means ( 9035 ; 9044 ) dependent on the detection signal from the detection means for setting the predetermined test mode. 31. A synchronous semiconductor memory device that can execute a predetermined test mode and accepts a plurality of external signals in synchronism with a clock signal, characterized by
detection means ( 9030 , 9032 ; 9040 , 9042 ) for detecting in synchronism with the clock signal that a combination of predetermined states of the plurality of external signals is continuously or twice applied in succession,
test mode setting means ( 9035 ; 9044 ), dependent on a detection signal from the detection means, for accepting a predetermined address signal bit and for setting the predetermined test mode so that the synchronous semiconductor memory device is set in a state which permits the test mode operation, and
means ( 9032 ; 9042 ) for resetting the test mode setting means when a combination of predetermined states of the plurality of external signals is applied after detection by the detection means. 32. Synchronous semiconductor memory device with memory cells, characterized by
a signal connector ( 8000 )
timer means ( 8012 ) for generating a refresh request in a predetermined time interval,
mode setting means ( 8040 ), dependent on a mode setting signal, for disabling or enabling transmission of the refresh request from the timer to the signal port, and
refresh means ( 8020 ) connected to the signal port and dependent on the refresh request supplied to the signal port for performing a refresh of the memory cells. 33. The semiconductor memory device according to claim 32, characterized by
means ( 8700 ), dependent on a sleep mode designation signal, for inhibiting transmission of the refresh request from the timer to the signal port, and
means ( 8706 , 8710 ), dependent on a sleep mode designation signal , for transmitting the refresh request from the timer to the refresh means. 34. The semiconductor memory device according to claim 32 or 33, characterized by
buffer means ( 8030 ) dependent on an external control signal that triggers a cycle to select a memory cell from among the memory cells, generate an internal control signal to activate the circuitry related to the selection of a memory cell, and
first arbitration means ( 8014 ), dependent on the refresh request and the internal control signal, for disabling the transmission of the refresh request when the internal control signal is active. 35. Semiconductor memory device according to claim 34, characterized in that
the buffer means ( 8030 ) comprises means ( 9060 ) dependent on the internal control signal for generating a precharge completion signal indicating that the memory cells have been brought into an unselected state, and wherein the refresh means ( 8020 )
second arbitration means ( 8022 ), dependent on the precharge completion signal and the refresh request from the signal port or timing means, for generating a refresh request signal and a mask signal when the precharge completion signal is active to indicate the unselected state of the memory cells, the masking signal to the Buffer means is applied to mask the external control signal so that the buffer means receives the external control signal in the inactive state, and
refresh control means ( 8024 ), dependent on the refresh request signal , for triggering the refresh. 36. semiconductor memory device, characterized by a DRAM field ( 102 ) with a plurality of dynamic memory cells,
an SRAM array ( 104 ) with a plurality of static memory cells,
a first transmission means (DTBR) with at least two stages of serially connected latch means (STW, MTW) for transmitting data from the DRAM field to the SRAM field,
a second transmission means (DTBW) with at least two stages of serially connected latch means (STR, MTR) for transmitting data from the SRAM field to the DRAM field,
a first control means ( 6008 , 6009 ), which is dependent on a first transfer determination (DRT1), for performing the data transfer from the DRAM field to the first transfer means and for performing the data transfer between the latch means of the second transfer means, and
a second control means ( 6008 , 6009 ), which is dependent on a second transfer determination (DRT2), for carrying out the data transfer from the DRAM field to the first transfer means and for blocking the data transfer between the latch means of the second transfer means. 37. The semiconductor memory device according to claim 36, characterized characterized in that the second transmission means N stages of FIFO storage means (# 1- # N), where N is an integer not less than 2 is.   38. semiconductor memory device, characterized by a DRAM field ( 102 ) with a plurality of dynamic memory cells,
an SRAM array ( 104 ) with a plurality of static memory cells,
a first transmission means (DTBR) with at least two stages of serially connected latch means (STR, MTR) for transmitting data from the DRAM field to the SRAM field,
a second transmission means (DTBW) with at least two stages of serially connected latch means (STW, MTW) for transmitting data from the SRAM field to the DRAM field,
a first transfer control means ( 6000 , 6006 ), which is dependent on a first transfer determination, for carrying out the data transfer from the SRAM field to only one latch means of the second transfer means, and
a second transfer control means ( 6000 , 6006 ), which is dependent on a second transfer determination, for performing the data transfer from the SRAM field to a plurality of latch means of the second transfer means. 39. The semiconductor memory device according to claim 38, characterized characterized in that the second transmission means N stages of FIFO storage means (# 1- # N), where N is an integer not less than 2 is. 40. Image processing means, characterized by
a data processing unit ( 9500 ) which generates an access request in synchronism with a first clock signal,
a semiconductor memory device ( 9530 ) synchronized with a clock signal, which operates in a register output mode in which an address signal is applied in synchronism with a second clock signal and the data of the memory cell, which is determined by the address, is output in the next clock cycle,
an image processing unit ( 9520 ) for displaying an image, and
access control means ( 9510 ) for alternately enabling the data processing unit and the image processing unit to access the semiconductor memory device synchronized with the clock signal. 41. The system of claim 40, characterized in that the access control means ( 9510 ) operates in synchronism with a third clock signal to access the semiconductor memory device synchronized with the clock signal, the third clock signal having twice the frequency of the first clock signal, and the first clock signal has twice the frequency of the second clock signal.