DE4337740B4 - Semiconductor memory device and method for driving a semiconductor memory device - Google Patents

Abstract

Semiconductor memory device, comprising:
a DRAM field (102; 7001) with a plurality of dynamic memory cells which are arranged in a matrix of rows and columns,
a first control means (128, 110, 112; 1452; 6008, 6009) having a row selection means (110) dependent on a first address for selecting a row in the DRAM field and a column block selection means (112) derived from a second Address dependent for selecting a column block having a plurality of columns of the DRAM, the control means being dependent on an external control signal for driving the DRAM field and the column block selection means being able to repeatedly select different column blocks while the row selection means is in an active state and selects a row in response to a one-time activation of a data transfer schedule;
an SRAM array (104) having a plurality of static memory cells arranged in an array of rows and columns;
second control means (132, 118, 120; 6000, 6006, 6002, 6004) with memory cell selection means (118, 120) dependent on a third address which is applied independently of the first and second addresses for selection a plurality of memory cell blocks in the SRAM array in response to the one-time activation of the data transfer setting, the control means being dependent on an externally supplied second control signal for driving the SRAM array and being independent of the first control means; and
a data transfer means (106), which is dependent on the one-time activation of the data transfer setting, for performing block-by-bit data transfer between the selected column block of the DRAM array and the selected memory cell block of the SRAM array.

Description

The invention relates to a semiconductor memory device and a method for driving a semiconductor memory device. The invention particularly relates to a semiconductor memory device, which has a main memory with large capacity and a fast cache with low capacity, which are integrated on the same chip. The present invention more specifically relates to a semiconductor memory device having a Cache, which is a dynamic random access memory (DRAM) and a static Has random access memory (SRAM) integrated on the same chip are.

(i) Use of standard DRAM as main memory

The operating speed more modern Microprocessor units (MPU) has risen so much that they become one Have an operating frequency of 25MHz or more. In a data processing system a standard DRAM becomes common as main memory with a large one memory used. Although the access time of a standard DRAM is reduced the operating speed of the MPU is much faster increased than that of the standard DRAM. Hence the increase the waiting cycles in a data processing system with a standard DRAM unavoidable as main memory. The distance in the operating speed between MPU and standard DRAM is inevitable because the standard DRAM has the following properties.

• (1) Row address and column address are time-multiplexed and are created on the same address connections. The row address becomes with the falling edge of a row address strobe signal / RAS adopted in the device. The column address becomes with the falling edge of a column address strobe / CAS transferred to the device. The row address strobe signal / RAS defines the start of a storage cycle and activates it Row selection circuit. The column address strobe signal / CAS activated the column selection circuit. Because a predetermined period of time with called "RAS / CAS delay time (tRCD) "between the time when the signal / RAS becomes active State and the time at which the signal / CAS is activated, there is a limit for the reduction the access time. Because there is a limit due to address multiplexing.
• (2) When the row address strobe signal / RAS has been raised once to put the DRAM in a wait state the row address strobe / RAS cannot be offset again fall to "L" until a time period called RAS precharge time (tRP) has passed. The RAS preload time is necessary to different Preload signal lines in the DRAM safely to predetermined potentials. Due to the RAS precharge time tRP, the cycle time of the DRAM cannot can be reduced. If the cycle time of the DRAM is reduced, also increases the number of loading / unloading operations of signal lines in the DRAM. This increases the current consumption.
• (3) A higher one Working speed of the DRAM can be achieved through circuit technologies can be realized, e.g. Layout improvements, enlargement of the Circuit integration levels, developments in manufacturing technology and through application-oriented improvements such as improvements in the activation process. The operating speed of the MPU however, increases much faster than that of the DRAM. The operating speed of Semiconductor storage is hierarchical. For example, there are high-speed bipolar RAMs that Use bipolar transistors, e.g. ECLRAMs (emitter-coupled RAMs) and static RAMs, as well as relatively slow DRAMs with MOS transistors (field effect transistors with insulated gate). It is very difficult to get operating speeds (Cycle times) of several tens of ns (nanoseconds) in a standard DRAM, which is formed by MOS transistors.

It has several application-oriented improvements given the gap between the operating speeds of MPU and standard DRAM close. Such improvements mainly include the following two approaches.

• (1) Using high speed modes of the DRAM and interleave method.
• (2) External high-speed cache formation (SRAM).

The first access (1) involves using one High speed mode such as a static column mode or a page mode, and combining the high speed mode and of the interleave process. In static column mode there is a word line (one line) selected, and subsequently only the column address is successively changed to memory cells of this row to address one after the other. A word line is selected in page mode, and then the column addresses by switching the signal / CAS successively read in to memory cells with this one word line are connected to address one after the other. In both modes, the Memory cells can be addressed without switching the signal / RAS, which means faster access than normal access using of the signals / RAS and / CAS possible is.

In the interleave method, a plurality of memories are formed in parallel with a data bus, and the access time can be reduced by alternately or successively addressing the plurality of memories. The use Formation of a high-speed mode of the DRAM and the combination of high-speed mode and interleave method is known as a method of using a standard DRAM as a high-speed DRAM in a simple and relatively effective manner.

The second approach (2) is high Dimensions in the range the mainframes been applied. High speed cache is expensive. In the field of personal computers, where both high performance as well low cost desired in some areas, this access is irrespective applied to the cost. There are three ways to use the high speed cache to form, namely

• (a) The high speed cache is contained in the MPU itself;
• (b) the high speed cache is outside the MPU formed; and
• (c) the high speed cache is not separate formed, but a high-speed mode in standard DRAM is used as a cache (the high speed mode is called a pseudo cache used). If a cache hit occurs, the standard DRAM addressed in high speed mode, and in the event of a cache miss the standard DRAM in Normal mode addressed.

The above three ways are (a) to (c) used in data processing systems in one way or another Service. In terms of cost, in most MPU systems Storage organized with a bank structure and it becomes bank-wise interleaved, around the RAS preload time to overcome (tRP) which is inevitable in the DRAM. Through this procedure, the cycle time of the DRAM essentially to half of the specification value be lowered.

The interleave procedure is only efficient when the memories are addressed sequentially. If the same memory bank is addressed continuously, is them ineffective. Furthermore, there can be no significant improvement in access time of the DRAM itself. The minimum storage unit is at least two banks.

If a high speed mode, such as. the page mode or static column mode can be used the access time can only be effectively reduced if the MPU a certain page (the data of a defined line) multiple times responds. This procedure is somewhat effective when the number the banks are comparatively large, e.g. two or four because different lines in different Banks can be addressed. If the data of the memory requested by the MPU in the given Page does not exist, it is called a "miss" (cache miss) designated. Usually, a group of data will be adjacent or sequential addresses. In high speed mode a row address that represents half of the addresses has already been defined been, and therefore is the probability of a miss large.

When the number of banks becomes very large, namely 30 up to 40 banks can exist the data of different pages are stored in different banks and therefore the miss-hit rate is significantly reduced. However, it is not practical to add 30 to 40 banks in a data processing system form. If a miss occurs, the / RAS signal also turns on raised and the DRAM must be closed return to a precharge cycle to reselect the row address. This invalidates the properties of the bank structure.

In the second method described above (2) a high speed cache is formed between the MPU and the standard DRAM. In In this case, the standard DRAM can operate at a relatively slow speed exhibit. Standard DRAMs with storage capacity 4MBit or 16MBit are in use. In a small system such as. a personal computer, the main memory can be accessed by only one or a few standard DRAM chips are formed. The external Formation of the high speed cache is in one small system in which the main memory of a standard DRAM cannot be formed as effectively. If the standard DRAM is used as the main memory is the data transfer rate between the high speed cache and main memory limited by the number of data input / output connections of the standard DRAM, which is a bottleneck for the increase represent the system speed.

When the high speed mode is used as a pseudo-cache, its speed of operation lower than that of the high speed cache, and it is difficult to find the one you want Realize system performance.

The formation of the high-speed cache (SRAM) in DRAM has been proposed as a method to be a relative to create cheap and small system that the problem of system performance degradation solves when the interleave process or a high-speed operating mode is used. More specifically, a 1-chip memory is hierarchical Structure of a DRAM that serves as main memory and an SRAM, that acts as a cache memory. The 1-chip memory with Such a hierarchical structure is called cache DRAM (CDRAM).

A DRAM and an SRAM are normally integrated on the same chip in a CDRAM. The SRAM is accessed in the event of a cache hit, while the DRAM is addressed in the event of a cache miss. That with high speed SRAM is used as cache memory and the DRAM with high storage capacity as main memory.

The so-called block size of the cache is regarded as the number of bits whose contents are written in a transfer in the SRAM. Generally, as the block size increases, the hit rate increases. However, if the cache is the same size, the number of sets is reduced in inverse proportion to the block size, and therefore the hit rate decreases. For example, if the cache size is 4kBit and the block size is 1024, the number of sets is four. However, if the block size is 32, the set number reaches 128. In a CDRAM structure, the block size is therefore made too large, and the cache hit rate cannot be particularly improved. A structure that enables the block size to be reduced is, for example, in the JP 1-146187 described.

Fig. 217 shows the overall structure of the CDRAM, which is described in the cited document. As in Fig. 217 is shown, the CDRAM has a memory field 1 with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns. The memory cell array 1 is divided into a plurality of memory blocks B # 1 to B # 4, each having a plurality of columns. The memory blocks B # 1 to B # 4 share word lines.

The CDRAM also has a row address buffer 2 , which takes on externally applied address signals AO to An as a row address signal RA as a function of an external row address strobe signal / RAS and generates an internal row address signal, a column address buffer 4 , which adopts address signals AO to An in response to an external column address strobe signal / CAS as column address signal CA to generate an internal column address signal, a row decoder 6 from the internal row address signal from the row address buffer 2 is dependent on generating a signal to a corresponding row in the memory cell array 1 select a word driver 8th from the line selection signal from the line decoder 6 is dependent on transmitting a driver signal to the selected row of the memory cell array 1 to put a word line into a selected state according to the specified row, a sense amplifier group 10 to acquire, amplify and lock the data from the memory cells with the selected row in the memory cell array 1 are connected, a data register circuit 14 with a plurality of data registers corresponding to each column of the memory cell array 1 are formed, a transfer gate circuit 12 for transferring data between the respective column of the memory cell array and the data register circuit 14 , an IO gate 16 for decoding the internal column address signal from the column address buffer 4 to a corresponding column of the memory cell array 1 or a corresponding data register in the data register circuit 14 select a block decoder 18 , which is dependent on an externally applied cache hit / miss signal CH, for selecting a corresponding block in the memory cell array 1 , an input buffer 24 and an output buffer 26 for input / output of data from or to the outside, a column decoder 20 for decoding the internal column address signal from the column address buffer 4 for generating a signal for selecting and connecting the corresponding column of the memory cell array 1 or the corresponding data register of the data register circuit 14 via the IO gate circuit 16 with the input buffer 24 and the output buffer 26 , and a read / write control circuit 28 to control the activation / deactivation of the input buffer 24 and the output buffer 26 depending on an externally applied write activation signal / WE and the column address strobe signal / CAS.

The transfer gate circuit 12 and the data register circuit 14 are each divided into blocks corresponding to blocks B # 1 to B # 4 of the memory cell array.

The CDRAM also has a gate circuit 22 on, which is dependent on an externally applied cache hit / miss signal CH, for transmitting a column address signal which, for example, consists of the two least significant bits from the column address buffer 4 exists, as a block selection signal to the block decoder 18 , The block decoder 18 is activated when the cache hit / miss signal CH indicates a cache miss with "L". It decodes the applied block address signal by a corresponding memory cell block in the memory cell array 1 select, and drives the transfer gate circuit 12 block by block to transfer data between the selected memory cell array blocks and the data register corresponding to the selected memory cell array block.

Fig. 218 10 shows the structure of a main portion of the semiconductor memory device of FIG Fig. 217 , The Fig. 218 shows the structure in the border area between the two memory blocks B # 1 and B # 2.

As in Fig. 218 is shown, the sense amplifier group 10 Sense amplifiers SA # 1, which are each formed in accordance with the respective bit line pair BL, / BL of the memory block B # 1, and sense amplifiers SA # 2, which are each formed in accordance with the respective bit line pair BL, / BL of the memory block B # 2. The sense amplifiers SA # 1 and SA # 2 differentially amplify the signals on the corresponding bit line pairs BL, / BL and lock the signals when they are activated.

The transfer gate circuit 12 has transfer gates DT # 1, which are each formed for the respective bit line pair BL, / BL of the memory block B # 1, and transfer gates DT # 2, which are each formed for the respective bit line pair BL, / BL of the memory block B # 2. The transfer gate DT # 1 for the memory block B # 1 are driven independently of the transfer gates DT # 2 for the memory block B # 2. More specifically, the transfer gates DT # 1 for the memory block B # 1 are driven by a block decoder circuit BD # 1 formed for the memory block B # 1, while the transfer gates DT # 2 for the memory block B # 2 are driven by a block decoder circuit BD # 2 be driven, which is formed for the memory block B # 2. The block decoder circuits BD # 1 and BD # 2 decode a block address that is used in the event of a cache miss from the gate circuit 22 is passed in Fig. 217 and drive an associated transfer gate DT (# 1 or # 2) when the block address indicates a corresponding memory block.

The data register circuit 14 has a register DR # 1, which is formed in accordance with the respective bit line pair BL, / BL of the memory block B # 1, in order to latch data which are applied via the transfer gate DT # 1, and a register DR # 2 which has data on the Bit line pair BL, / BL of the memory block B # 2 receives and stores via the transfer gate DT # 2. The data registers DR (# 1 and # 2) have the structure of an inverter latch circuit.

The IO gate 16 has an IO gate TG, which is formed for the respective one of the bit line pairs BL, / BL of the memory blocks B # 1 and B # 2 and of a column selection signal from the column decoder 20 is dependent on connecting the corresponding bit line pair BL, / BL to an internal data transmission line pair IO. The IO gate TG connects the bit line pair BL, / BL of the memory blocks B # 1 and B # 2 via the transfer gate circuit 12 and the data register circuit 14 with the internal data transmission line pair IO. If the transfer gate circuit is blocked (disconnected state), the IO gate TG connects the data register in the data register circuit 14 with the internal data transmission line pair IO. Referring to the signal diagram of Fig. 219 is now the operation of the in Fig. 217 and 218 semiconductor memory device shown.

In the Fig. 217 The semiconductor memory device shown is used in a system having a CPU as an external processing unit and a controller for controlling access to the semiconductor memory device according to a request from the CPU. The controller has a tag memory for storing tag addresses of the data stored in the data register circuit, a comparison circuit for determining the match / mismatch between a tag address in the tag memory and a portion of the address from the CPU (CPU address) corresponding to the tag address to generate a signal CH indicating a cache hit / miss miss according to the determination result, and a control circuit (a state machine and an address multiplexer) for controlling the address handover and access to the semiconductor memory device according to the determination result of the comparison circuit.

An address is supplied from the CPU in synchronism with the system clock signal. When the CPU address determines data in the data register circuit 14 are stored, the externally formed controller sets the cache hit signal CH to "H", which corresponds to the active state. At this time, if the row address strobe / RAS is active low at "L", the external controller switches the column address strobe / CAS and extracts a column address CA from the CPU address and applies it to the semiconductor memory device.

In the semiconductor memory device, the applied column address signal CA from the column address buffer 4 taken over, which generates an internal column address signal and this to the column decoder 20 invests. Because the cache hit signal CH is at "H", the output signal is from the gate circuit 22 on "L", the block decoder 18 is disabled (or block address transmission is blocked) and no block selection is performed. In this case, the column selection process from the column decoder 20 is performed, the corresponding data register is connected to the internal data line pair IO, and data is written or read into or from the selected data register. Whether data is written or read depends on the write activation signal / WE.

When the data requested by the CPU is in the data register circuit 14 are stored, the cache hit signal CH is at "H" and the corresponding data register of the data register circuit 14 is selected in accordance with the column address signal CA.

If the CPU address is not the one in the data register circuit 14 determines stored data, the cache hit signal CH is in the "L" state. In the event of a cache miss, the external controller raises the / RAS and / CAS signals once to "H", then lowers the row address strobe signal / RAS to "L", extracts the row address signal RA from the CPU address and applies it the semiconductor memory device.

In the semiconductor memory device, the row selection process in the memory cell array 1 from the row address buffer 2 , the line decoder 6 and the word driver 8th is executed in accordance with the applied row address signal RA, and the data of the memory cell connected to the selected row is acquired, amplified and locked by the sense amplifier group. In parallel with these operations, the column address strobe signal / CAS is lowered to "L", and the column address signal CA is extracted from the CPU address and applied to the semiconductor memory device. Because the cache hit signal CH is at "L", the semiconductor memory is pre-loaded direction of the block decoder 18 is activated, and the block address signal of the applied column address signal is sent to the block decoder 18 created.

The block decoder 18 decodes the block address and switches through all transfer gates that are formed in accordance with the memory block specified by the block address. As a result, the data locked by the sense amplifier SA is transferred to the data register DR (# 1 or # 2) in the selected memory block. The column decoder runs in parallel 20 a column selection process, the transfer gate TG switches in the IO gate circuit 16 through and connects the data register DR to the internal data transmission line pair IO.

If a cache hit continues, the line in the memory field 1 is kept in the selected state, the data register DR (# 1 or # 2) is then from the column decoder 20 selected and addressed.

By dividing the memory field in blocks and driving the data registers block by block as described above the data register can be used as a cache. How 220 is shown in this case, the data registers TR # 1 to TR # 4, the corresponding the memory field blocks B # 1 through B # 4 are formed, storing data of different rows, whereby the cache hit rate is improved. You can also see the block size of the cache equal to the number of columns contained in the memory block are. This allows an appropriate size of the cache block realize.

In the semiconductor memory device described above the DRAM field is used as main memory, and the data register circuit can be used as a cache. Because the data transfer between the main memory and executed the cache block by block will, can Transfer data at high speed become.

Now an application of the above described semiconductor memory device, i.e. of a CDRAM an image data processing is discussed.

Fig. 221 shows the structure of a general image data processing system. As in Fig. 221 is shown, the system has a CPU 30 as a processing device, a CDRAM 32 , a cathode ray tube 34 as a display and a CRT controller 36 to control the data transfer between the CDRAM 32 and the cathode ray tube 34 on. CPU 30 , CDRAM 32 and cathode ray tube 34 are with an internal data bus 38 connected. Data transmission is via the internal data bus 38 executed.

The CDRAM 32 stores both image data to be displayed and data from the CPU 30 used and not shown. If the image data on the cathode ray tube 34 to be displayed is under the control of the CRT controller 36 a data transfer between the CDRAM 32 and the cathode ray tube 34 executed. The CDRAM 32 Read data is over the data bus 38 to the cathode ray tube 34 created and displayed on a screen, not shown.

If in CDRAM 32 stored data are to be processed, the CPU intervenes 30 on the CDRAM 32 to. At the same time, the CPU 30 the CDRAM 32 respond at high speed according to the result of the cache hit / miss detection, and thereby data can be processed at high speed. The one from the CPU 30 Data addressed should preferably be in the cache area of the CDRAM 32 be saved. It is believed that the CRT controller 36 Data in the storage field 1 of the CDRAM 32 reads and displays them on the cathode ray tube 34 transfers.

In such a case, in the CDRAM with the structure described above, it is necessary that the row selection process and the column selection process are under the control of the CRT controller 36 be carried out. The data in the storage field 1 are through the data register circuit 14 read. Therefore, in this case, the data stored in the data register circuit used as the cache can be overwritten by data stored on the CRT 34 should be displayed. If image data generated by a video camera (not shown) or similar device is inserted into the CDRAM 32 In this case, those in the data register circuit are also to be written 14 stored cache data overwritten by the image data that is to be written into the main memory of the CDRAM 32 be created.

Therefore, in the CDRAM described above the writing and reading of data in the main memory are not carried out, except the cache data is changed. Accordingly, it is difficult to have both the graphic data and data an application program that should not be shown, save in CDRAM.

With this structure the CDRAM will uses a block division when using a DRAM main memory high storage capacity is used. In this case a block structure is used in which the memory array shown in Fig. 218 or 220 as a block is used. In the block division, only the block is activated the one selected Has word line, and the other blocks are in an inactive Condition kept. The number of available data registers is therefore appropriate small. This lowers the efficiency of use of the cache.

If there is only one row of data registers as in the structure of the CDRAM shown in Fig. 218, only direct mapping (Direct Mapped) can be used as an implementable mapping method. In order to implement mapping using the set-associative method, it is necessary to have a plurality of data registers to form lines. The direct mapping method and the set associative method cannot both be fulfilled. Only one of these mapping methods can be implemented.

In the CDRAM with the structure described above can access a bit of data registers in parallel with data transmission from the DRAM field to the data register. In contrast to a dual-port video RAM, however, the DRAM section cannot run in parallel to access the SRAM without affecting access to the SRAM field by the DRAM area and the SRAM area independently of each other drives.

From Electronic Design, February 20, 1992, Pp. 142, 144, 146, a semiconductor memory device can be found be a cache DRAM with two bidirectional data transfer buffers contains that are arranged between the DRAM field and the SRAM field, so that a fast Copy-back activities possible is.

From U.S. Patent 4,926,385 a semiconductor memory device are taken out in a Page mode (column selection) can be operated, with access according to a Spaltenadreßhinweissignales / CAS carried out becomes.

The object of the invention is a To provide a semiconductor memory device with a novel structure, which is data reading and data writing at high speed allowed that especially for image data processing is suitable and data writing and enables data reading in and out of a DRAM without the cache data to influence. Moreover is intended to provide a method for driving a semiconductor memory device can be specified.

The task is solved by that characterized in claim 1, 2, 11, 12, 18, 19, 22, 24, 25 or 26 Contraption. The method is characterized in claim 14 or 15a, 17. The semiconductor memory device according to the invention has a DRAM with a plurality of dynamic memory cells, arranged in a matrix of rows and columns SRAM array with a plurality of static memory cells that are arranged in a matrix of rows and columns, and a Data transmission means for simultaneous execution a data transfer between a plurality of selected memory cells of the DRAM and a plurality of selected ones Memory cells of the SRAM array. The semiconductor memory device according to the invention further comprises a control means for independently executing an operation control, the relates to the DRAM field, and an operational control that relates to the SRAM field and a means of external and direct access the data transmission medium on.

Furthermore, the semiconductor memory device according to the invention a novel structure for the realization of various distinctive Functions.

In the semiconductor memory device according to the invention can the data transfer between the DRAM field and the SRAM field by using a page mode of the DRAM are executed to drive the DRAM field and the SRAM field independently of each other. Because direct access to the data transfer medium is possible (with in other words, writing data into it and reading it of data from the data transmission medium no over the SRAM field is executed) that, writing and reading data in the DRAM field without affecting the stored in the SRAM field Cache data are executed. Therefore can both the image data and the cache data are stored in the DRAM field become.

The following is a description of exemplary embodiments with reference to the figures. The refer to with reference to Fig. 164 to 171 . 177 to 187 and 207 to 216 described embodiments do not directly apply to the invention. From the figures show:

1 : A block diagram of the overall structure of a semiconductor memory device according to an embodiment of the invention;

2 : in tabular form the correspondence between the states of the control signals of the semiconductor memory device and the operating modes which are currently being executed;

3 : A signal diagram of the operation of the semiconductor memory device of 1 in an SRAM power save mode;

4 : A signal diagram of the operation of the semiconductor memory device of 1 in a SRAM decommissioning mode;

5 : a structure of the SRAM control area of the semiconductor memory device of FIG 1 ;

6 : an example of the structure of a buffer circuit in the semiconductor memory device of 1 that receives external signals;

7 : the structure of a buffer circuit in the semiconductor memory device of 1 which receives a chip activation signal;

8th : the signal diagram of an SRAM read mode of the semiconductor memory device of 1 ;

9 : the data flow in the SRAM read mode;

10 : the signal diagram of an SRAM write mode;

11 : the data flow in SRAM write mode;

12 : the signal diagram of a buffer read transfer mode;

13 : the data flow in the buffer read transfer mode;

14 : the signal diagram of a buffer write transfer mode;

15 : the data flow in the buffer write transfer mode;

16 : the signal diagram of a buffer read transfer / SRAM read mode;

17 : the data flow in the buffer read transfer and SRAM read mode;

18 : the signal diagram of a buffer write transfer and SRAM write mode;

19 : the data flow in the buffer write transfer and SRAM write mode;

20 : the signal diagram of a buffer read mode;

21 : the data flow in the buffer read mode;

22 : the signal diagram of the buffer write mode;

23 : the data flow in the buffer write mode;

24 : in tabular form the operations that the DRAM of the semiconductor memory device of 1 correspond, as well as the states of the control signals to implement these operations;

25 : the signal diagram of a DRAM power saving mode;

26 : the signal diagram of a DRAM-NOP mode;

27 : the signal diagram of a DRAM read transfer mode;

28 : the data flow in DRAM read transfer mode;

29 : the signal diagram of the DRAM write transfer mode;

30 : the data flow in DRAM write transfer mode;

31 : a structure for controlling the operations that the DRAM portion in the semiconductor memory device of 1 affect;

32 : a chip layout of the semiconductor memory device according to the first embodiment of the invention;

33 : the structure of the SRAM array area of the semiconductor memory device according to the first embodiment of the invention;

34 : the structure of the DRAM array area of the semiconductor memory device according to the first embodiment of the invention;

35 : the basic structure of a bidirectional data transmission circuit;

36 : A signal diagram of the principle of the data transfer process from the DRAM field to the SRAM field in the semiconductor memory device of 1 ;

37A - 37D : schematically shows the data transfer process from the DRAM field to the SRAM field in the semiconductor memory device according to the first embodiment of the invention;

38 : the data transfer process from the SRAM array to the DRAM array in the semiconductor memory device according to the first embodiment of the invention;

39A - 39D : schematically shows the data transfer process from the DRAM field to the SRAM field in the semiconductor memory device according to the first embodiment of the invention;

40 : the structure of an IO area of the semiconductor memory device according to the first embodiment of the invention;

41 : an example of the special structure of a bidirectional data transmission circuit in the semiconductor memory device according to the first embodiment of the invention;

42 : An example of an operation sequence in the semiconductor memory device according to the first embodiment of the invention;

43A and 43B : schematically the operation, which is indicated by the signal diagram of 42 is pictured;

44 : Another operation sequence of the semiconductor memory device according to the first embodiment of the invention;

45 : an example of the structure of a mask circuit for masking a transfer gate that transfers data to the DRAM array;

46 : an example of the circuit structure for generating set and reset signals, which in 45 is shown;

47 : schematically the operation of the masking circuit of 45 ;

48 : the signal diagram of a DRAM self-refresh mode;

49 : the signal diagram of a command register setting mode;

50 : in tabular form in the command register setting mode of 49 set command data and the content set at that time;

51 : the signal diagram of the operation of the masking circuit of 45 ;

52 : the signal diagram of the operation of the semiconductor memory device according to the first embodiment of the invention at the time of turning on;

53 : the structure of a portion associated with the instruction register setting mode of the semiconductor memory device according to the first embodiment of the invention;

54 : an example of another structure of the portion belonging to the instruction register setting mode of the semiconductor memory device according to the first embodiment of the invention;

55 : An example of an operation sequence of the semiconductor memory device that follows the circuit structure 54 used;

56 : An example of the manner of distributing address and command data to the command register and the address buffer in the semiconductor memory device according to the first embodiment form of the invention;

57 : an example of the structure of the data input / output section in the semiconductor memory device according to the first embodiment of the invention;

58 : an example of the structure of the input circuit and the input control circuit of 57 ;

59 : an example of the structure of the output circuit of 57 ;

60 : a specific example of the structure of the latch circuit of 59 ;

61 : an example of the structure of the output control circuit of 57 ;

62 : the signal diagram of a latch output mode;

63 : the signal diagram of a register output mode;

64A and 64B : Signal diagrams of a transparent output mode;

65A and 65B : Output clocks of the output data in the transparent output mode;

66A and 66B : Output clocks of the output data in the register output mode;

67A and 67B : Output clocks of the output data in the latch output mode;

68 : required conditions of external signals of the semiconductor memory device according to the first embodiment of the invention;

69 : Shape and connection arrangement of a housing which accommodates the semiconductor memory device according to the first embodiment of the invention;

70 : the overall structure of a semiconductor memory device according to a second embodiment of the invention;

71 : a structure for the K buffer and the masking circuit of 70 ;

72 : an example of the structure of the DRAM control circuit and the SRAM control circuit of 70 ;

73 : a structure of the data input / output section of the semiconductor memory device of 70 ;

74 : an example of a data output operation sequence of the semiconductor memory device according to the second embodiment of the invention;

75 : an example of the structure of a memory system in the semiconductor memory device according to the second embodiment of the invention;

76 : Advantages of DQ control used in the semiconductor memory device according to the second embodiment of the invention;

77 : the correspondence between the cache and the main memory of the storage system of 76 ;

78 : a structure when a memory system having a bank structure is formed using the semiconductor memory device according to the second embodiment of the invention;

79 : the correspondence between the cache and the main memory of the storage system of 78 ;

80 : an example of the structure of a memory system in the semiconductor memory device according to the second embodiment of the invention;

81 : the correspondence between the cache and the main memory of the storage system of 80 ;

82 : a structure for generating the DQ control signal when the in 80 shown storage system is formed;

83 : the functional structure of the semiconductor memory device according to the second embodiment of the invention;

84 : an example of the structure of the bidirectional data transmission circuit in the semiconductor memory device according to the second embodiment of the invention;

85 : in tabular form the correspondence between the states of the control signals belonging to the SRAM area of the semiconductor memory device and the operation which is being realized at this time, according to the second embodiment of the invention;

86 : the data flow in the SRAM read mode;

87 : the data flow in SRAM write mode;

88 : the data flow in the buffer read transfer mode;

89 : the data flow in the buffer write transfer mode;

90 : the data flow in the buffer read transfer and read mode;

91 : the data flow in the buffer write transfer and write mode;

92 : the data flow in the buffer read mode;

93 : the data flow in the buffer write mode;

94 : in table form the correspondence between the operations corresponding to the DRAM field and the control signals for realizing these operations;

95 : the data flow in DRAM read transfer mode;

96 : the signal diagram of the operation at the time of setting the DRAM write transfer mode;

97 : an example of the structure of a data processing system using the semiconductor memory device according to the second embodiment of the invention;

98 : the data flow in DRAM write transfer mode 1 ;

Fig. 99 : the data flow in DRAM write transfer mode 1 / Reading mode;

Fig. 100 : the signal diagram of a DRAM read transfer mode;

Fig. 101 : the signal diagram of the DRAM write transfer mode;

Fig. 102 : an example of a circuit structure for generating a control signal for controlling the operation of a bidirectional data transmission circuit in a semiconductor memory device according to the second embodiment of the invention;

Fig. 103 : An example of an operation sequence of the semiconductor memory device according to the second embodiment of the invention;

Fig. 104A and 104B : schematically the data flow in DWT1 mode and in DWT2 mode from Fig. 102 ;

Fig. 105 : a diagram showing the effect of DWT2 mode from Fig. 104 represents;

Fig. 106 : the connection state with a tester when the semiconductor memory device is checked for its function;

Fig. 107 : the state of external control signals in a command register setting mode in the semiconductor memory device according to the second embodiment of the invention;

Fig. 108 : a structure of the command data contained in Fig. 107 are shown;

Fig. 109 : in tabular form the correspondence between the in Fig. 108 command data shown and the operating modes defined at this time;

Fig. 110 : a structure of the circuit system that supports the internal operation of the semiconductor memory device according to the in Fig. 108 controls command data shown;

Fig. 111 : an example of the structure of a data processing system using the semiconductor memory device according to the second embodiment of the invention;

Fig. 112 : the flowchart of a data reading sequence provided that no assignment is made in the write-back mode of the semiconductor memory device according to the second embodiment of the invention;

Fig. 113 : the flowchart of a data write sequence provided that no assignment is made in the write-back mode of the semiconductor memory device according to the second embodiment of the invention;

Fig. 114 the flowchart of a data reading sequence on condition that an assignment is made in the write-back mode of the semiconductor memory device according to the second embodiment of the invention;

Fig. 115 : the flowchart of a data write sequence with a write-back mode assignment of the semiconductor memory device according to the second embodiment of the invention;

Fig. 116 : the flowchart of the data reading sequence with a write-through mode assignment of the semiconductor memory device according to the second embodiment of the invention;

Fig. 117 : the flowchart of the data write sequence with a write-through mode assignment of the semiconductor memory device according to the second embodiment of the invention;

Fig. 118 : the flowchart of the data reading sequence provided that no write-through mode assignment of the semiconductor memory device according to the second embodiment of the invention is made;

Fig. 119 : the flowchart of the data write sequence under the condition that there is no assignment in the write-through mode of the semiconductor memory device according to the second embodiment of the invention;

Fig. 120 : an example of the structure of the bidirectional data transmission circuit in the semiconductor memory device according to the second embodiment of the invention;

Fig. 121 : the data flow in the buffer write mode of the semiconductor memory device according to the second embodiment of the invention;

Fig. 122 : the data flow in the DRAM write transfer mode of the semiconductor memory device according to the second embodiment of the invention;

Fig. 123 : a signal diagram of the setting and resetting operations of the masking register in the semiconductor memory device according to the second embodiment of the invention;

Fig. 124 : A signal diagram of the setting / resetting process of the masking data of the masking register in the semiconductor memory device according to the second embodiment of the invention;

Fig. 125 : the specific structure of a write data transfer buffer circuit in the bidirectional data transfer circuit used in the semiconductor memory device according to the second embodiment of the invention;

Fig. 126 : A signal diagram of the operation of the write data transfer buffer circuit of Fig. 125 ;

Fig. 127 : the specific structure of a read data transfer buffer circuit in the bidirectional data transfer circuit used in the semiconductor memory device according to the second embodiment of the invention;

Fig. 128 : A signal diagram of the operation of the read data transfer buffer circuit of Fig. 127 ;

Fig. 129 : a structure for generating control signals which are in the transfer buffer circuits of Fig. 125 and 127 to be used;

Fig. 130 : the chip arrangement of the CDRAM according to a third embodiment of the invention;

Fig. 131 : the internal functional structure of the CDRAM according to the third embodiment of the invention;

Fig. 132 : external control signals of the CDRAM from Fig. 131 and commands set accordingly;

Fig. 133 : in tabular form external tax sig nale of the CDRAM from Fig. 131 and operations performed accordingly;

Fig. 134 : a signal diagram of the data read operation of the CDRAM from Fig. 131 ;

Fig. 135 : a signal diagram of the data read operation of the CDRAM from Fig. 131 ;

Fig. 136 : a signal diagram of the data read operation of the CDRAM from Fig. 131 ;

Fig. 137 : a signal diagram of the data read operation of the CDRAM from Fig. 131 ;

Fig. 138 : a signal diagram of the data read operation of the CDRAM from Fig. 131 ;

Fig. 139 : a signal diagram of the data read operation of the CDRAM from Fig. 131 ;

Fig. 140 : a signal diagram of the data read operation of the CDRAM from Fig. 131 ;

Fig. 141 : a signal diagram of the data read operation of the CDRAM from Fig. 131 ;

Fig. 142 : a signal diagram of the data read operation of the CDRAM from Fig. 131 ;

Fig. 143 : a signal diagram of the data write operation of the CDRAM from Fig. 131 ;

Fig. 144 : a signal diagram of the data write operation of the CDRAM from Fig. 131 ;

Fig. 145 : a signal diagram of the data write operation of the CDRAM from Fig. 131 ;

Fig. 146 : a signal diagram of the data write operation of the CDRAM from Fig. 131 ;

Fig. 147 : a signal diagram of the operating sequence when switching on the CDRAM from Fig. 131 ;

Fig. 148 : a signal diagram of the operation of the CDRAM from Fig. 131 with a CPU reset;

Fig. 149 : a signal diagram of the operation of the CDRAM from Fig. 131 in sleep mode;

Fig. 150 : a signal diagram of the operation when the CDRAM of Fig. 131 released from sleep mode;

Fig. 151 : a signal diagram of the CDRAM instruction register read / write operation of Fig. 131 ;

Fig. 152 : a state transition of the CDRAM from Fig. 131 ;

Fig. 153A and 153B : a truth table of external control signals for performing CDRAM instruction register read / write and CDRAM instruction register read / write operation of Fig. 131 ;

Fig. 154 : Function and structure of the command register 00h;

Fig. 155 : Function and structure of the command register 01h;

Fig. 156 : Function and structure of the command register 02h and 03h;

Fig. 157 : Function and structure of the command register 04h and 05h;

Fig. 158 : Function and structure of the command register 06h and 07h;

Fig. 159 : Function and structure of the command register 10h and 16h;

Fig. 160 : Function and structure of the command register 17h and 1ch;

Fig. 161 : Latencies in a table when reading / writing the CDRAM from Fig. 131 ;

Fig. 162 : various parameters of the input signals to the CDRAM from Fig. 131 ;

Fig. 163 : various parameters of the CDRAM output signals from Fig. 131 ;

Fig. 164 : the structure of a memory system formed by the CDRAM;

Fig. 165A and 165B : Schematic structure and operation of a data signal output section of the CDRAM from Fig. 164 ;

Fig. 166 : the structure of an improved signal output section of the present invention;

Fig. 167 : a signal diagram of the operation of the signal output section of FIG Fig. 166 ;

Fig. 168 : a circuit structure for generating the control signals from Fig. 166 ;

Fig. 169 : a modification of the circuit of Fig. 168 ;

Fig. 170 : a signal diagram of the operation of the circuit of Fig. 169 ;

Fig. 171 : a signal diagram of the operation when a special mode is set;

Fig. 172 : a signal diagram of the operation when a special mode is set;

Fig. 173 : the structure of a test mode setting circuit;

Fig. 174 : another structure for the test mode setting circuit;

Fig. 175 : an example of the structure of the counter used in Fig. 173 and 174 is shown;

Fig. 176 : a signal diagram of the operation of the counter of Fig. 175 ;

Fig. 177 : the structure of a memory system with a synchronous self-refresh function according to the present invention;

Fig. 178 : Structures of sections that refresh the CDRAM from Fig. 177 affect;

Fig. 179 : a signal diagram of the operation of the master section of Fig. 178 ;

Fig. 180 : a signal diagram of the operation of the slave portion of Fig. 178 ;

Fig. 181 : a structure for generating the precharge completion signal of Fig. 178 ;

Fig. 182 : a signal diagram of the operation of the circuit of Fig. 181 ;

Fig. 183 : a modification of the circuit of Fig. 181 ;

Fig. 184 : an example of the structure of the first arbiter of Fig. 178 ;

Fig. 185 : an example of the structure of the second arbiter of Fig. 178 ;

Fig. 186 : an example of the structure of the RAS buffer and the refresh control circuit of Fig. 178 ;

Fig. 187 : the structure of another embodiment of the refresh control system;

Fig. 188 : Another example of the structure of the storage system with the synchronous self-refresh function;

Fig. 189 : an example of the data transfer process between the DRAM field and the SRAM field;

Fig. 190 : a second step of the data transfer process between the DRAM field and the SRAM field;

Fig. 191 : a third step of the data transfer process between the DRAM field and the SRAM field;

Fig. 192 : a fourth step of the data transfer process between the DRAM field and the SRAM field;

Fig. 193 : a fifth step of the data transfer process between the DRAM field and the SRAM field;

Fig. 194 : a sixth step of the data transfer process between the DRAM field and the SRAM field;

Fig. 195 : a seventh step of the data transfer process between the DRAM field and the SRAM field;

Fig. 196 : an eighth step of the data transfer process between the DRAM field and the SRAM field;

Fig. 197 : a ninth step of the data transfer process between the DRAM field and the SRAM field;

Fig. 198 : a tenth step of the data transfer process between the DRAM field and the SRAM field;

Fig. 199 : an eleventh step of the data transfer process between the DRAM field and the SRAM field;

Fig. 200 : a twelfth step of the data transfer process between the DRAM field and the SRAM field;

Fig. 201 : a signal diagram of the data transfer sequence between the DRAM field and the SRAM field;

Fig. 202 : the data transmission sequence between the DRAM field and the SRAM field;

Fig. 203 : a signal diagram of the data transfer process between the DRAM field and the SRAM field;

Fig. 204 : a signal diagram of the data transfer process between the DRAM field and the SRAM field;

Fig. 205 : an example of the correspondence between the read transfer command and the external control signals;

Fig. 206 : Another example of the structure of the data transmission circuit from the SRAM field to the DRAM field;

Fig. 207 : an example of an image processing system using the CDRAM according to the present invention;

Fig. 208 : schematically the operation of the image processing system of Fig. 207;

Fig. 209 : a signal diagram of the access sequence of the CDRAM in the image processing system of Fig. 207 ;

Fig. 210 : a signal diagram of the access sequence of the CDRAM in the image processing system of Fig. 207 ;

Fig. 211 : a signal diagram of the sequence of operations when writing video data in the CDRAM;

Fig. 212 : a signal diagram of the video data write to CDRAM and DRAM;

Fig. 213 : a signal diagram of the operation for reading video data from the SRAM and CDRAM;

Fig. 214 : a signal diagram of the operation for writing video data into the SRAM and CDRAM;

Fig. 215 : a signal diagram of the read-modify-write operation for video data for the SRAM and CDRAM;

Fig. 216 : a signal diagram of the operation for writing video data into the SRAM / DRAM and CDRAM;

Fig. 217 : the overall structure of a semiconductor memory device with a cache;

Fig. 218 : a structure of the main portion of the semiconductor memory device of FIG Fig. 217 ;

Fig. 219 : a signal diagram of the operational sequence of the semiconductor memory device with a cache;

Fig. 220 : schematically the data transfer in the semiconductor memory device with a cache; and

Fig. 221 : An Example of the Structure of a Data Processing System with a Display Using a Semiconductor Memory Device with a Cache.

1 FIG. 12 shows a block diagram of the overall structure of a semiconductor memory device according to a first embodiment of the invention. The semiconductor memory device has a DRAM section and an SRAM section, which is used as a cache memory. The semiconductor memory device is therefore referred to in the following description as a semiconductor memory device with a cache (CDRAM).

As in 1 is shown, the DRAM 100 a DRAM field 102 with a plurality of dynamic memory cells arranged in a matrix of rows and columns, an SRAM field 104 with a plurality of static memory cells arranged in a matrix of rows and columns, and a data transmission circuit 106 for transferring data between the DRAM field 102 and the SRAM field 104 on. The CDRAM 100 has a structure that enables input / output of data of four bits each. Therefore, the DRAM field includes 102 four storage levels 102 . 102b . 102c and 102d , The storage levels 102 to 102d of the DRAM field correspond to different ones of the data bits that are input / output at once.

The SRAM field 104 similarly has four levels of memory 104a . 104b . 104c and 104d on. Also the data transmission circuit 106 comprises four levels 106a . 106b . 106c and 106d to move data layer by layer between the storage layers 102 to 102d of the DRAM field and the memory layers 104a to 104d the SRAM field to transmit. The CDRAM 100 has a DRAM address buffer 108 , which receives externally applied DRAM addresses Ad0 to Ad11 for generating internal addresses, a row decoder 110 , the internal row addresses ROW1 to ROW11 from the DRAM address buffer 108 to select a corresponding line of the DRAM field 100 receives a column decoder 112 which receives predetermined bits of the internal column address signals from the DRAM address buffer, ie column block addresses Col1 to 9 for simultaneously selecting a plurality of columns ( 16 Bits of memory cells in this embodiment) in the DRAM array, a sense amplifier for detecting and amplifying data of the memory cells selected in the DRAM array, and an IO controller for transferring data between the selected memory cell in the DRAM array 102 and the data transfer circuit to drive the DRAM array. In 1 are the sense amplifier and the IO controller as one block 114 shown.

The DRAM address buffer 108 receives the row and column addresses in a multiplexed manner. Four data bits of addresses Ad0 to Ad3 are used as commands to set the data transfer mode in the data transfer circuit and to set / reset the masking data when masking is to be performed.

The CDRAM 100 also has an SRAM address buffer 116 , which receives externally applied SRAM address signals As0 to As11 for generating internal addresses, a row decoder 118 , the addresses As4 to As11 from the SRAM address buffer 116 decoded to select a corresponding line in the SRAM field 104 , a column decoder 120 for decoding the column addresses As0 to As3 from the SRAM address buffer 116 to a corresponding column in the SRAM field 104 and a corresponding transfer gate of the data transmission circuit 106 to select, and an IO circuit for acquiring and amplifying data from the selected memory cell of the SRAM array 104 and to connect the selected column of the SRAM array 104 and the selected gate with an internal data bus by an output signal from the column decoder 120 on.

The sense amplifier and the IO circuit for the SRAM are as one block 122 shown. A line of the SRAM field 104 comprises 16 bits. The data transfer is simultaneously between 16 bits of a selected row of the SRAM field and the data transfer circuit 106 with 16 transfer gates. Namely, in the CDRAM, 16 bits of data are transferred for one memory level, and therefore a total of 64 data bits can be transferred at the same time.

The CDRAM also has a K buffer 124 a clock signal masking circuit for receiving an externally applied clock signal K, which represents, for example, a system clock signal, for generating an internal clock signal 126 to provide a masking function for the internal clock signal from the K buffer 124 in accordance with an external applied mask signal CMd, a DRAM control circuit 128 , the externally applied control signals RAS #, CAS # and DTD # in synchronism with the clock signal from the clock signal masking circuit 126 takes over a clock signal masking circuit for generating the necessary control signals according to the states of the respective signals 130 to provide a masking function for the internal clock signal from the K buffer 124 in accordance with an external applied control signal CMs, an SRAM control circuit 132 for taking on externally applied control signals E #, WE #, CC1 # and CC2 # in accordance with the internal clock signal from the clock signal masking circuit 124 , for generating a control signal for controlling the operation of the data transmission circuit 106 , of the SRAM field 104 and a later described input / output section corresponding to the combinations of the states of the respective control signals, a main amplifier circuit 130 , which is activated synchronously with an externally applied control signal G #, for generating an external read value from the value on the internal data bus 123 , a din buffer circuit 134 for taking over external write data in synchronism with the clock signal under the control of the SRAM control circuit 132 for generating internal write data, and a mask setting circuit 136 for accepting externally applied masking data for performing a masking function with regard to the transfer of the write data from the Din buffer circuit 134 to the internal data line 123 on. The mask setting circuit 136 also takes over the masking data in synchronism with the clock signal under the control of the SRAM control circuit 132 ,

The CDRAM 100 can change the structure of data input / output. It has a DQ separation structure in which input data (write data) D and output data Q are transmitted via different connections, and a masking write mode in which write data D and read data (output data) Q are transmitted via the same connections. A masking of the write data is only possible in the masking write mode, in which the data input and the data output is carried out via the same connections. Ports to which write data D0 to D3 are applied in the DQ separation arrangement are used in the mask write mode as ports for receiving mask data (mask activations) M0 to M3.

Although this is shown in the drawings of the For the sake of simplicity, the setting of the connections executed by a command register that later is described.

[Definition of external Control signals]

When in 1 CDRAM shown 100 the input of data and the acceptance of the external control signals are carried out synchronously with the external clock signal K. The external control signals are all supplied in the form of pulses. The operating mode is determined as a function of the combinations of the states of the external control signals with the rising edge of the external clock signal. The input of the external control signal G # is carried out asynchronously to the clock signal K. Various external control signals are described below.

Master clock signal K: The master clock signal K sets the basic clocking, ie the clock positions for accepting the input signals, and the operating clock frequency of the CDRAM 100 firmly. The clock signal parameters of the respective necessary external signals (except G #, which will be described later) are defined using the rising or falling edge of the master clock signal K as a reference.

DRAM clock mask signal CMd: The DRAM clock mask signal CMd controls the transfer of the internal DRAM master clock signal from the K buffer 124 is produced. If the DRAM clock mask signal is in an active state with the rising edge of the external clock signal K, the generation of the internal DRAM master clock signal is interrupted in the next clock cycle. Accordingly, the operation for taking over the control signals of the DRAM section is interrupted in the next cycle, whereby the power consumption in the DRAM section is reduced.

Row address strobe signal RAS #: The row address strobe signal RAS # is used with the master clock signal K (depending on the states of the signals CMd, CAS # and DTD # at this time) to activate the DRAM section. More specifically, it triggers the locking of the DRAM row address, the selection of a row in the DRAM 102 and the start of a precharge cycle for setting the DRAM portion to the initial state, and it may also for transferring data between the DRAM and the data transfer circuit, setting the data in the instruction registers, starting the self-refresh cycle, generating a DRAM-NOP cycle, and interrupting operation (power saving state) of the DRAM section can be used. Namely, the row address strobe signal RAS # defines the basic duty cycle in the DRAM section.

Column address strobe signal CAS #: The column address strobe signal CAS # is used together with the master clock signal K to lock the Column address for uses the DRAM. If in the DRAM access cycle previously the row address strobe signal RAS # has been created by the successively created Column address strobe signal CAS # the data transfer from the data transmission circuit to the DRAM field or from the DRAM field to the data transmission circuit accordingly a control signal DTD # executed, that later is described.

Data transfer determination signal DTD #: The data transfer determination signal DTD # places the data transfer and its direction between the DRAM field 102 and the data transmission circuit 106 firmly. If the row address strobe signal RAS # was "L" in the previous cycle, a DRAM write transfer cycle is performed in which data is transferred from the data transfer circuit to the DRAM array; when the column address strobe signal CAS # and the data transfer determination signal DTD # are both at "L" with the rising edge of the master clock signal K. When the data transfer determination signal DTD # is "H", data transfer from the DRAM field to the data transfer circuit is carried out. When the data transfer designation signal DTD # falls to "L" in synchronism with the row address strobe signal RAS #, the DRAM enters the precharge mode and access to the entire DRAM section is blocked until the precharge cycle is completed.

DRAM addresses Ad0 to Ad11: The DRAM field 102 has a storage capacity of 16MBit (16 MegaBits). A DRAM memory layer has a structure with 4k rows x 64 columns x 16 blocks. The DRAM address bits Ad0 to Ad11 are supplied as DRAM row addresses and DRAM column addresses in a multiplexed manner. When the row address strobe signal RAS # is "L" with the rising edge of the master clock signal K, the DRAM address bits Ad0 to Ad11 are adopted as the row address, which determines a row of the DRAM field. When the column address strobe signal CAS # is "L" with the rising edge of the master clock signal K, the DRAM address bits Ad4 to Ad9 are used as the block address for specifying 16 bits of memory cells (one bit of each of the 16 blocks). When the row address strobe signal RAS # is "L" with the rising edge of the master clock signal K, the refresh address can be set when refreshing is instructed.

SRAM clock mask signal CMs: The SRAM clock mask signal CMs controls the transfer of an internal SRAM master clock signal (that from the K buffer 124 is produced). When the SRAM clock mask signal is in an active state with the rising edge of the master clock signal K, the internal SRAM master clock signal is turned off in the next clock cycle and the SRAM section maintains the state of the previous cycle. The SRAM clock mask signal is also used to continuously hold the same input / output data.

Chip activation signal E #: The chip activation signal E # controls the operation of the SRAM section. If the chip activation signal E # with the rising edge of the master clock signal K at "H" the SRAM section is in this cycle to an unselected state (wait state) set. If the chip activation signal E # increases with the Edge of the master clock signal K (provided the SRAM clock mask signal is "L" in the previous cycle), the SRAM section in activated this cycle. When the output enable signal (described later) G # is at "L", the chip activation signal E # controls the output impedance, and it can write and read data in a common IO structure accomplished become.

Write enable signal WE #: The write enable signal WE # controls the write and read processes in the SRAM section and the Data transmission circuit. When the chip activation signal E # with the rising edge of the master clock signal K is at "L", reading data from the data transmission circuit executed. There will be a reading of data from the SRAM field and / or a data transfer from the data transmission circuit to the SRAM field, if the write activation signal WE # is at "H" (depending on the states of the control signals CC1 # and CC2 #, which will be described later). If the write activation signal WE # is "L" at this time data is written into the data transmission circuits, writing data to the selected memory cells of the SRAM array or a transfer of data from the SRAM field to the data transmission circuit (depending on the control signals CC1 # and CC2 #).

Control clock signals CC1 # and CC2 #: These control clock signals CC1 # and CC2 # control access to the SRAM section and access to the data transmission circuit. If the chip activation signal E # with the rising edge of the Master clock signal K is at "L", the operating mode to be executed determined by the control clock signals CC1 # and CC2 #. Hereinafter the operating mode is briefly described. The details will be explained later.

CC1 # = CC2 # = "L": There is a buffer read / write cycle (WE # = H / L) executed, and reading data from the data transmission circuit, respectively Writing data into the data transmission circuit is carried out.

CC1 # = "L" and CC2 # = "H": It will a buffer read / write transfer cycle and an SRAM read / write cycle (WE # = H / L) executed. In this cycle will be a data transfer between the data transmission circuit and the SRAM field and reading or writing data from the or carried out in the SRAM field. The write operation or read operation is determined depending on whether the write enable signal WE # is at "H" or "L".

CC1 # = "H" and CC2 # = "L": It will a buffer read / write transfer cycle (WE # = H / L) executed. It is a data transfer performed between the SRAM array and the data transmission circuit.

CC1 # = CC2 # = "H": It is an SRAM read / write cycle (WE # = H / L) executed. A data read / write operation is carried out for the SRAM field.

SRAM addresses As0 to As11: The SRAM field has four memory levels, each memory cells in 256 Rows and 16 columns. If the SRAM field as cache is used the block size of the cache 16 x 4 (4 bits for the Input / Output). The SRAM address bits As0 to As3 are used as a block address for selecting a bit in a cache block used while the SRAM address bits As4 to As11 as the row address for selecting a row in the SRAM field be used.

Output enable signal G #: The Output enable signal G # becomes asynchronous to the master clock signal K fed. If the output activation signal G # reaches the "H" level, the Output in one state in both DQ disconnect mode and DQ mode high impedance offset.

Input / output data DQ0 to DQ3: The input / output data DQ0 to DQ3 represent the data of the CDRAM if DQ mode is selected by the command register. The status of the respective values is determined by the output activation signal G # controlled asynchronously to the master clock signal K. The output of Data is dependent on Contents of the command register (described later) in one transparent mode, latch mode or register mode.

Input signals D0 to D3: These are Input data when DQ separation mode is selected by the command register. When writing data, e.g. in the write buffer cycle or write SRAM mode the input data D0 to D3 with the rising edge of the master clock signal K locked.

Mask activation signals M0 to M3: These signals are activated when the DQ mode is set by the command register. The mask activation signals correspond to M0 to M3 the input / output data DQ0 to DQ3 and determine whether the corresponding DQ bit should be masked or not. The setting of the masking data is determined by the states of the mask activation signals M0 to M3 with the rising edge of the master clock signal K. When writing data into the data transmission circuit or the SRAM field in the SRAM write cycle or buffer write cycle, the desired input data can be masked.

As can be seen from the above description of the control signals, the control of the operations related to the DRAM section and the control of the operations related to the SRAM section of the CDRAM 100 concern, executed independently. Direct data writing into and direct data reading from the data transmission circuit is possible. Therefore, the DRAM section and the SRAM section can be driven independently to simplify the control. Data transmission using a high speed mode such as the page mode of the DRAM can be implemented, the access time in the event of a cache miss can be reduced and a burst mode (block mode) can be implemented.

Because the data transmission circuit 106 can be directly addressed externally, in the SRAM field 104 stored data is not influenced at all by direct access from the outside to the data transmission circuit. Therefore, both image data and cache data (data used by the CPU which is an external processing unit) can be in the DRAM field 102 get saved.

As in Fig. 1 is shown, the data transmission circuit 106 16 transfer gates on. Each transfer gate has a read transfer buffer for transferring data from the DRAM field 102 to the SRAM field or an input / output section, an intermediate register 142 for storing write data of the SRAM field 104 or the internal data bus 123 , a write transfer buffer 144 for transferring data in the intermediate register 142 are stored, to the DRAM field, and a mask register 146 to mask the data transfer from the write transfer buffer 144 to the DRAM field.

As in 1 is shown, the CDRAM receives 100 the ground potential Vss and the supply potential Vcc. The supply potential Vcc or an internally lowered supply potential can be used as the internal operating supply voltage of the CDRAM. Various operations that can be performed by the CDRAM are described below, followed by a detailed description of the structures of various sections of the CDRAM.

2 shows in a table the states of the control signals for specifying operations relating to the SRAM section. 2 shows the states of various control signals for the rising edge of the master clock signal K and operating cycles (operating modes) that are currently being executed. In 2 the reference symbol "X" represents any state. As from 2 it can be seen, the states of the control signals CMd, RAS #, CAS # and DTD #, which control the processes which relate to the DRAM field, are not defined, but are set arbitrarily if an operation relating to the SRAM field is to be controlled. The control of the processes that affect the SRAM field is carried out by the in 1 SRAM control circuit shown 132 executed. The SRAM array operating cycles include an SRAM power save cycle to interrupt a cycle of the SRAM master clock signal, an SRAM decommission cycle to put the output section in a high impedance state, an SRAM read cycle to read data from the SRAM array and an SRAM write cycle for writing data to the SRAM array.

The operations related to the SRAM section also include a buffer read transfer cycle, a buffer read transfer and read cycle, and a buffer write transfer and write cycle for transferring data between the SRAM array and the data transfer circuit, a buffer read cycle, and a buffer write cycle for direct access to the data transfer circuit on. Each of the operating cycles described in 2 are specified.

[SRAM System]

[SRAM power saving mode]

In the SRAM power saving cycle, the SRAM master clock signal is interrupted for the period of a cycle. There is no transfer of control signals into the SRAM control circuit 132 executed synchronously to the clock signal. The SRAM sense amplifier maintains the state of the previous cycle. The output buffer remains in the state at this time. Data can be output continuously.

For the SRAM power-saving cycle, the SRAM clock mask signal CMs is set to "H" with a rising edge of the master clock signal K. In the next clock cycle, the SRAM enters the SRAM power saving cycle. When the SRAM clock mask signal CMs with the rising edge of the master clock signal K is at "L" and the chip activation signal E # is set at "L", and both the write activation signal WE # and the control clock signals CC1 # and CC2 # with the rising Edge of the master clock signal K of the following cycle are at "H", the SRAM read mode is set. In this case, the data of the SRAM with the rising edge of the next master clock signal K read. The data read at this time is continuously output when the SRAM power saving mode is active at this time.

As in 3 is shown, the SRAM power saving mode begins more specifically from the second cycle of the master clock signal K, when SRAM clock mask signal CMs is "H" in the first cycle of the master clock signal K. In the first cycle of the master clock signal K, the SRAM has not yet entered the power-saving mode, and therefore the SRAM read mode is determined at this time depending on the combination of the chip activation signal E #, the write activation signal WE # and the control clock signals CC1 # and CC2 #. the selection of the memory cell in the SRAM field is carried out according to the SRAM addresses As0 to As11, which at this time are the SRAM address buffer 116 are supplied, and the data of the selected memory cell are set with the rising edge of the master clock signal K. Because the SRAM enters the power saving mode from the second cycle of the master clock signal K and the SRAM master clock signal is not supplied, the internal operation is stopped and its state is maintained. The output buffer (main amplifier) maintains this state until the next SRAM master clock signal is applied, and therefore the value Q1, which has set itself on the rising edge of the second cycle of the master clock signal K, is continuously output.

By adjusting the SRAM clock mask signal CMs on "L" will be on the rising edge of the fourth cycle of the master clock signal K the SRAM from the rising edge of the fifth cycle of the next master clock signal K released again from the power saving mode.

The SRAM read cycle is determined again by combining the states of the chip activation signal E #, the write activation signal WE # and the control clock signals CC1 # and CC2 # with the rising edge of the fifth cycle of the master clock signal K. Because the SRAM has been released from the power saving mode in the fifth cycle of the master clock signal K, the output buffer (the main amplifier in 1 ), which until now has continuously output the same value Q1, once put into a high impedance state by applying the clock signal K The timing for the occurrence of the output data will be described in detail later.

Corresponding to the SRAM addresses As0 to As11, the fifth Cycle of the master clock signal K are applied, memory cells selected in the SRAM field and data are selected from the Read memory cells.

With the rising edge of the sixth cycle of the master clock signal K, the output value Q is set to a stable state. With the rising edge of the fifth cycle of the master clock signal K is the SRAM clock mask signal CMs at "H", and that by the sixth cycle of the master clock signal K defined cycle is subjected to the power saving mode. Corresponding the output value Q2 is output continuously. That state is maintained as long as the SRAM clock mask signal CMs is on "H". By lowering the SRAM clock mask signal CMs on "L" with the rising edge of the 13th cycle of the master clock signal K is in 14th cycle of the master clock signal the SRAM from power saving mode Approved. This puts the output Q in a high impedance state.

As described above can be done by using the SRAM power save mode the operation of the SRAM section is stopped and the current draw due to the operation in synchronism with the clock signal K can in the SRAM section can be reduced.

[SRAM-aside mode]

The SRAM shutdown cycle offsets the output buffer (main amplifier 138 in 1 ) in a state of high output impedance. For the SRAM set mode, the SRAM clock mask signal CMs is set to "L" with the rising edge of the master clock signal K, and the chip activation signal E # is set to "H" with the rising edge of the next master clock signal K. Thus, it takes the SRAM decommissioning mode from the next cycle, the data transmission and the data input / output of the SRAM field are deactivated, and it assumes a state corresponding to a high output impedance. The SRAM quiesce mode allows the output impedance to be placed in the high output impedance state, with the SRAM region effectively in an unselected state (non-operational state). Therefore, erroneous overwriting of data in the SRAM that was read in the previous cycle can be prevented when switching from data reading to data writing operation, and erroneous data writing due to a collision of newly created write data and the read data can be avoided.

As in the signal diagram of the 4 is shown, the SRAM clock mask signal CMs is on the rising edge of the first cycle of the master clock signal K at "L". At this time, the chip activation signal E # is at "L" and the write activation signal WE # and the control clock signals CC1 # and CC2 # are at "H". therefore, the SRAM read mode is set. The SRAM address bits As0 to As11 applied in the first cycle of the master clock signal K are adopted, and the value Q1 of the memory cell corresponds to the address (in 4 as C1) is read.

If the chip activation signal E # in the second cycle of the master clock signal K is raised to "H", the SRAM enters the SRAM decommissioning mode on. In this state, the SRAM section is set to the unselected state and the output is in the third cycle of the master clock signal K placed in a high impedance state.

When the chip activation signal E # drops to "L", the SRAM decommissioning mode is released, the SRAM read mode is controlled according to the states of the other control signals WE #, CC1 # and CC2 # at this time, data is processed according to the SRAM currently applied Address (C2 in 4 ) is read and the output value Q2 is output.

If E # in the sixth cycle of the master clock signal K reaches the "H" level, the SRAM occurs from the fifth cycle of the master clock signal K in the SRAM decommissioning mode. The SRAM decommissioning mode is maintained as long as the chip activation signal E # is at "H" (provided that SRAM clock mask signal CMs is at "L"), and the state high output impedance is maintained.

More specifically, the SRAM decommissioning mode the SRAM section for the period of one cycle of the master clock signal K in the unselected state added.

5 shows the structure of the sections relating to the SRAM power saving mode and the SRAM decommissioning mode. In the 5 The structure shown corresponds to the structure of the SRAM control circuit 132 and the main amplifier 138 the clock signal masking circuit 130 in the structure of 1 , As in 5 is shown, the SRAM control circuit 132 a K buffer that receives the master clock signal K and generates an internal clock signal Ki, and a masking circuit 130 , which is dependent on the internal clock signal Ki and the SRAM clock mask signal CMs, for generating an SRAM master clock signal SK.

The masking circuit 130 has a shift register 152 , which is dependent on the internal clock signal Ki, for achieving a delay of one clock cycle period for the SRAM clock mask signal CMs and a gate circuit 164 that from the clock mask signal CMsR from the shift register 152 is dependent on the selective passage of the internal clock signal Ki. The gate circuit 164 is formed, for example, by a transfer gate with a p-channel MOS transistor. When the clock mask signal CMsR is "H", the transmission of the internal clock signal Ki is blocked. The gate circuit 164 can be formed using a logic gate. The SRAM master clock signal SK is from the masking circuit 130 generated.

The SRAM control circuit 132 has an E buffer 154 , which is dependent on the SRAM clock signal SK, for locking the chip activation signal E #, a WE buffer 156 , which is dependent on the SRAM master clock signal SK and the internal chip activation signal E on the E buffer, for locking the write activation signal WE # and generating an internal write activation signal WE and a CC1 buffer 158 and a CC2 buffer 160 , which are dependent on the internal chip activation signal E and the SRAM master clock signal SK, for generating internal control clock signals CC1 and CC2.

The SRAM control circuit 132 also has a control signal generating circuit 166 on, which is activated in dependence on the internal chip activation signal E by the E buffer, the clock position of which is defined by the SRAM master clock signal SK, for generating the necessary control signals in accordance with combinations of the states of the write activation signal WE and the control clock signals CC1 and CC2 from the buffers 156 . 158 and 160 are fed.

The control signal generating circuit 166 generates a driver control signal for driving the SRAM array and a data transfer control signal for driving the data transfer circuit. In data transmission between the SRAM array and the data transmission circuit, the time period of the transmission is determined by the master clock signal in order to transmit the data securely.

The CDRAM also has a G buffer 162 which receives the output enable signal G # to generate an internal output enable signal G and an output control circuit 168 by the internal output enable signal G and a control signal from the control signal generating circuit 166 is dependent on controlling the main amplifier 138 on. At the in 1 The structure shown is the output control circuit 168 formed in the SRAM control circuit. The output control circuit 168 has a gate circuit 176 which the internal output enable signal G from the G buffer 162 and receives the activation signal E1 from the control signal generating circuit, and a gate circuit 178 which the output signal from the gate circuit 176 and the clock mask signal CMsR from the shift register 152 receives on. The gate circuit 176 generates a signal with level "H" when the signals applied to its two inputs are at "L". The gate circuit 178 generates a signal with level "H" when at least one of the input signals reaches level "H".

The main amplifier 138 has an inverter circuit 172 for inverting the signal on an internal data bus 123a (1-bit data line of the internal data bus 123 of 1 ), a 3-state inverter circuit 170 which are dependent on an output signal of the output control circuit 168 is activated, an inverter circuit 174 and a connection gate 173 to connect the Output of the inverter circuit 170 with the input of the inverter circuit 174 corresponding to the internal clock mask signal CMsR. The output signal from the inverter circuit 174 is connected to an input of the 3-state inverter circuit 170 created. When the clock mask signal CMsR is "H", it forms the inverter circuit 170 and the inverter circuit 174 a latch circuit.

The operation will now be briefly described. The shift register 152 outputs a clock mask signal CMsR with a delay of one clock cycle. Depending on this clock mask signal CMsR delayed by one clock cycle, the gate circuit leaves 164 the internal clock signal Ki. If the SRAM clock mask signal CMs is generated externally, the transmission of the SRAM master clock signal SK to the SRAM control circuit is correspondingly carried out in the next clock cycle 132 blocked. The operation timing of the control signal generation circuit 166 is defined by the SRAM master clock signal SK and generates the necessary internal control signals. The buffer circuits 154 . 156 . 158 and 160 lock out the applied data in accordance with the internal chip activation signal E and the SRAM master clock signal SK. If no SRAM master clock signal SK is supplied, none of the buffers performs a new locking.

Similarly, if the chip activation signal E is not generated, the buffers will not work. If the chip activation signal E is at "H", which indicates the unselected state, the buffers operate 156 . 158 and 160 Not. The control signal generating circuit also operates at this time 166 Not.

The SRAM master clock signal SK is masked by this SRAM clock masking signal CMs from the next cycle after the generation of the SRAM clock masking signal CMs. Therefore, when the SRAM clock mask signal CMs is externally applied, the internal chip activation signal E and the SRAM master clock signal SK are generated in this cycle, and therefore an operation is carried out in accordance with the applied control signals. In the next cycle, no internal control signal is generated and the control signal generating circuit 166 maintains the state of the previous cycle. The control signal generating circuit 166 delays the chip activation signal E by a predetermined period of time and generates an internal chip activation signal E1. The output clock can thus be set precisely (because the generation clock position is defined by the SRAM master clock signal SK).

If the clock mask signal CMsR is "H", the 3-state inverter circuit is located 170 in the operating state and also the connection gate 173 becomes a leader. As a result, the inverter circuits form 170 and 174 a latch circuit. Although the output signal from the G buffer 162 is in the active state, the output value DQ remains through the inverter circuits 170 and 174 same value at. When the chip activation signal E # falls to "L", the internal chip activation signal E falls to "L", the control signal generating circuit 166 initializes the chip activation signal E1 to "H" and lowers it again to "L" after a predetermined period of time. If the clock mask signal CMsR is at "L", the inverter circuit 170 is put into a high impedance output state, and if the internal output enable signal G is at "L", the inverter circuit becomes 170 set to the operational state in accordance with the internal chip activation signal E1 after a predetermined period of time has passed. As a result, new output data appear.

As described above can the output impedance state by the clock mask signal CMsR and the chip activation signal E # can be set.

6 shows an example of the structure of the buffer circuit of FIG 5 , 6 shows a structure of the SRAM address buffer shown in 5 is not shown. The buffers 156 . 158 and 160 have the same structure as that in 6 shown buffers. As in 6 is shown, the buffer 116 a 3-state inverter circuit 7011 , the output state of which is determined by the master clock signal K, an inverter circuit 7013 which have an output signal from the inverter circuit 7011 receives, and a 3-state inverter circuit 7014, which is put into an output activation state in response to the internal chip activation signal E. The output of the inverter circuit 7013 is with one input of the inverter circuit 7014 connected. The output of the inverter circuit 7014 is with one input of the inverter circuit 7013 connected. The inverter circuit 7013 generates an internal address signal intAs. The operation will now be briefly described.

The 3-state inverter circuit 7011 is brought into the active state when the internal SRAM master clock signal SK is at "L" and inverts an externally applied address As and passes it through. If the SRAM master clock signal SK is at "H", the inverter circuit 7011 placed in a high impedance output state. Therefore, the inverter circuit takes over 7011 with the rising edge of the SRAM master clock signal SK, the address As that was created at this time.

The inverter circuit 7014 is put in the active state when the internal chip activation signal E is at "L" and thus indicates the chip selection state, while it is put in a state of high output impedance when the chip activation signal E is at "H" and indicates the unselected chip state. If the chip activation signal E is on the rising edge of the internal clock signal SK at "L", the address As is sent to the inverter at this time circuit 7011 is created by the inverter circuits 7013 and 7014 locked and an internal SRAM address is generated.

7 shows a structure for the E-buffer of 5 , As in 7 is shown, the E-buffer 154 a p-channel MOS transistor Tr700 whose source is connected to the supply potential Vcc and which receives the SRAM master clock signal SK at its gate, a p-channel MOS transistor Tr701 whose source is connected to the drain of the p-channel MOS Transistor Tr700 is connected and the gate receives the chip activation signal E #, an n-channel MOS transistor Tr702, the gate receives the chip activation signal E # and the drain is connected to the drain of the MOS transistor Tr701, and an n-channel MOS transistor Tr703, the drain of which is connected to the source of the MOS transistor Tr702, the source of which is connected to the ground potential Vss and the gate of which receives an inverted signal / SK of the SRAM master clock signal. The e-buffer 154 is placed in a high impedance state when the SRAM master clock signal SK is at "H" (transistors Tr700 and Tr703 are both blocked) and it inverts the chip activation signal E # and generates an inverted signal / E of the internal chip activation signal E # when the SRAM master clock signal SK is at "L". Therefore, the chip activation signal E # can be adopted in accordance with the SRAM master clock signal SK.

By using the structures of the SRAM control circuit and the main amplifier circuit 138 As described above, the SRAM power save mode and the SRAM set mode can quickly become simple.

[SRAM reading mode]

The SRAM read mode is a mode for reading data from the SRAM array. As in 8th is shown, the chip activation signal E # is set to "L" in this operating mode with the rising edge of the master clock signal K and the write activation signal WE # and the control clock signals CC1 # and CC2 # are set to "H". In the following description, it is assumed that the SRAM clock mask signal CMs is "L". At this time it is under the control of the SRAM control circuit 132 (please refer 1 ) in accordance with the simultaneously adopted SRAM address bits As0 to As1, a memory cell selection process is carried out, and the data of the selected memory cell of the SRAM field are transferred to the internal data bus 123 (please refer 1 ) transfer. If the output activation signal G # is at "L" at this point in time, a stable value is output with the rising edge of the next clock signal. The SRAM works at high speed. Therefore, by setting the SRAM read mode with each rising edge of the master clock signal K, the stable data can be output with the rising edge of the next clock cycle (provided the output enable signal G # is "L").

When the output enable signal G # is set to "H", the main amplifier circuit becomes 138 placed in a state of high output impedance.

9 shows the data flow in SRAM read mode. At this point a driver is decoding 118a that the in 1 SRAM line decoder shown 118 corresponds to the SRAM address bits As4 to As11 and selects a line in the SRAM field 104 out. In the SRAM field 104 are with one line 16 Bits connected to memory cells. One of these 16 bits of memory cells is used by the column decoder 120 selected. The column decoder 120 decodes the SRAM address bits As0 to As3 and selects one of the 16 bits of memory cells. An SA / IO control circuit 122 reads the data of the selected memory cell of the SRAM array 104 ,

[SRAM write mode]

The SRAM write mode is a mode for writing data into the memory cells of the SRAM array. For the SRAM write mode, with the rising edge of the master clock signal K, the chip activation signal E # and the write activation signal WE # are both set to "L" and the control clock signals CC1 # and CC2 # are both set to "H", as in 10 is shown. In this case, the SRAM clock mask signal CMs is also set to "L" in the previous cycle. This condition applies to the following descriptions and it is assumed that the SRAM clock mask signal CMs is "L" unless otherwise stated. As in 10 is shown, masking data M0 to M3 are used, and the operating signal diagrams in the SRAM read mode and SRAM write mode are shown with a common DQ connection arrangement.

As in 10 is shown, the SRAM read mode is set when, with the rising edge of the first cycle of the master clock signal K, the chip activation signal E # is set to "L" and the write activation signal WE # and the control clock signals CC1 # and CC2 # are set to "H". If the output enable signal G # is at "L", data is read with the rise of the next clock signal K.

In order to switch from the SRAM read mode to the SRAM write mode, the chip activation signal E # is raised to "H" with the rising edge of the third cycle of the master clock signal K. As a result, the SRAM decommissioning mode is set, and the SRAM memory cell data set in the second cycle of the clock signal K is updated with the rising edge of the third cycle klus of the master clock signal K stabilized and then placed in a state corresponding to a high output impedance.

In the fourth cycle of the master clock signal K, when the chip activation signal E # and the write activation signal WE # are both set to "L" and the control clock signals CC1 # and CC2 # are set to "H", the SRAM write mode is set. The SRAM address bits As0 to As11 created at this time are adopted, and also the masking data M0 to M3 (in 10 referred to as M3) and the internal write data are accepted at this time. A specific bit D3 of the write data is masked with respect to the write process in accordance with the masking data M3. As long as the chip activation signal E # and the write activation signal WE # are at "L" and the control clock signals CC1 # and CC2 # are at "H" with the rising edge of the master clock signal K, the SRAM write mode is then repeated, write data D and masking data M become with the rising edge of the clock signal K, and the data is written.

By setting the chip activation signal E # to "L" and the write activation signal WE # and the control clock signals CC1 # and CC2 # to "H" in the ninth cycle of the master clock signal K, the SRAM read mode is set. If the output activation signal G # is at "L", the values Q8 and Q9 read in the SRAM read mode are put into a stable state with the rising edges of the tenth and eleventh cycle of the master clock signal K. The output enable signal G # becomes earlier than the rising edge of the master clock signal 12 is set to "H", the input / output terminal DQ is put in a high impedance state, provided the write enable signal WE # is at "H".

Because access to the SRAM field as mentioned above executed at high speed data writing in one cycle of the clock signal K completed.

How out 10 it can be seen that the writing of data can be carried out safely using the SRAM decommissioning mode when switching from reading operation to writing operation; while the read data (Q2) does not affect the write data (D3) of the next cycle.

11 shows the data flow in SRAM write mode. As in 11 is shown a word line driver circuit 118a driven to perform the row selection operation in the SRAM, and the column decoder 120 works to a memory cell of the SRAM array 104 select. Data is over a block 122 into the selected memory cell of the SRAM field 104 enrolled.

As in the 9 and 11 is shown, in the SRAM read mode and the SRAM write mode, the writing of data into the SRAM field and the reading of data from the SRAM field are carried out independently of the operation of the data transmission circuit and the DRAM field. When accessing the SRAM field, data transfer between the data transmission circuit and the DRAM field can therefore be carried out in parallel. Such an operation is possible because of the DRAM control circuit 128 and the SRAM control circuit 132 are formed separately, as in 1 is shown.

[Buffer read transfer mode]

The buffer read transfer mode is an operating mode for transferring data from the read transfer buffer to the SRAM. In this mode, 16 bits of data are transferred simultaneously from the data transfer circuit to the SRAM array. As in 12 is shown, the buffer read transfer mode is realized by setting the chip activation signal E # and the control clock signal CC2 # to "L" and the write activation signal WE # and the control clock signal CC1 # to "H" with the rising edge of the master clock signal K. In 12 the other operating modes are also shown.

In the buffer read transfer mode, the data transfer is ensured by setting the SRAM address bits As0 to As3, which are being supplied at this time, to "L". By setting the SRAM column address bits As0 to As3 to "L", simultaneous data transfer of 16 bits is carried out. With reference to 12 The buffer read transfer mode and other operating modes will now be described.

As in 12 is shown, the SRAM read mode is set with the rising edge of the first cycle of the master clock signal K. The SRAM read operation is carried out in accordance with the SRAM address C1 which is applied at this time, and the output data Q1 is stabilized with the rising edge of the second cycle of the master clock signal K. Because the chip activation signal E # is at "H" on the rising edge of the second cycle of the master clock signal K, the second cycle of the master clock signal K is in SRAM decommissioning mode and is on the rise of the third clock of the master clock signal K. the output is in a high impedance state. At this time, with the rising edge of the third cycle of the master clock signal K, the chip activation signal E # and the control clock signal CC2 # are also set to "L" and the write activation signal WE # and the control clock signal CC1 # to "H". As a result, the buffer read transfer mode is set. At this time, the SRAM address bits As0 to As3 are at "L". A row selection operation is carried out in the SRAM field in accordance with the SRAM address bits As4 to As11. 16 bits of SRAM memory cells are connected in one row. The data is transferred from the read transfer buffer at the same time 140 to these 16 Transfer bits of the connected SRAM memory cells.

The SRAM field does not require any operations, such as precharging the bit lines. The SRAM field can be addressed by the read transfer buffer immediately after the data has been transferred. As in 12 is shown, with the rising edge of the fourth cycle of the master clock signal K, the chip activation signal E # is set to "L" and the write activation signal WE # and the control clock signals CC1 # and CC2 # are set to "H". This sets the SRAM read mode. Accordingly, data is read from the RAM memory cell on the rising edge of the fifth cycle of the master clock signal K.

Then by setting the Chip activation signal E # at "H" with the rising edge of the fifth Cycle of the master clock signal K set the SRAM shutdown mode, the SRAM is in the fifth Cycle in an unselected State and after a predetermined period of time has elapsed the output is placed in a high impedance state.

With the rising edge of the master clock signal K in the sixth cycle, the chip activation signal E # and the control clock signal CC2 # are both set to "L" and the write activation signal WE # and the control clock signal CC1 # are set to "H", as a result of which the buffer reading mode is set. As a result, 16 bits of memory cells in the SRAM array are selected and data is transferred from the read transfer buffer 140 to the selected 16 bits of SRAM memory cells. Then, in the seventh cycle of the master clock signal K, the chip activation signal E # and the write activation signal WE # are set to "L" and the two control clock signals CC1 # and CC2 # are set to "H", whereby the SRAM write mode is set. The data D5 applied at this time are written into the selected memory cell of the SRAM in accordance with the masking data M5.

In the eighth cycle of the master clock signal K, the chip activation signal E # is set to "L" and the write activation signal WE # and the two control clock signals CC1 # and CC2 # all become set to "H". This sets the SRAM read mode. Because of this When the output enable signal G # is at "H" a state of high output impedance to the outside.

In the ninth cycle of the master clock signal K, a buffer read transfer is performed again, and data is transferred from the read transfer buffer transferred to the SRAM field.

In the tenth cycle of the master clock signal K becomes the SRAM write mode is set, and data is put into the selected memory cells in this tenth cycle of the SRAM field.

By setting the buffer read transfer mode as described above it becomes possible in the event of a cache miss hit the cache block collectively with high Transfer speed to the SRAM field. Therefore, the access time in the case of a cache miss can be significantly reduced. The reason for this is that the SRAM field after the data transfer to the SRAM field corresponding to the buffer read transfer mode with high Speed can be addressed.

13 shows the data flow in the buffer read transfer mode. In the buffer read transfer mode, a word line driver circuit selects 188a a line of the SRAM field 104 off, and 16 bits of data are transferred from the read transfer buffer 140 simultaneously with the one selected line ( 16 Bits). The read transfer buffer described later 140 has 16 buffers so that 16 data bits can be transferred simultaneously.

[Buffer write transfer mode]

The buffer write transfer mode is an operating mode for transferring data from the SRAM array to a write data transfer buffer (with an intermediate buffer) formed in the data transfer circuit. The states of the control signals in the buffer write transfer mode are in 14 shown.

The buffer write transfer mode is set by setting the chip activation signal E #, the write activation signal WE # and the control clock signal CC2 # to "L" and the control clock signal CC1 # to "H" with the rising edge of the master clock signal K. In the buffer write transfer mode, the SRAM address bits As0 to As3 must all be set to "L" to complete the data transfer process. In the buffer write transfer mode, all of the masking bits (masking data) are in the masking register 146 are formed, put in the reset state ("0" state). The reason for this is that it is necessary to transfer all data to the DRAM field from the SRAM field to the write transfer buffer 144 have been transferred.

With reference to 14 the operation including the buffer write transfer mode will now be described. As in 14 is shown, the SRAM read mode is determined with the rising edge of the first cycle of the master clock signal K. The selection of a memory cell of the SRAM is carried out, and the data of the selected memory cell are stabilized with the rising edge of the second cycle of the master clock signal K.

With the rising edge of the second cycle of the master clock signal K, the chip activation signal E # is raised to "H", the SRAM set mode is set, the SRAM is set to the non-selected state and the output is set to a high impedance state. In the third cycle of the master clock signal K, the chip activation signal E #, the write activation signal WE # and the control clock signal CC2 # are on "L" and the control clock signal CC1 # are set to "H", so that the buffer write transfer mode is set. In the buffer write transfer mode, the SRAM address bits As0 to As3 are all set to "L". By using the remaining SRAM address bits As4 to As11, a line in the SRAM field ( 16 Bits) is selected, and the data of the selected 16 bits of SRAM memory cells are simultaneously transferred to the write transfer buffer (locked in the intermediate buffer).

In the fourth cycle of the master clock signal K becomes the SRAM read mode determined, a memory cell selection process corresponding to the SRAM address bits As0 until As11 is executed and the dates of the selected ones Memory cells are read. In the fifth cycle of the master clock signal K sets the decommissioning mode again, the SRAM is switched off during the fifth Cycle of the master clock signal K held in the unselected state and the output is placed in a high impedance state.

In the seventh cycle of the master clock signal K becomes the SRAM write mode established. At the same time, the output activation signal G # to "H", and writing data corresponding to the masking data M5 (mask bits M0 to M3) is carried out with respect to the SRAM field.

In the ninth cycle of the master clock signal K sets the buffer write transfer mode, one line of the SRAM field will selected and the data of the memory cells associated with the one selected row connected are transferred to the write data transfer buffer. In the tenth cycle of the master clock signal K, the SRAM write mode is determined, and data is written into the SRAM field.

15 shows the data flow in the buffer write transfer mode. As in 15 is shown, the word line driver circuit 118a driven one line of the SRAM field 104 is selected and the data of the memory cells connected to the selected row are transferred to the write data transfer buffer. Here, the write data transfer buffer has an intermediate buffer for temporarily storing the supplied data, and the data is stored in the intermediate buffer 142 locked. Through this structure, in which the SRAM field 104 transferred data from the buffer 142 Once locked, data can be extracted from the SRAM field 104 (in the case of a cache miss) and in parallel the cache data can be transferred from the DRAM field via the read data transfer buffer 140 be transmitted. Therefore, the data transfer can be carried out at high speed in the case of a cache miss. This reduces the access time. In the following description, the data transfer from the SRAM field to the write data transfer buffer corresponds to the state in which data is stored in the intermediate buffer.

[Transfer buffer read / SRAM reading mode]

In buffer read transfer and SRAM read mode (hereinafter referred to as buffer read transfer / SRAM read mode) Data is transferred from the read data transfer buffer to the SRAM field and further becomes one Bits (a total of four bits if the device has a * 4-bit structure) the transferred Data corresponding to the SRAM address output from the SRAM field.

The buffer read transfer / SRAM read mode is set by setting the chip activation signal E # and the control clock signal CC1 # to "L" and setting the write activation signal WE # and the control clock signal CC2 # to "H" with the rising edge of the master clock signal K. The state of the control signals in an operating sequence with the buffer read transfer / SRAM read mode is in 16 shown.

As in 16 is shown, the SRAM read mode is set with the rising edge of the first cycle of the master clock signal K, a memory cell selection process in the SRAM field is carried out and the data of the selected SRAM memory cell are read.

With the rising edge of the second Cycle of the master clock signal K become the chip activation signal E # and the control clock signal CC1 # set to "L" while the write activation signal WE # and the control clock signal CC2 # can be set to "H". Through this combination of the states of the Control signals determine the buffer read transfer / SRAM read mode. In this operating mode, a line is selected in the SRAM field, and Data at the same time are read from the read data transfer buffer (DTBR) the one selected line transferred from memory cells. After or parallel to data transfer becomes a memory cell (column) selection process accordingly the SRAM block address bits As0 to As3 executed, and the data related to the selected Memory cell transferred have been read.

In the third cycle of the master clock signal K the buffer read transfer / SRAM read mode is set again, Data is transferred from the read data transfer buffer (DTBR) to the SRAM field, and it gets a bit from the transmitted Data (16 bits) selected. The buffer read transfer / SRAM read mode is described in the following reasons continuous cycles of the master clock signal K executed. It is namely possible, data transmission with each clock cycle from the DRAM field to the read data transfer buffer by using the one described later Page mode of the DRAM used. The page mode of the DRAM is activated because the control circuit section for driving the DRAM array and the control section for setting the operations related to the SRAM field, independently are formed from each other.

In the fifth cycle of the master clock signal K the SRAM shutdown mode is set, the SRAM is set to the non-selected state for the fifth cycle, and a high impedance output state is set.

In the sixth cycle of the master clock signal K becomes the SRAM read mode set, the buffer read transfer / SRAM read mode is during the seventh and eighth cycle of the master clock signal K run continuously, and in the ninth cycle of the master clock signal K the SRAM read mode is determined.

The SRAM read mode and the buffer read transfer / SRAM read mode are run continuously because when a cache hit, the SRAM read mode is executed, and a cache miss the latch function of the sense amplifier is used in the DRAM field and data of a row of memory cells has been locked in the DRAM field are like later is described. If this is from an external device, e.g. a CPU Data is not in the SRAM field, but from the sense amplifier in the DRAM field are locked, can that of the DRAM sense amplifier locked data are transferred from the read data transfer buffer. Then be transfer the data from the read data transfer buffer to the SRAM field, and with it can the data is read. The structure for executing such an operating mode will later described in detail.

17 shows the data flow in the buffer read transfer / SRAM read mode. As in 17 is shown, a row of the SRAM field 104 from the word line driver circuit 118a selected. Data is transferred from the read data transfer buffer (DTBR) to the selected line at the same time. Then, according to a column selection signal from the column decoder 120 a memory cell in the SRAM field 104 selected, and the data of the selected memory cell are sent via a sense amplifier / IO control block 122 output.

[Buffer write transfer / SRAM write mode]

In buffer write transfer and SRAM write mode (hereinafter referred to as buffer write transfer / SRAM write mode) data is written to the SRAM field while data of the row with the Memory cell in which the data is written to the write data transfer buffer (Intermediate buffer) (DTBW) transferred become. The transfer process is completed in one clock cycle of the master clock signal K. The masking bits are in the buffer write transfer / SRAM write mode reset all in the masking register, and all data is transferred from the write data transfer buffer (DTBW) to the Transfer DRAM field.

In the buffer write transfer / SRAM write mode, the rising edge of the master clock signal K sets the chip activation signal E #, the write activation signal WE # and the control clock signal CC1 # to "L" and the control clock signal CC2 # to "H". As a result, data is written into the SRAM array and data is transferred from the SRAM array to the write data transfer buffer. The states of the external signals in operations involving the buffer write transfer / SRAM write mode are shown in 18 shown.

As in 18 is shown, in the first cycle of the master clock signal K, the chip activation signal E # is at "H" and the SRAM is in a non-selected state (SRAM shutdown mode). In the second cycle of the master clock signal K, the chip activation signal E #, the write activation signal WE # and the control clock signal CC1 # are set to "L" and the control clock signal CC2 # to "H". The buffer write transfer / SRAM write mode is determined by these signal states. In this mode, the SRAM address bits As0 to As11 supplied at this time are all adopted, a column selection is carried out in the SRAM field and data is written externally into the selected SRAM memory cell. After the completion of the write operation or in parallel with the write, the data of the memory cells which are connected to the one selected row of the SRAM field are transferred to the write data transfer buffer (DTBW) (more precisely to the intermediate buffer). In the third cycle of the master clock signal K, the buffer write transfer / SRAM write mode is carried out in a similar manner.

In the fourth cycle of the master clock signal K the SRAM read mode is set. Because the output enable signal G # but being "H", the output goes into a high impedance state added.

In the fifth cycle of the master clock signal K becomes the SRAM read mode is set, and data is read from the SRAM field. The output enable signal G # is at "L" and the data read in this cycle becomes Q3 output.

In the seventh cycle of the master clock signal K, the output enable signal G # is set to "H" to to put the output in a high impedance state. Thereby prevents the data read in the sixth cycle of the master clock signal K influence the subsequent data writing process.

In the eighth to tenth cycle of the master clock signal K, the chip activation signal E #, the write activation signal WE # and the control clock signal CC1 # are set to "L" and the control clock signal CC2 # to "H". In these cycles, an operation corresponding to the buffer write transfer / SRAM write mode is carried out. By executing the buffer write transfer / SRAM write mode, a write-through process is implemented in the event of a cache hit (in which the data written into the SRAM field is transferred directly to the DRAM field be).

19 shows the data flow in the buffer write transfer / SRAM write mode. With reference to 19 is driven by the word line driver circuit 118a a line of the SRAM field 104 selected. From the column decoder 120 becomes a column of the SRAM field 104 selected. With this selected column, write data is sent via the SA / IO block 122 transfer. After the transfer of the write data, the data is one row of memory cells by the word line driver circuit 118a in the SRAM field 104 has been selected to the write data transfer buffer (DTBW) 144 or more precisely to the buffer 142 transfer.

[Buffer read mode]

In the buffer read mode, data is transferred directly from the Read data transfer buffer output. It will not overwrite the Content through data transfer to the SRAM field. By running buffer read mode Data is read without the cache data stored in the SRAM field to influence.

For the buffer read mode, the chip activation signal E # and the control clock signals CC1 # and CC2 # are set to "L" and the write activation signal WE # to "H" with the rising edge of the master clock signal K. In the buffer read mode, data is transferred from the read data transfer buffer (DTBR) to the input / output terminal DQ. In the buffer read mode, all address bits As4 to As11 for selecting a row of the SRAM are all set to "L" in order to ensure operation in the buffer read mode and to reliably prevent data change in the SRAM field. The SRAM address bits As0 to As3 are used to select a buffer of the read data transfer buffer (DTBR). In 20 an example of an operating sequence with the buffer read mode is shown.

As in 20 is shown, the SRAM read mode is determined in the first cycle of the master clock signal K, and data is read from the SRAM field. In the second cycle of the master clock signal K, the chip activation signal E # and the control clock signals CC1 # and CC2 # are set to "L" and the write activation signal WE # to "H". This sets the buffer read mode. In the buffer read mode, the data of the read data transfer buffer (DTBR) is transferred to the input / output terminals DQ0 to DQ3 via the SRAM field (which is in a non-selected state). The SRAM block address bits As0 to As3 are used to select a buffer in the read data transfer buffer (DTBR).

The buffer read cycle is in one Cycle of the master clock signal K completed.

In the third and fourth cycle of the Master clock signal K, the SRAM read mode is set, and it data is read from the SRAM field. Although in the tenth cycle of the master clock signal K the SRAM read mode is set the output enable signal G # becomes "H" and the output in a state of high impedance. In the eleventh to thirteenth cycle of the Master clock signal K becomes an operation in the buffer write transfer / SRAM write mode executed. Through the buffer read mode Image data on a CRT display unit at high speed being represented. In SRAM read mode, the CPU reads the necessary ones Data from the SRAM field and processes it. Then the processed ones Data using buffer write mode and DRAM write transfer mode operation inscribed in the DRAM field. This operation enables the CDRAM can be used effectively as video memory in the graphics area.

21 shows the data flow in the buffer read mode. As in 21 the word line driver circuit operates 118a Not. The SRAM field 104 is kept in a non-selected precharge state. Data from the read data transfer buffer 140 traverse the SRAM field 104 , A column of the SRAM field 104 is from the column decoder 120 and the SA / IO control block 122, and the data is transferred to the data input / output terminal DQ. The SRAM field is also located in this structure 104 in the precharge state or the non-selected state (although the bit line potential changes due to the transfer data). The from the data transfer buffer 140 Read data transmitted influence that in the SRAM field 104 stored data at all.

[Buffer write mode]

The buffer write mode is an operating mode in which externally supplied write data are not written into the SRAM memory cells, but into the write data transfer buffer (DTBW). For the buffer write mode, the chip activation signal E #, the write activation signal WE # and the control clock signals CC1 # and CC2 # are all set to "L". When the control signals are in these states, no row selection operation is performed in the SRAM field. It is necessary that the SRAM address bits As4 to As11 are all set to "L" in order to ensure the buffer write mode. The states of the control signals of operating sequences with the buffer write mode are in 22 shown.

As in 22 is shown, with the rising edge of the master clock signal K, the chip activation signal E # is at "H" and the SRAM is in a non-selected state (SRAM shutdown mode). With the rising edge of the second cycle of the master clock signal K, the chip activation signal E #, the write activation signal WE # and the control clock signals CC1 # and CC2 # are set to "L". So that will the buffer write mode is set.

In this state the SRAM field not driven and externally supplied Data (D1) are written into the write data transfer buffer (DTBW). The address bits As4 to As11 are set to "L". The write data transfer buffer (DTBW) is selected in accordance with the SRAM block address bits As0 to As3 and Data are selected in the Write data transfer buffer (DTBW) written. When the buffer write mode is set, the masking data of the masking register according to the external masking data valid at that time modified. If one of the masking values M0 to M3 is "0" what indicates a write becomes the corresponding bit of the mask register reset and indicates that the Masking is removed. Only the masking bit of the masking register corresponding to the transfer buffer into which data writing is carried out, is reset.

In the third and fourth cycle of the Master clock signal K, the SRAM read mode is set, and data are read from the SRAM field. In the fifth cycle of the master clock signal K, the chip activation signal E # is set to "H" and the SRAM decommissioning mode established.

In the sixth to eleventh cycle of the Master clock signal K becomes the chip activation signal E #, the write activation signal WE # and the control clock signals CC1 # and CC2 # are all set to "L" and set the buffer write mode. So that in every cycle Data written to the write data transfer buffer (DTBW).

By executing the operation in the buffer write mode can Data is written into the write data transfer buffer (DTBW), without the Data stored in the SRAM field are affected because in the SRAM field no memory cell selected is. Subsequently can by transferring of data from the write data transfer buffer (DTBW) to the DRAM field data be written into the DRAM field without the ones stored in the SRAM field To influence data (cache data). So that a letter of Graphics data is executed at high speed.

23 shows the data flow in the buffer write mode. In the buffer write mode, the word line driver circuit 118a not driven. Through the column decoder 120 a corresponding buffer in the intermediate buffer 142 selected, and data is written to the selected buffer. The operation of the section that drives the DRAM array will now be described.

[DRAM system]

24 shows in table form the operating modes that relate to the DRAM field and the states of the control signals for realizing the respective operating modes. As in 24 the operations relating to the DRAM array include a DRAM power save mode in which transmission of the clock signals to the DRAM portion is inhibited to effectively extend the DRAM array's operating cycles, a DRAM-NOP mode to disable the DRAM Mode, a DRAM active mode for driving the DRAM field, a DRAM read transfer mode for transferring data from the DRAM field to the read data transfer buffer, a DRAM write transfer mode for transferring data from the write data transfer buffer to the DRAM field, a DRAM precharge mode for offset of the DRAM into a precharge state and a DRAM self-refresh mode for performing self-refresh of the DRAM array. The section for driving the DRAM array further includes a special mode for the CDRAM and a command register setting mode for setting command data for specifying the arrangement of the data input / output ports and the like in one (in 1 not shown) command register. The operating mode will now be described.

[DRAM power saving mode]

In the DRAM power saving mode, the master clock signal is not supplied to the DRAM area. The operating speed of the DRAM is lower than that of the SRAM. It takes several clock cycles to select a line and to address the DRAM field. The same applies to the data transfer mode. Therefore, the duration and clock position for generating the control signals are determined in accordance with the master clock signal for each process. When the master clock signal is not sent to the DRAM control circuit ( 128 in 1 ) is created, the state of the previous clock cycle is retained.

As in 25 is shown, the DRAM clock masking signal CMd for the DRAM power saving mode is set to "H" with the rising edge of the master clock signal K, and the DRAM enters the power saving mode from the next cycle. As in 25 is shown, the DRAM clock mask signal CMd is set to "H" with the rising edge of the second cycle of the master clock signal K and the DRAM power saving mode begins after the third clock cycle of the master clock signal K. By stopping the DRAM operation, the Power consumption reduced.

[DRAM-NOP Mode]

The DRAM-NOP mode is an operating mode in which a new process is blocked in the DRAM. The DRAM section reserves the precharge status or the active status of the previous cycle.

As in 26 is shown for the DRAM-NOP mode, the DRAM clock mask signal CMd with the rising edge of the master clock signal K is set to "L", and the row address scan signal RAS # and the column address scan signal CAS # both go up with the rising edge of the master clock signal K. "H" raised. Because both the row address strobe signal RAS # and the column address strobe signal CAS # are at "H", the DRAM section maintains the unselected state, that is, the precharge state of the standby mode (if the precharge state was set in the previous cycle).

In the operations related to the DRAM, the states of the control signals relating to the operation of the SRAM array are arbitrary, as the table of 24 shows. Therefore, the SRAM operation can be carried out independently of the DRAM operation. This also applies to the other processes that affect the DRAM field and are described below. The DRAM clock mask signal CMd allows the transmission of the master clock signal K in the next cycle if it is at "L". If the DRAM clock mask signal CMd is at "H", the transmission of the master clock signal K to the DRAM control circuit is blocked in the next cycle. When the DRAM-NOP mode is set, the DRAM maintains the precharge state when the precharge state has been set in the previous cycle and maintains the active state when the active state has been set in the previous cycle. The DRAM-NOP mode ensures that the DRAM area does not adopt a new operating mode.

[DRAM-active mode]

The DRAM field is activated in DRAM active mode. To set the DRAM active mode with the rising edge of the master clock signal K of the next Clock cycle the row address strobe signal RAS # to "L" and the column address strobe CAS # as well as the data transmission determination signal DTD # set to "H" when the DRAM clock mask signal CMd is at "L" in the previous clock cycle. In this condition the DRAM address Ad is used as the row address for defining a row of the DRAM field, and it becomes a line selection operation as well as detection, amplification and Locking the memory cell data is performed by the sense amplifier.

[DRAM precharge]

In the DRAM precharge mode, the DRAM put into a standby or precharge state. By executing the Precharge mode, the DRAM active mode can be ended. For the DRAM preload mode becomes the DRAM clock mask signal CMd with the rising edge of the master clock signal K is set to "L", and the row address strobe signal RAS # and the column address strobe signal CAS # are set to "K" with the rising edge of the master clock signal K of the next cycle. When the DRAM precharge mode is set, the DRAM returns to Precharge status back. More specifically, a line (selected line) that is in the DRAM field was in the active state to the unselected state for the next Activation cycle to be ready. If another in the DRAM field Row selected it is necessary to switch the DRAM active mode once through a DRAM precharge cycle exit and run DRAM active mode again.

[DRAM read transfer mode]

The DRAM read transfer mode is on Operating mode in which data from the DRAM field to the read data transfer buffer (DTBR) broadcast become. The data transfer from the DRAM field to the read data transfer buffer (DTBR) and data transfer from the read data transfer buffer to the SRAM field and the data input / output circuit are carried out by separate control systems.

For the DRAM read transfer mode, with the rising edge of the master clock signal K, the row address strobe signal RAS # is set to "L", the data transfer designation signal DTD # is set to "H" and the column address strobe signal CAS # is set to "L" while the DRAM active mode is set. At this point the in 1 Column block decoder shown 112 with the DRAM input addresses Ad4 to Ad11 as column addresses. A corresponding column block (data block) of the memory cells connected to the selected row of the DRAM array is selected, and the memory cell data contained in the selected data block are transferred to the read data transfer buffer (DTBR).

To ensure this process, it is necessary to set the address bits Ad0 to Ad3 to "L". When the DRAM read transfer mode is set, all other operations are inhibited for a predetermined period of time. After a predetermined clock signal time has elapsed after the DRAM read transfer mode has been set, the data in the read data transfer buffer (DTBR) is stabilized. The necessary time period between the determination of the DRAM read transfer mode and the stabilization of the new data in the read data transfer buffer (DTBR) is referred to as latency, which is determined by a command value set in the command register, which will be described later. The read data transfer buffer (DTBR) has a latch function and holds the data of the previous cycle. By setting the latency and setting the data transfer timing by the master clock signal K the content of the read data transfer buffer (DTBR) can be safely overwritten with the new data and data can be transferred / read safely. Because access is blocked when the data in the read data transfer buffer (DTBR) is changed, the storing or reading of incorrect data in or from the read data transfer buffer (DTBR) can be prevented.

27 shows the states of the external control signals and the states of the data stored in the read data transfer buffer when the DRAM precharge mode, the DRAM active mode and the DRAM read transfer mode are set. With reference to 27 an operating sequence of the DRAM is described.

As in 27 is shown, the DRAM clock masking signal CMd reaches the level "L" with the rising edge of the master clock signal K and the transmission of the master clock signal K to the DRAM control circuit ( 128 in 1 ) is allowed.

With the rising edge of the third Cycle of the master clock signal K become the row address strobe signal RAS # and the data transfer designation signal DTD # both at "L" and the column address strobe signal CAS # at "H" set. The DRAM preload mode is set.

After the RAS precharge time elapsed (the minimum time required to precharge each signal line in the DRAM section) in the seventh cycle of the master clock signal K, the row address scanning signal RAS # at "L" and the column address strobe signal CAS # and DTD # both at "H" set. This sets the DRAM active mode. Here is the DRAM clock mask signal CMd dropped to "L" in the previous cycle (sixth cycle). In In the following description lies the DRAM clock mask signal CMd always set to "L" in the previous cycle of setting the operating mode, and therefore it becomes out of order for cases that require a special description, not described.

When the DRAM active mode is set , the DRAM addresses Ad0 up to Ad11 adopted as the row address for defining a row in the DRAM field, and the dates of the selected ones Memory cells are detected, amplified and locked by a sense amplifier.

After the RAS / CAS delay time tRCD has passed, in the tenth cycle of the master clock signal K, the row address strobe signal RAS # and data transfer determination signal DTD # are both set to "H" and the column address strobe signal CAS # to "L". This determines the DRAM read transfer mode. The DRAM active mode selects a memory cell block corresponding to the DRAM address Ad4 to Ad11 supplied at that time, and after a predetermined period of time has elapsed (in 27 a latency of two clock cycles), the data of the read data transfer buffer (DTBR) are replaced by new data.

When setting the latency of the DRAM read transfer mode comprises n clock cycles, the determination of a new operating mode in the (n - 1) th Clock cycle from the cycle in which the DRAM read transfer begins blocked. at the data transmission from the DRAM field to the read data transfer buffer (DTBR) the read data transfer buffer in a locked state. During this Time period is the buffer read mode (i.e. reading data from Read data transfer buffer (DTBR)) blocked. The reason for this is that the data in the read data transfer buffer (DTBR) are unstable.

The definition of a new operating mode will possible, after all clock cycles determined by the latency have passed are. In the twelfth Cycle of the master clock signal K reach the row address strobe signal RAS # and the data transfer designation signal DTD # both the "L" level and the column address strobe signal CAS # the level "H". This sets the DRAM precharge mode. Hence returns the DRAM field returns to the precharge state and is for the next access ready.

28 shows the data flow in DRAM read transfer mode. As in 28 is shown, in DRAM read transfer mode a block with a predetermined number of memory cells of the selected row in the DRAM field 102 selected, and the data of the selected memory cell block becomes the read data transfer buffer 140 transfer. To ensure the DRAM read transfer mode, the DRAM address bits Ad0 to Ad3 are all set to "L". When operating the DRAM field section, an operation relating to the SRAM field can be carried out arbitrarily, with the exception of the DTBR blocking time. Accordingly, data writing or data reading can be performed by accessing the SRAM in parallel with the data transfer from the DRAM field to the read data transfer buffer (DTBR), and data can also be written to the write data transfer buffer (DTBW). It is important that the data transfer to the read data transfer buffer (DTBR) is not affected.

[DRAM write transfer mode]

In the DRAM write transfer mode, the data stored in the write data transfer buffer (DTBW) is written in the selected memory cell block of the DRAM array in accordance with the masking data stored in the masking register. As in 29 is shown, with the rising edge of the master clock signal K after the lapse of a predetermined period of time (after the lapse of the RAS / CAS delay time tRCD) from the execution of the DRAM active cycle, the row address strobe signal RAS # becomes "H" and that column address strobe signal CAS # and the data transmission determination signal DTD # are set to "L". This sets the DRAM write transfer mode. The DRAM address bits Ad4 to Ad11 supplied at this time are adopted as the column address Col for selecting a column block (memory cell block), and a selection process of a memory cell block is carried out. Data is transferred simultaneously from the write data transfer buffer (DTBW) to the selected memory cell block. To ensure operation in the DRAM write transfer mode, the DRAM address bits Ad0 to Ad3 must be set to "L". In the first clock cycle from the determination of the DRAM write transfer mode (the tenth clock cycle in 29 ) every new operation is blocked for the DRAM field.

In the cycle immediately after the first Cycle after the DRAM write transfer mode is set the masking data of the masking registers are all set (data transmission block), for an incorrect overwrite the next data to avoid.

As in 29 is shown, after the lapse of the RAS cycle time tRAS in the twelfth cycle of the master clock signal K, the row address scan signal RAS # and the data transfer determination signal DTD # are both set to "L" and the column address scan signal CAS # to "H" , This sets the DRAM precharge mode. In the first clock cycle after the DRAM write transfer mode has been determined, the write data transfer buffer (DTBW) is set to the locked state. More specifically, access to the write data transfer buffer is blocked in this cycle. Operations related to the SRAM field can be freely set and executed.

30 shows the data flow in DRAM write transfer mode. As in 30 is shown, those in the write data transfer buffer 144 stored data corresponding to that in the masking register 146 set masking data for the DRAM field 102 transfer. In the DRAM field 102 a row has already been selected and in DRAM write transfer mode a block is selected from a plurality of memory cells of the selected row. Data is sent from the write data transfer buffer 144 transferred to the selected block of a plurality of memory cells. How out 30 can be seen during this period the SRAM field 104 can be addressed, and so can the read data transfer buffer 140 be addressed.

Now a special structure of the DRAM area.

31 10 shows an example of the structures of the DRAM control circuit and the mask circuit of FIG 1 , As in 31 a K buffer is received 124 an external clock signal K and generates an internal master clock signal Ki.

A masking circuit 126 has a shift register 202 for delaying the DRAM clock mask signal CMd by one clock signal period of the internal clock signal Ki from the K buffer 124 and a gate circuit 204 for passing the internal master clock signal Ki in accordance with the delayed DRAM clock mask signal CMd from the shift register 202 on. As in 31 is shown, the gate circuit 204 formed by a p-channel MOS transistor (field effect transistor with insulated gate) which blocks the transmission of the internal master clock signal Ki when the delayed clock mask signal CMd is at "H". If the clock mask signal CMd is "H" in a certain cycle, the transmission of the internal master clock signal Ki is blocked in the next cycle, and therefore the generation of the DRAM master clock signal DK is interrupted.

The DRAM control circuit 128 has a RAS buffer 206 which takes over the row address strobe signal RAS # with the rising edge of the DRAM master clock signal DK in order to generate an internal row address strobe signal RAS, a CAS buffer 208 which latches the column address strobe signal CAS # with the rising edge of the DRAM master clock signal DK to produce an internal column address strobe signal CAS, a DTD buffer 210 , which is dependent on the DRAM master clock signal DK, for taking the data transfer determination signal DTD # with its rising edge to generate an internal data transfer determination signal DTD, and a DRAM control signal generating circuit 212 which takes over the internal control signals RAS, CAS and DTD with the rising edge of the DRAM master clock signal DK in order to determine the mode which is determined by the states of the signals and to generate the necessary control signals in accordance with the specified operating mode ,

The DRAM control signal generation circuit 212 also carries out a monitoring of the latency, which is necessary for the data transmission, in accordance with the DRAM master clock signal DK. The DRAM control signal generation circuit 212 generates various control signals which are necessary for driving the DRAM field area and for the data transfer operation between the data transfer circuit (read data transfer buffer and write data transfer buffer) and the DRAM field. In 31 are a transmission control signal? DT for controlling the operation of the transmission circuits, a RAS control signal? RA for controlling the operation of the circuits related to the RAS signal (such as the row selection operation in the DRAM array), and a control signal? CA for controlling the operation the circuit sections relating to the CAS signal (such as the selection of a column) are represented as representatives.

The address buffer 108 has a line buffer 214 from the DRAM master clock signal DK and the RAS control signal is dependent, for taking over an external DRAM address Ad and for generating a DRAM row address Adr and a column buffer 216 , which is dependent on the DRAM master clock signal DK and the CAS control signal? CA, for locking the DRAM address Ad and for generating a DRAM column address Adc. The row address Adr is sent to the row decoder 110 created the in 1 and a predetermined high order bit of the column address from the column buffer 216 is attached to the column block decoder 112 created the in 1 is shown. As will be described later, in some operating modes the column address Adc or Adr is used as the command value to the command register. The column address Adc is also used to determine the type of data transfer mode (this will be described later).

As described above, the DRAM control circuit controls 128 the operation of the DRAM array and the data transfer process between the DRAM array and the data transfer circuit. It is independent of the operation of the SRAM field area. As described above, the driving of the DRAM array and the data transfer between the DRAM array and the data transfer circuit can be carried out regardless of the states of the control signals sent to the SRAM control circuit 132 are fed.

[Chip layout]

32 shows a special layout of the CDRAM field. As in 32 is shown is the CDRAM 100 arranged on a rectangular chip. The CDRAM 100 has four DRAM memory sections DM1, DM2, DM3 and DM4, each with a memory capacity of 4MBit, SRAM memory sections SM1, SM2, SM3 and SM4, which are formed in the central region of the chip corresponding to the DRAM memory sections and each have a memory capacity of 4kBit , and data transfer circuits DTB1, DTB2, DTB3 and DTB4 formed between the DRAM memory sections DM1 to DM4 and the SRAM memory sections SM1 to SM4.

Each of the DRAM memory sections DM1 to DM4 is shown to be divided into 4 x 16 = 64 memory blocks MBA. The memory block MBA has memory cells which are arranged in 256 rows by 256 columns. The DRAM memory sections DM1 to DM4 each have 16 pairs of IO lines, which are arranged so that they pass through all the row blocks RB shown in the figure. In 32 a large global IO line pair BGIO is shown, which comprises four pairs of global IO lines. A global IO line corresponds to 64 columns of the DRAM field. One of the 64 columns is connected to a global IO line pair. In a DRAM memory section, 16 columns are selected at the same time. 4 columns are selected in the MBA memory block at the same time.

There are four pairs of local IO lines to connect the four columns selected at the same time with the global IO line pair educated. The local IO line pair is only in the corresponding memory block MBA used. In each of the DRAM memory sections DM1 to DM4 only the memory block is activated that contains the selected line (word line) contains and the other blocks of memory are kept in the precharge state. By going with this Partial activation procedure (block division procedure) can take up the line can be reduced.

Among the memory cells that are connected to the selected row of the DRAM, 16 columns of memory cells are selected, the data of the selected 16 bits of memory cells are transmitted to the local IO line pair and then to the global IO line pair. In 32 the expression "divided into four" indicates that four pairs of local IO lines LIO are formed in this divided block and are each connected to the large global IO line pair BGIO (four pairs of global IO lines) formed in the corresponding block are.

16 data transmission circuits in each of the Data blocks DTBl to DTB4 are formed according to the global IO line pairs. The SRAM memory sections SM1 to SM4 each have static ones Memory cells that are arranged in 256 rows of 16 columns. When transferring data becomes a row in each of the SRAM memory sections SM1 to SM4 selected and the data transmission between 16 bits of static memory cells with this one Line are connected, and the data transmission circuits executed.

Along the narrow side of the CDRAM 100 a DRAM row decoder and a row control circuit are arranged between adjacent memory sections. A DRAM row decoder / line control circuit RDC1 is arranged between the DRAM memory sections DM1 and DM3 and a DRAM row decoder / line control circuit RDC2 is arranged between the DRAM memory sections DM2 and DM4. The DRAM row decoder / row control circuit executes a row selection process in the corresponding memory section, drives the sense amplifier for acquiring and amplifying the data of the selected memory cell, precharges the bit lines, etc.

The SRAM control circuit and some of the DRAM control circuits are in the central portion of the CDRAM 100 arranged. The DRAM control circuits have a block decoder for selecting a column in the DRAM memory section, a circuit for controlling the column selection process, and various peripheral circuits. The SRAM control circuit has an SRAM row decoder, an SRAM column decoder and the in 1 SRAM control circuit shown.

In the central section of the CDRAM input / output circuits IO1 and IO2 are formed. The input / output circuit IO1 is used for data input / output of the DRAM memory sections DM1 and DM2 and the SRAM memory sections SM1 and SM2, which contain the input / output data Enter / output DQO and DQl. The input / output circuit IO2 leads one Input / output of the input / output data DQO and DQl in or from the DRAM memory sections DM3 and DM4 as well as the SRAM memory sections SM3 and SM4 off.

Because the data input / output in the central section of the CDRAM chip 100 is executed, the signal lines for performing data input / output can be made shorter. This enables data input / output at high speed. Because the SRAM memory section is located in the center of the chip, the data input / output connections for the SRAM memory section can be made shorter. This enables high-speed access to the SRAM.

[Field structure]

33 shows a structure for the SRAM array (the one shown in 32 SRAM memory section shown or that in 1 SRAM field shown). The SRAM field 104 has static memory cells SMC, which are arranged in a matrix of rows and columns. A row of static memory cells SMC is connected to an SRAM word line SWL, while a column of static memory cells SMC is connected to an SRAM bit line pair SBL. In 33 three SRAM word lines SWL1 to SWL3 are shown as representatives.

A static memory cell SMC exhibits both cross-coupled p-channel MOS transistors P1 and P2 as well as cross-coupled n-channel MOS transistors N1 and N2. The transistors P1 and N1 form a first inverter, while transistors P2 and N2 form a second inverter. The entrances and outputs of the first and second inverters are cross-connected to one another To form inverter latch circuit.

The static memory cell SMC has an n-channel MOS transistor N3, which depends on a signal potential on the SRAM word line, for connecting one Connection node of the transistors P1 and N1 with an SRAM bit line SBLa and an n-channel MOS transistor N4 by a signal potential dependent on the SRAM word line SWL for connecting a connection node of the transistors P2 and N2 with an SRAM bit line * SBLa on.

For each of the SRAM bit line pairs SBL is an SRAM sense amplifier SSA and a bidirectional transfer gate BTG is formed. The bidirectional Transfer gate BTG is with a global IO line pair GIOa or GIOb connected extending from the DRAM array as described later becomes. The transfer control signals shown as? TSD and? TDS are applied to the bidirectional transfer gate BTG.

At the in 33 As shown in the structure shown, the SRAM word lines SWL1 to SWL3 are each connected to memory cells, the number of which is equal to the number of data bits that are transferred with one data transfer operation between the DRAM field and the SRAM field (16 bits in this embodiment).

34 shows an arrangement for the DRAM array. 34 represents a section corresponding to one half of the memory block MBA of 32 More precisely, two pairs of global IO lines GIOa and GIOb and two pairs of local IO lines LIOa and LIOb are formed. A DRAM memory block MBij has a plurality of dynamic memory cells DMC, which are arranged in a matrix. A dynamic memory cell DMC has a memory transistor Q0 and a storage capacitor C0. A predetermined potential Vgg (usually an intermediate potential of Vcc / 2) is applied to an electrode (cell plate) of the storage capacitor C0.

The memory block MBij has DRAM word lines DWL, each with a row of DRAM cells (dynamic memory cells) DMC is connected, and DRAM bit line pairs DBL, each with a column of DRAM cells connected to DMC. The DRAM bit line pair DBL has complementary Bit lines BL and / BL on. The DRAM cell DMC is on the respective Cross between the DRAM word line DWL and the DRAM bit line pair DBL arranged.

For each DRAM bit line pair DBL is a DRAM sense amplifier DSA for capturing and amplifying the potential difference is formed on the corresponding bit line pair. The DRAM sense amplifier DSA has a p-channel sense amplifier section with cross-coupled p-channel MOS transistors P3 and P4 and an n-channel sense amplifier section with cross-coupled n-channel MOS transistors N5 and N6.

Operation of the DRAM sense amplifier DSA is from the sense amplifier driver signals /? SAP and? SAN controlled by the p-channel MOS transistor TR1 and n-channel MOS transistor TR2 depending from a sense amplifier activation signal /? SAPE and

The p-channel sense amplifier section raises the potential on the bit line with a higher potential to the level of the operating supply voltage Vcc depending on the sense amplifier drive signals /? SAP. The n-channel sense amplifier section discharges depending on the sense amplifier ker driver signals? SAN the potential of the bit line with a lower potential to, for example, the level of the ground potential Vss.

If the sense amplifier activation signal /? SAPE reaches the "L" level, the p-channel MOS transistor TR1 generates this Sense amplifier driving signal /? SAP with the level of the supply potential Vcc and transfers it to the supply node of the DRAM sense amplifier DSA. When the sense amplifier activation signal ? SANE reaches level "H", the n-channel transmits MOS transistor TR2 the sense amplifier driver signal? SAN with the level of the ground potential Vss to the other supply node of the DRAM sense amplifier.

Here the driver signal lines are to which the sense amplifier drive signals are transmitted are precharged to the intermediate potential Vcc / 2. For simplification the drawing is the circuit for precharging the driver signal lines of the sense amplifier not shown.

For each of the DRAM bit line pairs DBL is a precharge / equalization circuit DEQ formed that depending from a preload / equalization signal? EQ to preload the respective Bit line of the corresponding bit line pair to a prescribed Precharge potential Vbl and to equalize the precharge potential of the Bit line BL and / BL is activated. The precharge / equalization circuit DEQ has n-channel MOS transistors N7 and N8 for transmission of the precharge potential Vb1 to the bit lines BL and / BL and one n-channel MOS transistor N9 to equalize the potentials of the bit lines BL and / BL.

The DRAM memory block MBj has a DRAM column selection gate CSG that corresponds to the respective one of the DRAM bit line pairs DBL is formed and dependent conductive from a signal potential on a column select line CSL is made to the corresponding DRAM bit line pair DBL to connect the local IO line pair LIO. The column selection line CSL is together for two pairs of DRAM bit lines and two DRAM bit line pairs DBL are formed simultaneously selected. A pair of local IO line pairs LIOa and LIOb receive data from the two pairs of DRAM bit lines that are selected at the same time. For each of the local IO line pairs LIOa and LIOb is a precharge / equalization circuit similar to that Bit line equalization / precharge circuit DEQ formed. For simplification the precharge / equalization circuit is not shown in the drawings.

The memory block MBij also has DRAM-IO gates IOGa IOGb for connecting the local IO line pairs LIOa and LIOb with the global IO line pairs GIOa and GIOb depending from a block activation signal? BA. In CDRAM only one becomes Block in the selected State that has a selected line (word line). Only for this selected block the DRAM IO gates IOGa and IOGb are made conductive. The control signal count the For example, blocks are generated from the four high-order bits of the DRAM row address, the to select the Word line is used (in a structure in which only one row block of 16 line blocks (with 256 lines each) in the selected state).

[Data transfer operation: Page mode transfer mode]

The data transfer process between the DRAM field and SRAM field will now be described. In the following Description is the data transfer gate for a better understanding of the Data transfer operation simplified between fields.

35 shows a basic structure for the bidirectional transmission gate BTG. As in 35 the bidirectional transmission gate BTG has a 3-state buffer DR1, which is dependent on a transmission determination signal? TSD, for transmitting data on the SRAM bit line pair SBL to the global IO line pair GIO and a 3-state buffer DR2, which, depending on the carry determination signal, transmit the data on the global IO line pair GIO to the SRAM bit line pair SBL. The buffers DR1 and DR2 have a latch function. The data of the bidirectional transmission gate will be described later. First, the data transfer process from the DRAM field to the SRAM field is described with reference to this figure and the signal diagram of FIG 36 described.

There are before time t1 both the SRAM field and the DRAM field in the waiting state (precharge state).

The precharge determination signal state, the DRAM precharge / equalization circuit DEQ is in an active state, making it the DRAM bit line pair DBL precharges to a predetermined precharge potential and the Balances potential bit lines BL and / BL. More like that The potentials of the local IO line pair LIOa and of a global IO line pair GIO precharged to an intermediate potential (the circuit structure is not shown).

At time t1 when the precharge determination signal? EQ drops to "L", the precharge / equalization circuit DEQ is deactivated and the DRAM bit line pair DBL is set to an electrically floating state at a predetermined precharge potential. Similarly, the signal line that transmits the sense amplifier drive signals is also made to float at the intermediate potential Vcc / 2. Then the DRAM row decoder performs a row selection operation according to the supplied ones DRAM address signal off.

At time t2, a DRAM word line DWL is selected in the DRAM field and the potential of the selected word line DWL increases. The selected DRAM word line extends in all memory blocks MBA (MBij) contained in a row block. A row of memory cells connected to the selected DRAM word line DWL is connected to the corresponding DRAM bit line pairs DBL (the DRAM bit line BL or / BL) (the memory transistor Q0 is made conductive), and the potential of the DRAM Bit line pair DBL changes in accordance with the data of the connected memory cell. As in 36 memory cells are shown in three pairs of DRAM bit lines DBL1, DBL2 and DBL3 which store the value "1", and the associated bit lines BL (or / BL) are shown with a raised potential.

At time t3, the sense amplifier activation signal increases the driver signal ? SAN drops from the intermediate potential Vcc / 2 to "L" of the ground potential Vss down. The n-channel sense amplifier section, which is in the DRAM sense amplifier DSA is activated, and the potential of the bit line with the lower potential of the DRAM bit line pair DBL drops to the level of ground potential Vss.

This falls at time t4 Sense amplifier activation signal / Ärker driving signal /? SAP rises from the intermediate potential Vcc / 2 to the level of the operating supply voltage Vcc on. The p-channel sense amplifier section, which is in the DRAM sense amplifier DSA is activated, and the potential of the bit line with the higher Potential of the DRAM bit line pair rises to the level of the supply voltage Vcc on.

At time t5, a column selection line CSL is selected in accordance with a column selection signal from the DRAM column block decoder, and the potential of the selected column selection line CSL1 rises to "H". Consequently, in a memory block MBij, two pairs of DRAM bit line pairs DBL (four pairs of DRAM bit lines in the memory block MBA) are connected to the local IO line pairs LIOa and LIOb via the DRAM column selection gate CSG. The potentials of the local IO line pairs LIOA and LIOB (summarized in 36 denoted by the reference symbol LIO) change from the original potential Vcc / 2 in accordance with the data transmitted from the selected DRAM bit line pair DBL.

At time t6 the block activation signal rises for the block, the the selected one Word line contains to "H" and the DRAM-IO gate IOG (IOG collectively denotes the gates IOGa and IOGb) is switched through. Consequently, the signal potential on the local IO line pair LIOa to the global IO line pair Transfer GIO. The Definition of the selected one Memory block (of the block with the selected word line) is marked by Decode the higher order Bits of the row address signal, that to choose the DRAM word line is used.

No read is performed in the remaining unselected memory blocks and the precharge state is maintained. Due to the sequence of operations described above, only one memory block MBA of the 16 memory blocks MBA that are in 32 are arranged vertically, connected to the bidirectional transmission gate circuit (that is, connected to four bidirectional transmission gates BTGs).

In the SRAM, a row selection process is carried out by the SRAM row decoder at time ts11, an SRAM word line SWL is selected in the SRAM field (a total of four SRAM word lines) and the potential of the selected SRAM word line SWL (in 36 the SRAM word line SW1) rises to "H". The row selection process in the DRAM section and the row selection process in the SRAM section are carried out asynchronously because the determination of the buffer read transfer mode in SRAM is carried out independently of the DRAM read transfer mode in DRAM.

The respective data of the SRAM cells which are connected to the SRAM word line SWL are transmitted to the corresponding SRAM bit line pair SBL. The potential of the SRAM bit line pair SBL changes from the precharge potential (or equalization potential) Vcc / 2 according to the information stored in the corresponding SRAM cell. In 33 the circuit structure for equalizing the potential of the SRAM bit line pair SBL is not shown. If an access cycle to the SRAM is specified in CDRAM (i.e. access to the SRAM field is established with a rising edge of the master clock signal K), a single pulse signal can be generated to compensate for the SRAM bit line pair SBL.

At time t7, the data transfer designation signal rises to "H" for a predetermined period. The data of the DRAM cell has already been transmitted on the global IO line pair GIO, and the SRAM bit line pair SBL is connected to the SRAM cell. Depending on the data transmission determination signal? TDS, the bidirectional transmission gate BTG is activated and the signal potential on the global IO line pair GIO is transmitted to the corresponding SRAM bit line pair SBL. As a result, data transfer from the DRAM cell to the SRAM cell is carried out. As described above, two bits of DRAM memory cells are selected in a memory block NBij and the memory cell data is transferred to 16 pairs of global IO line pairs GIO. Therefore, a total of 16 bits of data from DRAM cells through the data transmission circuit become the at one time SRAM cells transmitted.

Provided that the time t7 at which the Data transfer designating signal ? TDS is activated after time t6 at which the block activation signal ? BA increases and after the time ts11 at which the SRAM word line SWL selected is, the temporal relationship between the points in time ts11, t1 and t6 can be any. The signal? TSD, which is a data transmission from SRAM field to the data field is set to one in this cycle kept inactive level "L".

At time ts12, the word line selection is in the SRAM field 2 completed. This also completes the data transfer of 16 bits from memory cells. At time ts21, the SRAM word line SWL in the SRAM field is again set to the selected state.

The DRAM word line DWL in the selected State maintained (because no DRAM precharge mode is set). To the Time t5 'when the DRAM read transfer mode is set again is, the column selection line CSLl in the unselected state and at time t5 'the next column selection line CS2 in the selected State shifted. This process is usually known as page mode. By Choose a new column selection line CSL2 changes at time t5 ' the potential of the local IO line pair LIO corresponding to the data of the memory cell, that of the column selection line CSL2 selected becomes. Alternatively, a structure can be used in which the Potentials of the local IO line pair LIO and the global IO line pair GIO once after deactivating the column selection line CSL restored to the precharge state become. While During this period, the block selection signal? BA is held at "H". The new data on the local IO line pair LIO become global Transfer IO line pair GIO. The active time of the column selection line can be determined by the latency become.

At time t7 ', this is again Data transmission signal ? TDS generated. At time t7 ', the potential of the global IO line pair GIO is already have been placed in the stable state and in the SRAM field are the Data of the memory cells that are new with the SRAM word line SWL2 have already been transferred to the SRAM bit line pair SBL been in and in a stable condition. 16 bits of data on the global IO line pair, GIO are about the bidirectional transmission gate BTG transferred at once to the 16 bits of memory cells that are connected to the SRAM word line SWL are connected.

At time ts22 the selection process is Word line SWL2 completed in the SRAM field, and at time ts31 a new SRAM word line SWL3 is selected. The selection / non-selection the word line SWL in the SRAM field is determined by the state combinations of Signals E #, WE # and CC1 # and CC2 # fixed. Because the SRAM with can work at high speed, it works faster than that High speed mode of the DRAM. Furthermore, at the time of data transfer the next one in SRAM new word line can be safely put into the selected state.

In the DRAM field at time t6 ' a column selection line DSL3 in the selected state and dependent on of which change the potentials on the local IO line pair LIO and the global one IO cable pair GIO. At time t7 'the data transfer determination signal ? TDS is generated and the data on the DRAM bit line pair DBL3 to the SRAM bit line pair Transfer SBL.

At time t1, the DRAM word line becomes DWL in the unselected State shifted, the data transfer cycle is completed and the DRAM field returns to the ready state (execution of the DRAM precharge).

The potential of the SRAM word line drops in the SRAM field SWL3 at time TS32 to the potential "L", and the potential of the SRAM bit line pair SBL returns to the precharge potential. Here is the potential of the SRAM bit line pair SBL in the standby state represented as an intermediate potential. With the help of a clamping transistor it can be pre-charged to the level of the supply potential.

The DRAM block decoder selects eight Column select lines CSL out at once. A column selection line CSL chooses two pairs of DRAM bit line pairs DBL. The data transfer from DRAM field to SRAM field is executed in parallel to the global IO line pair. Therefore 16 data bits transmitted together. By repeated execution of the data transfer cycle can the transferred Amount of data increased from 16 to 32.48 bits etc.

In the above description, the data transfer from DRAM field to SRAM field in one step. in the CDRAM of the present invention can perform the data transfer process from the DRAM field to the data transmission circuit and the data transfer process from the bidirectional data transmission circuit for SRAM field independent executed from each other become. However, the working principle is similar to that described above, and by using the DRAM sense amplifier in the DRAM array as a latch can be a big one Transfer the amount of data to the SRAM field at high speed using the page mode of the DRAM.

After the time TS32, the SRAM field section can be addressed externally. In contrast, the DRAM field in the DRAM cannot be addressed from the time t8 until the RAS precharge time tRP has elapsed. With the help of this structure, a large amount of data with ho speed are transferred from the DRAM field to the SRAM field and the transmitted data in the SRAM can be addressed externally at high speed. Therefore, for example, in the event of a cache miss, the data transferred from the DRAM field can be read immediately after this data transfer is completed.

By repeatedly executing the DRAM read transfer mode and the buffer read transfer mode of the SRAM, it becomes possible to have a plurality of data blocks to transfer from the DRAM field to the SRAM field.

37 shows schematically the data transfer process from the DRAM field to the SRAM field. With reference to 37 the data transfer process is described.

As in 37 is shown, the DRAM word line DWL1 is set to the selected state in the DRAM field. The data block D1 has a plurality of memory cells ( 16 Bits of memory cells in this embodiment) which are transferred by a transfer operation. The SRAM word line can be selected in the SRAM field at this time. It is important that the selection process should be completed before the transfer process from the DRAM field to the SRAM field is carried out (more specifically, before the data transfer process from the bidirectional transfer gate to the SRAM field is carried out).

As in 37 is shown, the data block D1 of the DRAM word line DWL1 in the DRAM field is transferred collectively to the selected memory cells of the SRAM word line SWL1 of the SRAM field via the bidirectional transmission gate BTG.

As in 37 data block D1 is set to the unselected state and in the SRAM field the next word line SW2 is set to the selected state. In this state, the data block D2 newly selected in the DRAM field is transmitted via the bidirectional transmission gate BTG to the memory cells of the SRAM word line SWL2. The data block D2 is then set to the unselected state and the SRAM word line SWL2 is set to the unselected state.

As in 37 is shown, a high-speed mode is executed (DRAM read transfer mode), the next data block D3 on the DRAM word line DWL1 is selected and the data are transferred via the bidirectional transmission gate BTG to the memory cells which are in SRAM with a newly selected SRAM word line SWL3 Field are connected.

By using the high speed mode of the DRAM (page mode) can handle a large amount of data at high speed as described above transferred to the SRAM field become.

In this embodiment, it is said in more detail the data transfer process of the bidirectional transmission gate executed in two steps. It is a first step in data transfer from the DRAM field to the bidirectional transmission gate and second step of data transmission from the bidirectional transmission gate to the SRAM field available. These data transfer operations will be run under the control of separate control systems. The can bidirectional transmission gate from the outside can be addressed directly by the buffer read or write mode is set. Therefore it is possible not just data transmission between the SRAM field and the DRAM, but also a block write mode in the data from outside be written one after the other. The SRAM field is in the unselected State, and therefore the data stored therein is not affected (provided that the operation takes place in buffer read or write mode).

38 shows a signal diagram of the data transfer process from the SRAM field to the DRAM field. In the 38 operating signals shown match those of 36 agree, except that the data transfer determination signal? TSD is generated instead of the data transfer determination signal? TDS, the direction of the data transfer from the SRAM field to the DRAM field is and the potential of the bit line pair DWL of the DRAM field corresponds to that of the SRAM field transferred data changes. In this case, an operation similar to that at the time of data transfer from the DRAM field to the SRAM field in the DRAM field and SRAM field is carried out, except that the specified mode of operation is different. More specifically, the buffer write transfer mode or the buffer write transfer / write mode is set in the SRAM field section, and the DRAM write transfer mode is set in the DRAM. Therefore, the detailed description of the process is not repeated.

39 shows schematically the data transfer process from the SRAM field to the DRAM field. In this case too, the only difference is that the direction of the data block transmission differs from that in the diagram of 37 shown differs. A detailed description is not repeated. By using this mode, not only high-speed data transfer from the SRAM field to the DRAM field, but also a block write mode can be implemented (because data can be written directly from the outside into the bidirectional transfer gate).

[IO section]

40 shows a structure for the IO area of the SRAM section. If at the in 1 The structure shown that the bidirectional transmission gate is addressed externally is via the SRAM field performed a data write and read. The SRAM field must be kept in the unselected state. The structure of the input / output section at this time is shown. Although no SRAM sense amplifiers SSA, which are formed for the respective SRAM bit line pair SBL, are not shown, one is formed for each SRAM bit line pair. An SRAM column selection gate 302 is formed for each of the SRAM bit line pairs SBL. A column selection signal CD from the column decoder ( 120 in 1 ) becomes the column selection gate 302 fed. A pair of SRAM bit lines is thus selected from the 16 bits of SRAM bit line pairs SBL.

The internal data bus 123 (please refer 1 ) has an external write data line pair 123a for transferring write data and read data transmission line 123b for transferring read data to the main amplifier circuit. The read data transmission line 123b can be formed from a pair of signal lines.

The internal write data line pair 123a has write data lines DBW and * DBW for transferring complementary data generated by the Din buffer circuit (input buffer circuit). The internal write data line pair 123a is with the write circuit 303 connected. The write circuit 303 amplifies the internal write data from the internal write data line pair 123a and transfers the amplified data to the internal data lines DBWa and * DBWa.

The write circuit 303 has n-channel MOS transistors T301, T302, T303 and T304. The gates of transistors T302 and T303 are connected to the internal write data line DBW. The gates of transistors T303 and T304 are connected to the internal write data line * DBW. The connection section of the transistors T302 and T304 is connected to the internal data line DBWa, and the connection section of the transistors T301 and T303 is connected to the internal data line * DBWa.

Transistors T301 and T302 transmit one Signal at the level of the supply voltage Vcc when it are leading. The transistors T303 and T304 transmit the ground potential Vss, if they are switched through. For the internal data lines DBWa and * DBWa is a sense amplifier SSAa for reinforcement the supplied Data formed. The data from the sense amplifier SSAa is transmitted to the main amplifier circuit. The operation will now be briefly described.

It is assumed that the value "H" is transferred to the internal write data line DBW. The value "L" is transferred to the internal write data line * DBW. The transistors T302 and T303 are turned on. Consequently, the value becomes "H" from the write circuit 303 transmitted via transistor T302 to the internal data line DBWa, while a value "L" is transmitted via transistor T303 to the other internal data line * DBWa.

When reading data, data "L" is transferred from the input buffer circuit (Din buffer circuit) to both internal write data lines DBW and * DBW. The output of the write circuit 303 assumes a high impedance state. The SRAM sense amplifier SSAa is activated. The SRAM bit line pair SBL is switched over the selected column selection circuit 302 connected to the internal data lines DBWa and * DBWa. The data transmitted to the internal data lines DBWa and * DBWa are amplified by the SRAM sense amplifier SSAa and then via the data transmission line 123b transmitted to the main amplifier circuit.

By using the structure of 40 data can be written directly into the data transfer buffer (bidirectional transfer gate circuit) via the SRAM field. However, if the bidirectional transmission gate BTG (or buffer circuit) is to be addressed via the SRAM field, it is necessary to connect the SRAM field to the transmission gate in order to release the balanced state of the SRAM bit line pairs SBL in the SRAM field. The SRAM word line is placed in the unselected state. As a result, the bidirectional transmission buffer (bidirectional transmission gate circuit) can be addressed externally via the SRAM field without influencing the data stored in the SRAM field. The reason for this is that a bidirectional transmission gate or bidirectional transmission buffer is formed for each of the SRAM bit line pairs.

Because the write data transmission line 123a and the read data transmission line 123b separated as an internal data line 123 are formed, the input / output circuit layout can be made simpler compared to a structure in which writing and reading of data is carried out via a common internal data bus.

[Data transmission buffer circuit]

In the above business description with the page mode operation is the bidirectional transmission gate BTG described as a 3-state buffer to simplify the description Service. The bidirectional transmission gate has a latch function.

The following is the operating mode described by the formation of the latch function for the bidirectional transmission gate is realized.

41 shows a more precise structure of the bidirectional transmission gate. The bidirectional transmission gate has a read transfer buffer 210 for receiving data from the DRAM field, that is, the data on the global IO line pair GIO, and a write transfer buffer 250 to receive data from the SRAM field (data that stored in the SRAM field, or externally created data).

The read transfer buffer 210 has a gate 212 , which is switched on in response to a data transmission determination signal? TDSl, a latch circuit 230 to lock the over the gate 212 supplied data, an inverter circuit 218 for inverting the latched data of the latch circuit 230 , and a gate 220 which is switched on in response to a transmission determination signal? TDS2 for transmitting the output data from the inverter circuit 218 to the SRAM bit line pair SBL. The latch circuit 230 has an inverter circuit 214 with a high driving capacity and an inverter circuit 216 with less propulsion. The output of the inverter circuit 214 is with the input of the inverter circuit 216 connected, and the output of the inverter circuit 216 is with the input of the inverter circuit 214 connected. Because the driving ability of the inverter circuits 214 and 216 differs, there is a function for locking data and, in addition, the data transmission can be carried out in one direction at high speed.

The write transfer buffer 250 has a gate 260 , which is switched in response to a transmission determination signal? TSD2, for transmitting the data to the SRAM bit line pair SBL, an inverter circuit 258 for inverting the over the gate 260 fed data, a latch circuit 232 to lock the output value from the inverter circuit 258 and a gate 252 , which is dependent on the transmission determination signal, for transmitting the output value from the latch circuit 232 to the global IO cable pair GIO. The latch circuit 232 has an inverter circuit 254 with a high driving capacity and an inverter circuit 256 with less propulsion. The output of the inverter circuit 254 is with the input of the inverter circuit 256 connected, and the output of the inverter circuit 256 is with the input of the inverter circuit 254 connected.

From the DRAM control circuit, which in 1 is shown, the transfer determination signals "TDS1 and" TSDl are generated in accordance with the row address scan signal RAS #, the column address scan signal CAS # and the data transfer determination signal DTD #.

From the SRAM control circuit 132 , in the 1 is shown, the transmission determination signals? TDS2 and? TSD2 are generated in accordance with the chip activation signal E #, the write activation signal WE # and the internal clock signals CCl # and CC2 #. With reference to 42 , which is an operation signal diagram, the operation of the bidirectional transmission buffer described in FIG 41 is shown.

As described above, the DRAM field and the SRAM field are driven independently of each other. As in 42 for the SRAM section from the first to the sixth clock cycle of the master clock signal K, the chip activation signal E # is at "L" and the write activation signal WE # and the control clock signals CC1 # and CC2 # are all at "H". This sets the SRAM read mode so that a static memory cell corresponding to the SRAM address As which is supplied with the rising edge of the master clock signal K is selected and the data of the selected memory cell is read.

In the DRAM section, the row address strobe signal RAS # falls to "L" with the third cycle of the master clock signal K. This determines the DRAM active mode, the DRAM address Ad that is being supplied at this time is adopted as the row address, and a row selection process is carried out. After the RAS / CAS delay time tRCD has passed, the column address strobe signal CAS # falls to "L". The transmission determination signal DTG # is at "H". As a result, the DRAM read transfer mode is determined, the DRAM address Ad currently applied is adopted as the block address, a memory block is selected in the DRAM field, and the data of the selected memory cell are transferred to the read transfer buffer (which in 41 shown transmission control signal

After the DTBR lockout time (which is determined by the latency) has elapsed, the control clock signal CC1 # falls to "L" in the SRAM section and the buffer read transfer / read mode is set. As a result, in 41 shown transmission control signal? TDS2 the level "H" and that in the latch circuit 230 latched data is transferred to the SRAM bit line pair SBL. The data transmitted to the SRAM bit line pair is further selected depending on the SRAM address As which is set at the time the SRAM read transfer / read mode is set, and thus data is read. More specifically, from the eighth cycle of the master clock signal of 42 new data bi, ... which are transferred from the DRAM field are continuously read.

In the eighth cycle of the master clock signal K reach both the row address strobe signal RAS # and the transmission direction determination signal DTB # the level "L", the DRAM precharge mode is set and that DRAM returns to the precharge state.

43 shows schematically the parallel operation of the DRAM and the SRAM. As in 43A is shown, the data reading is carried out in accordance with the externally created SRAM address As in the SRAM field. In parallel with the data reading process in the SRAM field, a row and a memory cell block MDBO are selected in the DRAM, and the selected memory cell block becomes MDBO transferred to the transmission buffer DTBR and stored there.

As in 43B is shown, the buffer read transfer / read is performed, data stored in the read transfer buffer DTBR is transferred to the SRAM field, and one bit of data is read from the memory cell data block MDBO (16 bits). Repeating this process enables high speed access.

Especially in graphics applications can do that next address to be known beforehand. To be more precise the data of a scan line on a cathode ray tube in succession addressed. The addresses of the data displayed on the monitor follow one another. Therefore, the address to be addressed next always be known. By using the CDRAM for graphics applications, the Graphic data can be processed at high speed by the next one data to be addressed are preselected in the DRAM field and this data locked in the read transfer buffer.

As will be described later, by using this operating mode, the sense amplifiers in the DRAM field can be used as an additional cache. This enables a reduction in the waiting time in the event of a cache miss. This process will be described in detail later. 44 shows a different mode of operation when the DRAM field and the SRAM field are operated in parallel. In contrast to the operation after 42 the process of in 44 is shown, after the tenth cycle of the master clock signal K, the DRAM read transfer mode is determined again. As a result, the data of another memory cell block of the DRAM row currently selected is transferred to the read transfer buffer.

In the (n + 1) th cycle of the master clock signal K the control clock signal CCl # is set to "L" and the control clock signal CC2 # is set to "H". As a result, the buffer read transfer / read mode fixed, the data stored in the read transfer buffer DTBR transferred to the SRAM field, and the data of the transmitted Memory cell data block will continue to be selected and read. Repeating this process can save a large amount of data can be read at high speed.

By using this mode of operation, that is, the high speed mode (page mode) of the DRAM, the data transfer operation can be carried out at high speed. More specifically, it is in the 43A and 43B shown operation performed repeatedly. The data transfer from the DRAM field to the SRAM field can be carried out in accordance with the page mode operation until the precharge mode of the DRAM field is determined. At this time, a data block can be transferred in the opposite direction from the SRAM field to the DRAM field in accordance with the page mode. Because data can be written directly into the write data transfer buffer circuit from the outside by executing the buffer write mode and then setting the DRAM write transfer mode, data can be written into the DRAM array according to the page mode.

[Mask register]

As in 1 a mask register is formed for the write data transfer buffer. The reason for this is that unnecessary data transfer to the DRAM field must be prevented when data is written externally to the write data transfer buffer in the buffer write mode. The function of the masking register is briefly described. Its detailed structure is described later along with the detailed structure of the bidirectional transfer gate.

45 shows an example of the structure of the mask register corresponding to a 1-bit write data buffer circuit. As in 45 is shown, the masking register 290 a latch circuit 261 made up of inverter circuits 266 and 268 there is a gate 262, which is dependent on a setting determination signal, for transmitting a signal with the supply level Vcc to the latch node LN, a gate 264 , which is dependent on a reset determination signal? R, for transmitting a signal with the ground level Vss to the latch node LN, and a gate 270 for the selective transfer of the output data from the write data transfer buffer (DTBW) 215 to the global IO line pair GIO according to the latch data of the latch circuit 261 on. When the setting determination signal is asserted, the mask register stores 290 Masking setting data and blocks the transfer of write data from the write data transfer buffer (DTBW) 250 , When the reset determination signal? R is applied, the mask register leaves 290 the data output by the write data transfer buffer (DTBW).

46 Fig. 10 shows an example of the structure of a control circuit for generating the masking data setting and reset determination signals. The masking data set / reset determination signal generating circuit has a decoder 272 for decoding the SRAM block address bits As0 to As3, an AND circuit 274 which the column selection signal CD of the decoder 272 and the buffer write mode determination signal? BW receives an OR circuit 278 which have an output signal from the AND circuit 274 and the buffer write transfer mode (with the buffer write transfer / write mode) determination signal? BWT receives a pulse generation circuit which is sensitive to the falling of the signal to generate a single pulse and an OR circuit 282 that have an output signal from the circuit 280 and the Masking data setting determination signal starts. The mask data reset signal? R is from the OR circuit 278 generated while the masking data setting signal 282 is produced.

More specifically, when the buffer write mode is set, the masking value is reset only for the write data transfer buffer to which the data is written. When data transfer from the SRAM field is specified, the masking data is reset for each bit. When the masking data setting signal is generated (command register described later), the masking register is set. When the mask activation signals MO to M3 are used, a structure is used in which the output signal from the gate circuit 274 is set to "L" when the mask enable signals MO to M3 are active.

47 shows schematically the function of the marker register. As in 47A is shown, only the masking value that corresponds to the written write transfer buffer is reset in the masking register MR when external write data (DQ) is written into the write data transfer buffer (DTBW). Therefore, in the DRAM write transfer mode for transferring data to the DRAM field, only the data that have been written into the write data transfer buffer DTBW are transferred from the transfer buffer.

In 47B data is transferred from the SRAM field to the write data transfer buffer DTBW. In this state, all masking data in the masking register MR are reset. Therefore, all data transmitted from the SRAM field is transmitted to the DRAM field.

By forming the masking register for the write data transfer buffer (DTBW) As described above, only the necessary data for the DRAM field written if data from outside be written directly into the write data transfer buffer.

By forming a masking register for the Write data transfer buffer As described above, CDRAM can not only be used as the main memory of the CPU are used, but also simply as memory for graphic data.

As in 41 is shown, it is possible to store data in the write data transfer buffer (from the SRAM field or from the outside) before the transfer of data to be read from the DRAM field to the read transfer buffer because the read transfer buffer and the write transfer buffer are formed separately. This enables high-speed access.

Because the masking register is formed only the necessary data is overwritten in the DRAM field (because the masking data is reset can be). Therefore, it is not necessary to pass data from the DRAM field once a read-modify-write process and read the data of the read Rewrite memory cell externally. Therefore, the required data overwritten at high speed become.

At the in 1 As shown in the structure of the bidirectional data transfer buffer circuit, the write data transfer buffer has an intermediate register in order to safely transfer the necessary data only to the DRAM field. Generally, when the DRAM write transfer mode is set and the DRAM array is active, the data of the write data transfer buffer is written to the specified memory cell block of the DRAM array. At this time, the masking register provides a mask against overwriting. The bit whose masking register is set is not described. The data transfer between the write data transfer buffer ( 144 in 1 ) and the intermediate register ( 142 in 1 ) is controlled by using the two least significant bits of the DRAM address Ad. The data transfer between the register 142 and the buffer 144 is completed in a cycle in which the RAS # latency has passed after the DRAM active command has been triggered and the CAS # latency has passed after the DRAM write transfer mode has been set. If the DRAM address Ad0 is "0", there is no data transfer between the registers 142 and 144 executed. A data transfer takes place if it is "1".

[DRAM self-refresh]

The memory cells of the DRAM field must be refreshed periodically. A self-refresh mode is formed for this purpose. 48 shows the states of various control signals in self-refresh mode. As in 48 for the DRAM self-refresh mode with the rising edge of the master clock signal K, the row address scan signal RAS # and the column address scan signal CAS # are set to "L" and the data transfer designation signal DTD # is set to "H". In the DRAM self-refresh mode, the output from an internally formed address counter is used as the line address, and a line selection process and a refresh process are performed. At the end of the refresh cycle, the value of the address counter is increased by 1. Although the structure for executing the DRAM self-refresh mode is not explicitly shown, it is in the DRAM control circuit 128 to 1 contain. In order to execute the operation mode for driving the DRAM array after the DRAM self-refresh mode, a DRAM precharge operation must be performed once. This is similar to the CAS before RAS refresh mode (CBR) in a standard DRAM. In this refresh mode, by executing the DRAM precharge mode, a line that is in an active state is not turned off selected state. This completes the refresh state.

The structure for executing the DRAM self-refresh mode is in the DRAM control circuit 128 to 1 contain. A structure can be used in which the states of the signals RAS #, CAS # and DTD # are monitored with the rising edge of the master clock signal K. When the predetermined conditions are set, it is determined that the DRAM self-refresh mode is set, and in accordance with the determination result, the count value of the address counter is supplied as a row address instead of the externally applied DRAM address Ad. More specifically, the state detection circuit of an ordinary standard DRAM can be used to use the states of the control signals RAS #, CAS # and DTD # in the CBR mode detection section.

Alternatively, an externally created DRAM address can be used as a refresh address.

[Command register setting mode]

The CDRAM has a (in 1 Command register (not shown) for setting the arrangement of the input / output ports, setting the latency in the DRAM read transfer mode and the latency of the DRAM write transfer mode, setting the output mode (latch-transparent and register mode), etc.

For the instruction register setting mode (SCR mode), with the rising edge of the master clock signal K, the row address strobe signal RAS #, the column address strobe signal CAS # and the data transfer determination signal DTD # are all set to "L" as in FIG 49 is shown. At this time, the DRAM address bits Ad0 to Ad11 are adopted as command data Cmd and the necessary internal mode is determined.

As in 49 is shown, the DRAM precharge mode is set in the third cycle of the master clock signal K, and after the RAS precharge time tRP has elapsed, in the seventh cycle of the master clock signal K the row address scan signal RAS #, the column address scan signal CAS # and the data transfer designation signal DTD # all set to "L". This sets the command register setting mode. With the rising edge of the master clock signal K of the seventh cycle, the DRAM address bits Ad0 to Ad11 are adopted as command setting data and the internal state is set. In the command register setting mode, the self-refresh of the DRAM field is carried out simultaneously. When accessing the DRAM field, it is necessary to raise a word line in the DRAM field after the rising edge of the master clock K as quickly as possible. For this purpose, the number of mode determinations should be kept as small as possible (in order to reduce the time required for the mode determination). Therefore, in the DRAM field, the self-refresh is carried out in the instruction register setting mode. In order to cancel the self-refresh, a precharge process is carried out in the twelfth cycle of the master clock signal K.

However, it is also possible Setting data in this mode only to be carried out in the command register, see above that the Operation of the DRAM at all unaffected becomes. You can implement that easily if you have one Structure uses the DRAM addresses Ad0 in the command register to Ad11 in SCR (command register setting) mode directly and not via the DRAM address buffer received.

50 shows in a table the correspondence between the command data and the content determined at that time. In 50 the DRAM address bits Ad11 to Ad7 are reserved for future expansion. Address bits Ad4 through Ad6 are used to set the access latency (the latency in DRAM read transfer mode and DRAM write transfer mode, that is, the number of clock cycles that determine the transfer clock in the data transfer buffer). Four different access latencies are prepared according to the rate (number of cycles) of the clock signal K.

The address bits Ad2 and Ad3 are used for setting output mode. If the two address bits Ad2 and Ad3 are at "L", the transparent output mode is set. Is the address bit Ad2 to "H" and the address bit Ad3 to "L", the latch output mode is set. Is the address bit Ad2 to "L" and the address bit Ad3 set to "H", the register output mode is set.

The address bit Ad1 is used for setting the output port configuration used. Is the address bit Ad1 at "L", the common DQ arrangement is fixed. In this Condition can Mask activation signals (masking data) for masking external write data can be entered. Is the address bit Ad1 to "H", the DQ separation mode is set. The input / output of Data is about separate connections executed.

The address bit Ad0 is used to set the masking data of the masking register. If the address bit Ad0 is at "L", the masking data of the masking register are not changed. If the address bit Ad0 is at "H", all masking data are set. The state of the masking data is not stable when switched on. Therefore, when a buffer write mode is executed in a dummy cycle and then data is transferred to the DRAM array, it is possible that the DRAM write transfer mode is performed with unstable masking data and that the mask formed in the initial cycle is unstable. To avoid such a condition, after the Turn on the masking data of the masking register all set. This process is described below.

51 shows the structure of the control system for the mask register data 46 , As in 51 the data for the corresponding global IO line pair GIO change in accordance with the potential that is transferred from the write data transfer buffer when the transfer determination signal for the write data transfer buffer DTBW increases for a predetermined time period (this period is determined by the latency) and when the masking data of the masking register 290 (please refer 45 ) are in the reset state. When the transfer of the write data transfer buffer is completed, the pulse generation circuit generates 280 a single pulse, a setting signal? S is generated and the data stored in the masking register are set.

In the initial state after switching on, the Masking data must be set exactly if data is appropriate buffer write mode is written to the write data transfer buffer and then have to the written data is transferred to the DRAM field. thats why it is necessary to set the masking data of the masking register, before the buffer write mode is executed. About this process to implement is a masking value of the masking register set by a command.

As in 52 a predetermined number of master clock signals K are transmitted to the DRAM section after the supply voltage has been applied to the CDRAM. At this point the blind cycle is executed. The row address strobe signal RAS #, the column address strobe signal CAS # and the data transfer designation signal DTD # are all "H". The DRAM thus enters the DRAM-NOP mode. The DRAM master clock signal DK is transmitted to the peripheral circuit, an operation is carried out in accordance with the applied master clock signal DK, and the peripheral circuit is initialized. This corresponds to the initialization operation of a standard DRAM. In this state, the masking data in the masking register are unstable.

If in this dummy cycle the DRAM write transfer mode accomplished the masking register can be safely set be transferred. In DRAM write transfer mode, however, there is a data transfer from the write data transfer buffer to the DRAM field. The data in the transfer buffer is unstable, so the state of the DRAM field becomes unstable. Therefore, the setting of the masking data of the masking register not in the dummy cycle using such a DRAM write transfer mode Cheap.

After the completion of the dummy cycle, the row address strobe signal RAS #, the column address strobe signal CAS # and the data transfer designation signal DTD # are respectively set to "L" to execute the command register setting mode. The masking setting signal for the masking register rises to "H" and the data of the masking register is surely put in the set state (see 45 ). 53 shows a structure for the section concerning the SCR mode. As in 53 is shown, the circuit relating to the SCR mode has an SCR mode detection circuit 400 , which depends on the states of the row address strobe signal RAS #, the column address strobe signal CAS # and the data transfer designation signal DTD # with the rising edge of the DRAM master clock signal DK, for detecting the determination of the SCR mode, a command register 402 that is from the SCR mode detection signal from the SCR mode detection circuit 400 a self-refresh mode detection circuit is dependent on adopting the address Ad being supplied at that time as a command value for generating a required signal 404 for detecting the determination of the self-refresh mode according to a combination of the states of the row address strobe signal RAS #, the column address strobe signal CAS # and the data transmission determination signal DTD # with the rising edge of the DRAM master clock signal DK, and a self-refresh control circuit 406 that from the self-refresh detection signal from the self-refresh mode detection circuit 404 is dependent on executing self-refresh mode.

The self-refresh control circuit 406 comprises an address counter and a multiplexer circuit for multiplexing the output of the address counter with an external address to apply the result to the address buffer or the DRAM row decoder. When the SCR mode is detected, the self-refresh control circuit performs 406 also the self-refresh of the DRAM depending on the SCR mode detection signal from the SCR mode detection circuit 400 out.

54 shows another example of the structure of the section related to the SCR mode. At the in 54 structure shown is only the command register 402 driven when the SCR mode is set. The self-refresh control circuit 406 is only driven when the self-refresh mode is set. The reason why the self-refresh of the DRAM field is only carried out when the SCR mode is set is to reduce the number of operating modes to be determined and to select the word line in the DRAM field as quickly as possible. As in 54 is shown, the instruction data can be stored in the instruction register even during the page mode and precharge operations of the DRAM field be set if only the command register is operated in SCR mode. Therefore, command data can be selectively changed in the operating cycle of the DRAM field.

55 shows an example of an operation sequence of the DRAM array with an instruction register setting mode for setting the instruction register. As in 55 is shown, the DRAM active mode is determined in the first cycle of the master clock signal K, and a row selection process is carried out in the DRAM field.

In the fourth cycle of the master clock signal K becomes the DRAM write transfer mode determined, a block of memory cells of the DRAM field is selected and the data stored in the write transfer buffer is saved to the selected one Transfer memory cell block. After a predetermined period of time (in the example shown, latency is the same 3) becomes the DRAM write transfer mode in the seventh cycle of the master clock signal K. set again. In the second write transfer mode, the ninth Cycle of the master clock signal K during the data transfer the command register setting mode set, that is, RAS #, CAS # and DTD # all reach level "L". The one about this Time supplied Address is adopted as the command value and set in the command register.

In the twelfth cycle, the DRAM write transfer mode set again, and data transfer from the write data transfer buffer to the DRAM executed. In the fifteenth Cycle of the master clock signal K, the DRAM precharge mode is set, and the DRAM field returns to the precharge state.

As in 55 is shown, the command data can be changed without affecting the operation of the DRAM field because the setting of the data for the command register is carried out only in the command register setting mode.

In order to implement this structure, the address bits Ad0 to Ad11 supplied to the DRAM field must be divided into those for selecting the row and column of the DRAM field and those for setting the command register. Is in 56 shown.

As in 56 is shown creates an address buffer 108 , which receives DRAM address bits Ad0 to Ad11, internal row and column addresses, locks the created address bits Ad0 to Ad11 as row address and column address and feeds them to the DRAM row decoder or the DRAM column decoder. Depending on the row address lock signal? RAS and the column address lock signal 402 takes ßbits Ad0 to Ad11 as command data depending on the detection signal for the command register setting mode. Because the DRAM address bits Ad0 to Ad11 the address buffer 108 and command register 402 supplied separately, the command data can be set without affecting the operation of the DRAM array when the command register setting mode is set.

57 shows a structure for controlling the input / output by the command data. As in 57 is shown, the command register 402 Latch circuits 410 . 412 . 414 and 416 that are dependent on the determination signal for the instruction register setting mode for locking the supplied DRAM address bits Ad11 to Ad0. Corresponding to the DRAM address bits Ad0 to Ad11, twelve latch circuits are formed, and four latch circuits of these are represented as representatives. The latch circuit 410 locks the DRAM address Ad1 and the latch circuits 412 and 414 lock the DRAM addresses Ad2 and Ad3.

The input / output section has an input circuit 424b , which is connected to the input data terminals D0 to D3, an input circuit 424a connected to the data input / output terminals DQO to DQ3 (Q0 to Q3), and an output circuit 422 connected to the data input / output terminals DQO to DQ3. The activation / deactivation of one of the input circuits 424a and 424b is from the input control circuit 423 executed. The input control circuit 423 activates one of the input circuits 424a and 424b in accordance with a signal from the latch circuit 410 that in the command register 402 is formed.

The output circuit 422 gives data to the internal data output line 421a are transmitted at a predetermined time according to the control signals? 1, /? 1 and 420 out. The data output mode includes a transparent mode .1, a transparent mode 2 , a latch mode and a register mode. The output control circuit 402 selects the output mode in accordance with the DRAM address bits Ad2 and Ad3 used by the latches 412 and 414 of the command register 402 are fed. The operation of the input control circuit will now be described.

58 shows a structure of the input control circuit and the input circuits. As in 58 is shown, the input control circuit 423 a buffer 435 that a command CM from a command register 402 receives an inverter buffer 434 to invert the command CM and a gate 436 that from an output signal from the buffer 435 is dependent on the transmission of the output signal from the input circuit 424b to the internal write data line 421b on.

The input control circuit 424a has an input buffer 431 for accepting the input signal DQ, which is applied in response to the DRAM clock signal DQ, and a gate circuit 432 for transferring the output signal of the input buffer 431 selective to the internal write data line 421b depending on an output signal from the input circuit 424b on. The entrance bepuffer 431 is deactivated (put into a state of high output impedance) when the output signal of the inverter circuit 434 that in the input control circuit 423 is formed, located on "L".

The command signal CM reaches the "H" level when the address bit Ad1 is at "H". This state indicates that the DQ disconnect state is set. More specifically, the input buffer 431 deactivated and the write data D are from the input circuit 424b to the internal write data transmission line 421b transfer. The input circuit 424b accepts the applied data D as a function of the DRAM master clock signal DQ and generates internal write data. If the address bit Ad1 is at "L", the command signal CM reaches the level "L". This state indicates that the ordinary DQ mode, that is, the mask activation mode is set. In the input control circuit 423 becomes the gate 436 put in the locked state. The output signal of the input circuit 424b does not become the internal write data line 421b transfer. The masking data M are from the input circuit 424b output. The input buffer 431 accepts the data in accordance with the DRAM master clock signal DK and in accordance with the masking data M and selectively transmits the internal write data via the gate 432 to the internal write data transmission line 421b , This allows masking to be performed while data is being written.

59 shows an example of a special structure of the output circuit. As in 59 is shown, the output circuit 422 a first output latch 981 that of control signals 420 depends on the locking of data on the read data buses DB and * DB (data line 421a ), a second output latch 982 , which is dependent on a clock signal, for transmitting latch data of the first output latch 981 or of data on the data buses DB and * DB, and an output buffer 983 , the data from the output latch 982 receives and from the output signal from the gate circuit 984 is dependent on transferring the data as output data to an external connection DQ. The gate circuit 984 receives a signal locked state, and an output enable signal? G, which is generated in synchronism with the output enable signal G #. If the output signal of the gate circuit 984 is at "H", the output buffer 983 placed in a state of high output impedance.

The first output latch 981 has clock signal inverters ICV1 and ICV2, which are activated as a function of clock signals? 1 and /? 1. The input or output of the clock signal inverter ICV1 is connected to the output or input of the clock signal inverter ICV2. When the clock signal? 1 is "H", the clock signal inverters ICV1 and ICV2 are activated, and thus the first output latch 981 placed in the locked state. If the clock signal? 1 is at "L", the clock signal inverters ICV1 and ICV2 are deactivated. Hence the first output latch 981 no locking process.

When the clock signal? 2 is "L", the second output latch latches 982 the data supplied to its inputs A and * A and delivers them to the outputs Q and * Q. Is the clock signal 982 at the outputs Q and * Q from the data that were locked when the clock signal? 2 was at "L". This happens regardless of the signal states at inputs A and * A. The clock signals? 1, /? 1 and? 2, which control the locking process, represent signals which are synchronized with the master clock signal K (DRAM master clock signal DK), and the times of their generation are determined by the output control circuit 420 controlled.

60 shows an example of a special structure for the second output latch 982 , As in 60 is shown, the second output latch 982 a D flip-flop DEF, which eats the clock signal at its D input, the signal applied to input A (* A) and its clock signal input CLK. At the output Q of the D flip-flop DEF, the output signal Q (* Q) of the second output latch 982 issued. The D flip-flop DFF works with falling edge triggering takes over the signal fed to input A when the clock signal drops. It outputs the adopted input signal A continuously as long as the clock signal

If the clock signal? 2 is at "H", it outputs the previously locked data continuously regardless of the state of the input signal A which is fed to its input terminal D. D flip-flops DFF are formed for the inputs A and * A, respectively. The second output latch 982 may have a different structure, and any circuit structure may be used, provided that it has the latch state and the pass state depending on the clock signal

61 shows an example of a special structure of the output control circuit 420 , The output control circuit 420 has delay circuits 981a . 981b and 981C , for delaying the master clock signal K by a predetermined period of time, a single pulse generation circuit 982a from the output signal of the delay circuit 981a is dependent, for generating a single pulse signal with a predetermined pulse width, a single pulse generating circuit 982b by the output signal of the delay circuit 981 is dependent for generating a single pulse signal with a predetermined pulse width and a single pulse generating circuit 982 by the output signal from the delay circuit 981C is dependent on generating a single pulse signal with a predetermined pulse width. From the single pulse generation circuit 982a the clock signals? 1 and /? 1 are generated. The Output signals from the single pulse generation circuits 992b and 992c become an OR circuit 993 fed. The OR circuit 993 generates the clock signal by the delay circuit 991b is shorter than that by the delay circuit 991c , The single pulse generation circuits 992a to 992c are activated / deactivated in accordance with a command value which is generated from two bits of the address bits Ad2 and Ad3 from the command register. When these two bits of command data (addresses Ad2 and Ad3) indicate the latch mode as the output mode, the single pulse generating circuits 992a and 992c activated and the single pulse generation circuit 992b is deactivated. With reference to the 59 to 61 the operation of the data output circuit is described.

(i) Latch output mode.

In 62 the operating signals are shown in the latch output mode. The latch output mode is set by setting the address bit Ad3 to "L" and the address bit Ad2 to "H" in the command register setting mode. At this time, the single pulse generation circuits are 992a and 992c activated. It is assumed that the output enable signal G # is active "L", which indicates the data output, and that the gate circuit 994 of 59 the main amplifier 993 activated. It is also assumed that the SRAM read mode has been set as the output mode.

With the rising edge of the master clock signal K the SRAM address As (An) is transferred to the address buffer, in the SRAM field corresponding SRAM word line SWLn selected and data RDn appear on the SRAM bit line pair SBL.

The single pulse generation circuit 992a generates a single pulse depending on the rise of the master clock signal K, which is held at "L" for a predetermined period of time at a predetermined time. When the clock signal? 1 drops to "L", the latch function of the first output latch 981 blocked. The clock signal is at this time 982 maintains the lock state to lock and output the data Qn-1 read in the previous cycle.

Among 64 bits (16 × 4) of the data RDn on the SRAM bit line pairs SBL selected according to the external address As, four bits of data selected according to the block address are transferred to the internal output data buses DD and * DD , The clock signal? 1 rises to "H" as soon as the data DBn on the data buses DB and * DB are stabilized. This will be the first output latch 981 placed in the lock state to lock the stabilized data DBn.

Subsequently, a single pulse from the single pulse generation circuit 992c generated and the signal drops to "L". The second output latch 982 accepts the data DBn from the first output latch 981 have been locked, new depending on the drop of the signal transfers the data via the output buffer 983 to the output port DQ.

The generation of the clock signal? 2 is carried out in synchronization with the drop in the master clock signal K, and depending on the drop in the master clock signal K, the data DBn selected in this cycle are output as output data Qn. The next rise in the master clock signal K causes the clock signal? 2 to rise to "H". The second output latch 982 outputs the stabilized data DBn continuously regardless of the value on the internal output data buses DB and * DB.

Then the clock signal? 1 drops to "L" and gives the latch state of the first output latch 981 free so that it is ready for the next cycle, that is to say for the next stable data to be locked. By repeating the above-described operations, data read in the previous cycle is successively output as stabilized data depending on the rise of the master clock signal K.

(ii) Register output mode.

The register output mode is referenced to 63 described. The register output mode is set by setting the address bit Ad3 to "H" and the address bit Ad2 to "L" in the instruction register setting mode. In the register output mode, the single pulse generation circuit 992b activated and the single pulse generation circuit 992c is deactivated. In this case, a single pulse falling to "L" becomes dependent on the rise of the master clock signal K from the single pulse generating circuit 992b generated. Because the clock signal latch 992 locks data DBn-1 that was read in the previous cycle.

In the register output mode, the time at which the clock signal drops is determined by the rise of the master clock signal K. Therefore, in the (n + 1) th cycle of the master clock signal K, the data DBn of the nth clock cycle are output as output data Qn at the output terminal DQ. More specifically, the latch output mode and the register output mode differ only in the time of activation, that is, the time of the transition of the clock signal? 2 to "L". Therefore, both the latch output mode and the data read in the immediately preceding cycle are output, and then data read in the current cycle as well as the register output mode are output in data that were read in the nth cycle are output in the (n + 1) th cycle.

(iii) Transparent output mode.

With reference to 64 the transparent output mode is described. First, referring to 64A described the first transparent output mode. The first transparent output mode is set by setting the address bits Ad2 and Ad3 to "L". In the first transparent output mode, the clock signals? 1 and? 2 are kept at "L". At this point, the first output latch runs 981 no lock out, and also the internal output latch 982 is in the on state. Therefore, in this case the read data DBn, which have been transmitted to the internal data buses DB and * DB, are not locked, but rather are output directly as output data Qn. Therefore, if the value on the SRAM bit line SBL is invalid (INV), invalid data INV appears at the output terminal DQ.

The second transparent output mode (transparent 2) is set by setting the address bits Ad2 and Ad3 to "H". As in 64B is shown, the clock signal? 1 is generated when the second transparent output mode is set. The first output latch runs during the clock signal 981 a locking process. Therefore, even if the value RDn on the SRAM bit line pair SBL is invalid, the value on the data buses DB and * DB from the first output latch 981 locked as a valid value and output for a predetermined period of time (as long as the clock signal? 1 is at "H"). Therefore, the time period during which invalid data INV is output becomes shorter. The clock signal is also in the second transparent output mode

In the structure described above, a D flip-flop with falling edge triggering becomes the second output latch 982 used. A latch circuit with rising edge triggering can be used when the polarity of the clock signal is changed. The first output latch 981 can be implemented by other latch circuits.

In the operating signal diagrams of the 62 to 64B the chip activation signal E # and the output activation signal G # are both kept active "L". This indicates that no high impedance state should be set in each clock cycle. The setting of the high impedance output state by the chip activation signal E # and the output activation signal G # will now be described.

[Data output timing]

[Transparent output mode]

The 65A and 65B show the relationship between the output data and the chip activation signal E # and the output activation signal G # in the transparent output mode. In transparent output mode, the data is transferred directly to the output buffer on the internal data buses DB and * DB. If the chip activation signal E # with the rising edge of the master clock signal K is at "H", the SRAM blocking state is assumed and the output state of high impedance is set. When the output enable signal G # is "H", the output state of high impedance is set.

It is assumed that the output enable signal G # is already active "L" as in 65A is shown. In this state, data reading is performed in this cycle when the chip activation signal E # is at "L" with the rising edge of the master clock signal K. After the time period tKHQZ has passed from the rising edge of the master clock signal K, the output state of high impedance is released and read data are transmitted. After the time period tKHA has passed from the rising edge of the master clock signal K, valid data are output.

Is the chip activation signal E # becomes "H" with the rising edge of the master clock signal the state of high output impedance set after the period tKHQX has elapsed from the rising edge of the master clock signal K.

When a data read operation is performed as the chip activation signal E # drops to "L" for the rising edge of the master clock signal "K", as in FIG 65B is shown, this cycle becomes a data read cycle. If the output activation signal G # falls to "L" after the chip activation signal E #, this cycle (cycle 1 in 65B ) Read data is output as valid data after the time tGLQ has elapsed since the output activation signal G # fell. Similarly, when the chip enable signal E # is set to "L" with the rise of the master clock signal K, the data read in this cycle (cycle 2 ) issued in a similar state as in 65A is shown. In this cycle, if the output enable signal G # is raised to "H", the output state of high impedance is set after the lapse of the period tGHQ.

The states of the signals in the 65A and 65B indicated by dashed lines show that the output value represented by the dashed line appears when the state indicated by the dashed line of the chip activation signal E # is set.

[Register Output mode]

This is an output mode in which an output register is formed between the output buffer and the internal data buses DB and * DB. The data is output with a delay of one cycle. As in 66A the first cycle of the master clock signal K is more specifically a read mode if the chip activation signal E # is lowered to "L" in the first cycle of the clock signal K while the output activation signal G # is at "L". The one in the cycle 1 read data will be in the next cycle 2 read. That is, the read data is output after the lapse of the time period tKHQZ from the rising edge of the next master clock signal, and valid data is output after the lapse of the time period tKHAR. After the lapse of the time period tKHQX from the rising edge of the master clock signal K in the next clock cycle 3 the output state of high impedance is set. Will be in the cycle 2 the chip activation signal E # is set to "L" again in the cycle 3 valid data as given by the dashed line in 66A is shown.

It is assumed that the data read operation is carried out by lowering the chip activation signal E # in the state of high output impedance with the output activation signal G # at "H" to "L". As in 66B is shown in this state, the in the cycle 1 Read data after the lapse of the time period tGLQ from the drop of the output activation signal G # in the second cycle as valid data. If the chip activation signal G # is "L" in the second cycle, in the cycle 3 valid data output. The output enable signal G # in the clock signal cycle 3 raised to "H", the output state of high impedance is set after the lapse of the time period tGHQ.

[Latch Output Mode]

The latch output mode represents an output mode in which an output latch circuit is formed between the output buffer and the internal data buses DB and * DB. It is assumed that the data read operation is carried out by lowering the chip activation signal E # to "L" in the first cycle of the master clock signal K (as in FIG 67A is shown). In this case, data is output in the first cycle after the lapse of the time tKLQZ from the falling edge of the master clock signal K. After the time period tKLA has elapsed from this falling edge, valid data are output. After the lapse of the time tKLQX from the falling edge of the clock signal of the next clock signal cycle (cycle 2 ) the data is set according to the initial state of high impedance. The chip activation signal is E # in the cycle 2 has been lowered to "L", data is output after the lapse of the period tKLQZ from the fall of the master clock signal K (as shown by the broken line). At the in 67A In the process illustrated, the output activation signal G # is already at "L". As in 67B is shown, it is now assumed that the output enable signal G # later drops to "L". If, by lowering the chip activation signal E # in the first cycle of the master clock signal K, data reading is carried out, and in this first cycle of the master clock signal K the output activation signal G # is lowered to "L", those in the cycle 1 read data after the lapse of the time tGLQ from the falling edge of the output activation signal G # output. Will be in the cycle 2 Data read again is carried out in this cycle 2 read data after the lapse of time tKLQZ from the falling edge of the master clock signal K in the cycle 2 output. If the output activation signal G # is subsequently raised to "H" (provided that no output control is carried out by the chip activation signal E #), after the lapse of the time period tGHQ, the output state of high impedance is set from the rising edge of the output activation signal G #.

Is in transparent output mode the period of time during the valid the output data are only the period of time during which valid data is on the internal Buses appear. In this latch output mode the read data for output locked, and therefore become valid Data even during of the period spent while the invalid Data appear on the internal data buses. Therefore, it can be sufficient Period of time available to be asked for the CPU or other device as an external processing unit is necessary to accept the output data. In this register output mode the data of the previous cycle is output with a delay of one cycle. In this case, a so-called pipeline operation can be implemented which realizes high-speed data reading leaves. By Set the output modes described above in accordance With the command data in the command register, a user can do that Select output mode, the for the system is suitable.

[Signal parameters]

68 shows the setting and holding times required for the respective signals in a table. The operating mode of the CDRAM is determined by the state combination of the control signals with the rising edge of the master clock signal K. sets, and the CDRAM executes the specified operation according to the determined operating mode. The externally applied signals are all supplied in the form of pulses. The set time required for the external signals (the time required to set the signal to a stable level with the rise of the master clock signal K) and the hold time (the time to maintain the stable state of the signal after the rise of the master clock signal K is required) match for all external signals. Therefore, an external device can easily determine the timing of signal generation because the timing for generating signals and the timing for setting the signals to a stable state can be made the same for all signals.

The minimum clock cycle time of the master clock signal K is 8ns and the maximum clock cycle time is 100ns. The Master clock signal K has an "H" time tKH and an "L" time tKL. The DRAM clock mask signal CMd has a response time tCMDS and a hold time tCMDH. The row address strobe signal RAS # has a settling time tRS and a hold time tRH. The column address strobe signal CAS # has one Response time tCS and a hold time tCH. The data transfer designation signal DTD # has a response time tDTS and a hold time tDTH. The SRAM clock masking signal CMs has a response time tCMsS and a hold time tCMsH. The chip activation signal E # has a setting time tES and a holding time tHE.

The write activation signal WE # has a response time tWS and a hold time tWH. The control clock signal CC1 # has a setting time tC1S and a holding time tCiH. The Control signal CC2 # has a response time tC2S and a hold time tC2H. The DRAM address bits Ad0 to Adll and the SRAM address bits As0 to Asll have a response time tAS and a hold time tAH on. The mask activation signals N0 to N3 have a response time tMS and a holding time tMH. The input data DQO to DQ3 or D0 to D3 have a response time tDS and a hold time tDH. The Response time is at least 2 until during the hold time is at least 3 to 4ns. The rise / fall time of the internal signal is 2ns (if it is in the range of 0V to 3V changes).

[Connection arrangement]

69 shows the shape of a housing containing the CDRAM according to the present invention, as well as the connection arrangement. The CDRAM is in a Type II TSOP (thin small outline package), with a connection distance of 0.65mm and 400mil thickness.

The connections with the numbers 1 . 15 . 17 . 31 . 46 and 48 a supply voltage Vcc is supplied. The ground potential Vss is the connections with the numbers 12 . 16 . 20 . 32 . 43 . 47 . 51 and 62 fed. The DRAM address bits Ad0 to Ad11 are connected to the connections with the numbers 2 to 4 . 28 to 30 . 33 to 35 and 59 to 61 created. The SRAM address bits As0 to As11 are the connections with the numbers 22 to 24 . 37 to 41 and 53 to 56 fed. The control clock signals CC2 # and CC1 # are the connections with the numbers 5 and 6 fed. The write activation signal WE # and the chip activation signal E # are the connections with the numbers 7 or 11 supplied. The DRAM clock masking signal CMd and the SRAM clock masking signal CMs are connected to the connections with the numbers 9 respectively. 10 created.

The master clock signal K is fed to the connection with the number 11. The row address strobe signal RAS #, the column address strobe signal CAS # and the data transfer designation signal DTD # become the terminals with the numbers 25 to 27 fed. The input data D0 to D3 or the mask activation signals M0 to M3 are connected to the terminals with the numbers 13 . 19 . 44 and 50 created. The connections with the numbers 14 . 18 . 45 and 49 output data Q0 to Q3 are used, or they are used as input / output data terminals DQ0 to DQ3.

The connections with the numbers 36 . 42 . 52 . 57 and 58 are not connected (NC).

At the in 69 In the connection arrangement shown, the supply voltage Vcc and the ground potential Vss, which are supplied in the middle section of the housing, are used for the data input / output section. The ground potential Vss and the supply voltage Vcc that correspond to the connections with the numbers 12 or 15 are used to drive the data M0 / D0 and DQ0 / Q0, which are connected to the connections with the numbers 13 and 14 occur. The supply voltage Vcc and the ground potential Vss, the connections with the numbers 17 and 20 are supplied are used for the circuit that the data DQ1 / Q1 and M1 / D1 on the connections with the numbers 18 and 19 drives. The ground potential Vss and the supply voltage Vcc connected to the connections with the numbers 43 and 46 are used for the circuits for driving the data M2 / D2 and DQ2 / Q2, which are connected to the connections with the numbers 44 and 45 occur. The connections with the numbers 48 and 51 The supplied supply voltage Vcc and the ground potential Vss are used for the circuit for driving the data DQ3 / Q3 and M3 / D3, which are connected to the connections with the numbers 49 and 50 occur. The supply voltage and the ground potential are distributed to the respective circuits in such a way that the influence of internal interference is reduced.

In the embodiment described above, data input / output is carried out over the bit lines of the SRAM array. The dates Output / output can also not be carried out via the bit lines of the SRAM field, but the data can be input / output via the connection section of the SRAM field and the bidirectional transmission gate. In this case, a sense amplifier / IO block 122 and the SRAM column decoder 120 between the SRAM field 104 and the bidirectional data transmission circuit 106 the structure of 1 be arranged.

For those in 1 structure shown, the four command bits (command (0) to (3)) have not yet been described by the DRAM address buffer 108 to the bidirectional data transmission circuit 106 be created. These are used to set the mode in the data transmission circuit, and they can be used similarly in the second embodiment. Therefore, the details will be described later.

Embodiment 2

70 shows the overall structure of a CDRAM according to a second embodiment of the present invention. In 70 are the sections that are the components of the in 1 shown CDRAM correspond with the same reference numerals and therefore their detailed description is not repeated here.

In the CDRAM, which in 70 is a column decoder 120 and a sense amplifier / IO block 122 between the bidirectional data transmission circuit 106 and the SRAM field 104 educated. This structure enables direct access to each buffer of the bidirectional data transmission circuit 106 from the outside.

This in 70 CDRAM shown has a masking circuit 1436 and a din buffer 1434 which receive external data DQ0 to DQ3 and M0 to M3 (or D0 to D3) in an input / output circuit 1435, and a main amplifier circuit 1438 to output data to the terminals DQ0 to DQ3 (or Q0 to Q3). The data output clocking to the main amplifier circuit 1438 from the input / output circuit 1435 is set by the external output enable signal G # and the data input / output clock is set by a DQ control signal DQC.

The DQ control signal DQC only controls the activation / deactivation of the input / output circuit 1435. If the DQ control signal DQC is at "H", the input / output circuit is activated. If the DQ control signal DQC is "L", the Din buffer 1434 who have favourited Masking Circuit 1436 and the main amplifier circuit 1438 disabled. In the common DQ arrangement, the write activation signal WE # determines whether the Din buffer circuit 1434 or the main amplifier circuit 1438 should be activated.

In the CDRAM, which in 70 is shown, the chip select signal CS # of a K buffer clock signal generating circuit 1424 fed. The K buffer clock signal generation circuit 1424 also receives an external master clock signal K. The chip select signal CS # controls only the operation of the DRAM field, the operation of the SRAM field, the data transmission between the DRAM field and the SRAM field, the data transmission between the data transmission circuit and the DRAM Field as well as the data transmission between the data transmission circuit 106 and the SRAM field. The other structures are essentially the same as those in 1 are shown. That of the SRAM control circuit 143 supplied control clock signal is referred to as the control clock signal CCO # or CCl #. With the changed designation of these signals, the types of data transmission have also changed. The data transfer process will be described in detail later.

Also in 70 CDRAM shown are memory cell blocks (16 bits) at once in a DRAM field 102 (a storage section) by the column block decoder 112 selected. In the SRAM field 104 16 bits of memory cells are connected with one row. Accordingly, the bidirectional data transmission circuit has 16-bit transmission gate buffers. The function of the DQC control DQC is described.

[DQ Panel]

71 shows a special structure of the K buffer clock signal circuit and the marker circuit shown in FIG 70 are shown. In the CDRAM 70 becomes the activation / deactivation of the DRAM control circuit 128 and the SRAM control circuit 432 controlled by the chip selection signal CS #. In the CDRAM from 1 only the SRAM control circuit 132 controlled by the chip activation signal E #. Therefore, the control signal buffer (a circuit for locking external control signals) operates in the DRAM control circuit 128 is included, only depending on the DRAM master clock signal DQ, as in 31 is shown. At the in 70 DRAM shown, both the DRAM control circuit and the SRAM control circuit take over the applied data in accordance with the master clock signal K and the chip selection signal CS #. In 71 are the SRAM control circuit and the DRAM control circuit as the control circuit 1452 shown.

As in 71 is shown, the K buffer clock circuit 1424 a K buffer 1460 , which receives the master clock signal K, for generating an internal clock signal and a CS buffer 1462 , which is dependent on an internal clock signal K buffer, for taking over the chip selection signal CS #. The masking circuit 1450 (referring to the masking circuit 126 and 130 relates that in 70 are shown) has a shift register 1464 that from the internal clock signals K buffer 1460 is dependent on outputting the clock mask signal CM with a delay of one clock cycle and a selection gate 1466 for selectively passing the internal clock signal from the K buffer 1460 for generating the master clock signal Ki in accordance with the masking data from the shift register 1464 on. In this second embodiment, when the mask value CM is at "L", the generation of the internal master clock signal Ki is inhibited.

The control circuit 1452 is activated when it receives the internal chip select signal CS from the CS buffer 1462 receives INA at its activation input. The control circuit 1452 operates in accordance with the master clock signal Ki from the masking circuit 1450 when it is in the active state. If the chip selection signal CS is at an inactive level "H", the CDRAM is therefore not selected and the control circuit 1452 is deactivated.

72 shows a structure for the control circuit 1452 , The output activation signal G # is generated asynchronously to the master clock signal K. At this point in time, the DQ control signal DQC can be generated asynchronously to the master clock signal K.

The activation / deactivation of the DRAM control circuit and the SRAM control circuit is controlled by the chip selection signal CS. The external control clock signals RAS #, CAS #, DTD #, CCO #, CC1 #, DQC and WE # are taken over in accordance with the master clock signal K and the chip selection signal CS. Therefore, the structure of the buffer circuit that takes over the external control signals matches that of 6 match. Hence the control signal buffer 1480 shown, the buffer for taking over the external control clock signals. The control clock signal

As in 72 is shown, the control circuit 1452 a control signal buffer 1480 , which is dependent on the master clock signal K and the chip selection CS #, for taking over the external control clock signal? E and a control signal generating circuit 1482 , which is dependent on the chip selection signal CS and the master clock signal Ki, for generating the necessary control signals in accordance with a combination of states of the control signals from the control signal buffer 1480 be created on.

The DRAM address buffer 108 has the same structure as in 31 shown on, and the SRAM address buffer 116 has the same structure as in 6 (except that the chip select signal CS is applied instead of the chip activation signal I). The structures of the K buffer and the CS buffer are the same as those in FIG 7 are shown. As in the 71 and 72 is shown, the control circuit 1452 disabled when the chip select signal CS is "H", and therefore no internal operation is performed. This state does not affect the signal states of the clock mask signal CM. More specifically, the control circuit 1452 deactivated when the chip selection signal CS is "H", regardless of whether the master clock signal Ki is applied or not.

If the clock mask signal CM is at "L", the master clock signal Ki is not generated in the next cycle. As from the in 72 The structure shown can be seen in the control circuit 1452 No new external control signal? E # is taken over when the clock mask signal CM reaches a level "L", therefore no master clock signal Ki is generated in the next cycle, and therefore in the control circuit 1452 maintain the state of the previous cycle. If the chip selection signal CS is "H" in the previous cycle, the control circuit is more precisely located 1452 in an inactive state. At this point the control circuit 1452 kept in the state of the previous cycle even if the chip select signal CS changes to the active level "L" because no master clock signal Ki is applied. Namely, the CDRAM enters the power saving mode (both the DRAM section and the SRAM section).

The chip activation signal is located CS in the previous cycle at the active level "L" and achieves this Clock mask signal CM in the current cycle level "L", does not become a master clock signal Ki applied even if the chip select signal CS # in the next clock cycle is set to an inactive level "H". Therefore, too in this cycle the data output in the previous cycle continues output.

73 FIG. 14 shows a structure for controlling the operation of the input / output circuit 1435 of FIG 70 , As in 73 , is shown, the input / output control circuit has a G buffer 1492 , which takes over the output activation signal G # asynchronously to the clock signal K, for generating an internal output activation signal, and a DQC buffer 1490 , which is dependent on the chip selection signal CS and the internal master clock signal Ki, for taking over the external DQ control signal DQC # for generating the internal DQ control signal DQC. As a DQC buffer 1490 a structure can be used in which, similarly to the output activation signal G #, the DQ control signal DQC # is adopted asynchronously to the master clock signal K for generating the internal DQ control signal.

The input / output circuit 1435 has a Din buffer 1434 whose activation / deactivation depending on an output signal from the DQC buffer 1490 is controlled, and a gate circuit 1494 , the internal DQ control signal DQC, the internal output activation signal G and the chip selection signal CS for activating / deactivating the main amplifier circuit 1438 receives on. When the DQ control signal DQC is "H", the output enable signal G is "L" and the chip selection signal CS reach the "L" level, activates the gate circuit 1494 the main amplifier circuit 1438 , If the chip selection signal CS is "H", the main amplifier circuit 1438 placed in a state of high output impedance. It is put in a high output impedance state even when the DQ control signal DQC is "L".

The Din buffer 1434 is by the internal DQ control signal DQC from the DQC buffer 1490 activated / deactivated. The internal write determination signal? W determines whether or not write data should be generated. More specifically, the Din buffer creates 1434 the internal write data if and only if the DQ control signal DQC is at "H" and the data write determination signal

74 shows a control sequence of the output states by the output activation signal, the DQ control signal and the chip selection signal. As in 74 is shown, in the first cycle of the master clock signal K, the chip selection signal CS # is at "H" and the first cycle is a NOP cycle (no operation). The DRAM control circuit and the SRAM control circuit do not operate and the output is placed in a high impedance state.

In the second cycle of the master clock signal K when the chip select signal CS # is at "L" field, the output enable signal G # is at "L" and the DQ control signal DQC is at "H" becomes one Data reading process carried out (the executed Operation is accomplished by combining the states of the other control signals set; their operation is not here, but later in detail described) and the value Q1 is output.

In the third cycle of the master clock signal K, when the chip selection signal CS # again reaches level "H", the NOP mode is set and the CDRAM does not work. Therefore it is again placed in a high output impedance state.

In the fourth cycle of the master clock signal, if the chip selection signal CS # again reaches the "L" level is in agreement with the address As, which is being created at this point in time, a data read process executed and the read value Q2 is output.

In the fifth cycle of the master clock signal K even if both the chip select signal CS # and the output enable signal G # are both at "L", the input / output circuit does not work, because the DQ control signal DQC is at "L". Therefore, this is Cycle a state of high output impedance.

When the chip select signal in the sixth cycle CS # is set to "L", the DQ control signal DQC becomes "H" is set and the output activation signal G # is in this Cycle raised to "H". The output becomes dependent from rising output enable signal G # to a high state Impedance offset. According to the rise of the output enable signal G # is for a short period of time a stabilized or not stabilized Value issued.

Because the chip selection signal CS # and the DQ control signal DQ can be supplied separately, as described above only the data input / output can be controlled by the DQC control signal DQC, while internal operation is carried out in the CDRAM. A memory expansion and bank switching of the cache DRAM can be easily implemented and the degree of freedom of the bank structure can be increased. This example will now be described.

[Change in memory structure by the DQ control]

75 Fig. 14 shows an example of the structure of a memory system for a CPU as an external processing unit that requires data with a width of 32 bits. As in 75 CDRAMs CDR # 0 to CDR # 7, each of which performs input / output of data based on 4 bits, are connected to a 32-bit data bus 1002. The input / output of the CDRAMs CDR # 0 and CDR # 1 are controlled by the DQ control signal DQC-0. The data input / output of CDRAMs CDR # 2 and CDR # 3 are controlled by the DQ control signal DQC-1. The data input / output of the CDRAMs CDR # 4 and CDR # 5 are controlled by the DQ control signal DQC-2. The data input / output of the CDRAMs CDR # 6 and CDR # 7 is controlled by the DQ control signal DQC-3.

Not only the chip selection signal CS #, but also other control signals are jointly applied to the CDRAMs CDR # 0 to CDR # 7. In 75 the chip selection signal CS # is only shown as a representative. In the storage system that in 75 is shown, the memory is controlled byte by byte. The reason for this is that the data is formed by 8-bit units when a value is 32 bits. Therefore, when the DQ control signals DQC-0 to DQC-3 are activated at the same time, input / output of 32-bit data is carried out, and when a DQ control signal DQC-i is activated, a value of 8 bits can be obtained. Therefore, values with 8 bits, values with 16 bits and values with 32 bits can be easily achieved as output values. In this case, the chip selection signal CS # is commonly applied to all CDRAM CDR # 0 to CDR # 7, and an operation is carried out therein. Therefore, data input / output can be performed at high speed by controlling only the DQ control signals DQC-0 to DQC-3. This structure enables easy change of the memory system structure when the data bus 16 Bits, 32 bits or even 64 bits.

When the width of the data bus is fixed, a bank structure is commonly used to increase the storage capacity. Switching the bank structures can be done easily. in the Bank switching using the DQ control signal will now be described.

With reference to 76 it is assumed that a memory system is formed by using 8 CDRAMs with 4M 4 bits each or with 4 memory levels each with a respective storage capacity of 4 megabits. As in the case of 75 2 CDRAMs form a set and the input / output control is carried out byte by byte.

As in 75 is shown in this case 256 Sets are cached (SRAM), each set having a block of 32 bits * 16 bits because a CDRAM has a * 4-bit structure. This results in a total of 4 (bits) * 8 (CDRAMs) = 32 bits, and 16 bits of memory cells are connected to one row of the SRAM field. As with the structure of the main memory (DRAM field), blocks ( 16 Bits) with a width of 32 bits for one page. The number of pages is 4 KPages because it corresponds to the number of word lines. One page has 64 blocks. It is believed that a memory system with twice the storage capacity, i.e. 32 megabits, is formed by using the memory system having the structure described above.

78 shows an example of the storage system architecture. As in 78 is shown, the CDRAMs CDR # 0 to CDR # 7 are selected by the chip selection signal CS # 0 and the CDRAMs CDR # 8 to CDR # 15 are selected by the chip selection signal CS #. The data input / output of the CDRAMs CDR # 0, CDR # 1, CDR # 8 and CDR # 9 is controlled by the same DQ control signal DQC-0. Similarly, a common DQ control signal DQC is applied to the CDRAMs arranged in the vertical direction of the drawing.

At the in 78 illustrated memory system architecture, the CDRAMs CDR # 0 to CDR # 7 or the CDRAMs CDR # 8 to CDR # 15 are selected and operated. Therefore, of the 16 CDRAMs, that is, CDRAMs CDR # 0 to CDR # 15, always work B. This is half of all CDRAMs that are present in the memory system and therefore the power consumption can be reduced.

As in 79 the block size is not changed, although the number of sets of the cache is increased. As in 79 is shown, the cache CAC # 1 can perform a data transfer with the main memory MEM # 1, and the cache CAC # 2 can only carry out a data transfer with the main memory MEM # 2. The reason for this is that the data transfer can only be carried out between the corresponding cache and the main memory.

80 shows another example of a memory system using the DQ control signal. As in 80 is shown, the storage system 16 CDRAMs CDR # 0 to CDR # 15. In the storage system after 80 two types of DQ control signals DQC, that is, DQO and DQ1, are used. When these two DQ control signals DQCO and DQC1 are both activated, the corresponding CDRAM is put into the active input / output state. For CDRAMs CDR # 0 to CDR # 7, the second DQ control signal DQC1-0 is supplied together. For the CDRAMs CDR # 8 to CDR # 15, a second DQ control signal DQC1-1 is supplied together.

For CDRAMs CDR # 0, CDR # 1, CDR # 8 and CDR # 9, the first DQ control signal DQCO-0 is applied. For the CDRAMs CDR # 2, CDR # 3, CDR # 10 and CDR # 11 become the first DQ control signal DQCO-1 fed. More like that Way becomes for that CDRAMs CDR # 4, CDR # 5, CDR # 12 and CDR # 13 the DQ control signal DQCO-2 created, and for CDRAMs CDR # 6, CDR # 7, CDR # 14, CDR # 15 becomes the DQ control signal DQCO-3 fed.

For the CDRAMs CDR # 0 to CDR # 15, the chip selection signal CS # common fed. More like that Thus, other control clock signals are shared with CDRAMs CDR # 0 up to CDR # 15 (not shown).

In the structure of the storage system that in 80 is shown, the activation / deactivation (selection / non-selection) of the CDRAMs CDR # 0 to CDR # 15 is controlled together by the chip selection signal CS #. The data input / output is controlled by the DQ control signals DQCO and DQCl. When the chip select signal CS is activated, driving of the DRAM field, driving of the SRAM field and internal data transmission are generally carried out in the CDRAMs CDR # 0 to CDR # 15. Therefore, the block size of the cache is twice that of the structure shown in 79 is shown. Half of the area of the doubled cache block is controlled by the second DQ control signal DQCl (DQC1-0 and DQC1-1).

Because only the data input / output is controlled by the DQ control signal, as in the 78 to 81 is shown, a high impedance output state can be realized in bank switching while the CDRAM is operating internally, and the input of data can be inhibited so that erroneous data input / output in bank switching can be prevented.

When bank switching is performed using two types of DQ control signals, as in 80 is shown, only the data input / output is controlled by the DQ control signal, and an internal operation of the CDRAM is carried out. Therefore, data input / output can be performed faster when switching banks.

82 shows a structure for realizing the storage system 80 , As in 82 is shown is a gate circuit 1100 , which receives the first DQ control signal DQCO and a second DQ control signal DQC1. The gate circuit 1100 can follow the next level of the DQC buffer in the structure 73 or in the previous stage of the DQC buffer. When both the first and second DQ control signals DQC0 and DQC1 reach the active state "H", the gate circuit is activated 1100 the DQ control signal and applies it to the gate circuit 1494 , in the 73 and to the Din buffer 1494 on. By using the gate circuit that is in 82 is shown, the buffer can be switched over and the memory enlarged in a simple manner.

[General functional Structure]

83 shows the functional structure of the CDRAM according to the second embodiment. As in 83 is shown, the DRAM field DRA has a memory capacity of 4K rows * 64 columns * 16 blocks * 4 (IO). 64 columns of DRAM bit line pairs are arranged in one block and one column is selected in a block.

The SRAM field SRA has a memory capacity of 256 lines 16 Columns * 4 (IO). One line is selected in the SRAM field, and data transfer can be performed between the one selected line of 16 bits and 16 bits (1 bit of each block) selected in the DRAM field.

The column decoder COLD selects DTBR (16 bits * 4 (IO)) from the read data transfer buffer, and transmits the read data via the IO circuit IOC to the data input / output terminal DQ. The column decoder COLD also transmits the 4 bits of data supplied from the IO circuit IOC to the corresponding 4 bits of the write data transfer buffer DTBW (16 bits * 4 (IO)). The column decoder COLD also writes 4 data bits from the IO circuit IOC in 4 bits to memory cells of the SRAM field SRA when data writing is carried out. As will be described later, the column decoder COLD further has the function of transferring 16 * 4 bits of data stored in the read data transfer buffer DTBR to the write data transfer buffer DTBW (the structure will be described later). The DRAM control circuit 128 (please refer 70 ) controls the data transfer from the DRAM field DRA to the read data transfer buffer DTBR and the data transfer process from the write data transfer buffer DTBW to the DRAM field DRA. An operating mode in which data is transferred simultaneously to the read data transfer buffer DTBR at the time of the data transfer from the write data transfer buffer DTBW to the DRAM field is newly created, as will be described later. This data transfer is also carried out by the DRAM control circuit 128 controlled.

The SRAM control circuit 1432 (please refer 70 ) controls the data reading from the SRAM field SRA to the data input / output port DQ, the data writing from the data input / output port DQ to the SRAM field SRA, the data transfer from the read data transfer buffer DTBR to the SRAM field SRA, the data transfer from the SRAM field SRA to the write data -Transfer buffer DTBW, the data writing from the input / output port DQ to the write data transfer buffer DTBW, the data reading from the read data transfer buffer DTBR to the input / output port DQ, the data writing from the data input / output port DQ to the SRAM field SRA and the write data transfer buffer DTBW as well as the Reading data from the read data transfer buffer DTBR to the data input / output terminal DQ and the data transfer to the SRAM field SRA.

84 shows a more detailed structure of the data transmission area. In 84 those sections are shown that belong to a pair of global IO lines GIO and a pair of SRAM bit lines SBL. The Din buffer 1634 and a main amplifier 1638 perform an input / output of one bit of data.

As in 84 is shown, a path for data transmission to the DRAM field has a write data transmission circuit 1620 with a write data transfer buffer for locking and transferring data to be transferred to the DRAM field, and a masking register for masking this transfer and a selector 1615 to select either the write data from the Din buffer 1634 or the data from the first sense amplifier 1612 , which will be described later, according to the operation mode, to the selected data to the write data transfer circuit 1620 to put on.

The selector 1615 becomes dependent on the signal? BW in the buffer write mode (an operation mode in which external write data is input to the write data transfer circuit 1620 be activated), and depending on the selection signal from the column decoder 1616 transmits the selector 1615 the write data from the Din buffer 1634 to the write data transfer circuit 1620 ,

In the data transfer process from the SRAM field to the write data transfer buffer or in the operating mode for storing data from the read data transfer buffer DTBR, which will be described later, the selector transfers 1615 the data applied to the write data transfer circuit 1620 depending on the signal transmission circuit 1620 locks the created data depending on the signals transmits the created data to the global IO line pair GIO depending on the transmission determination signal

The path for transferring data from the DRAM array has a read data transfer circuit 1610 for locking and outputting the data on the global IO line pair GIO and an SBL driver circuit 1611 which the data from the read data transmission circuit 1610 emp catches to transmit the data to the SRAM bit line pair SBL depending on the signal? BR. The read data transmission circuit 1610 locks the applied data and then transmits it depending on the signal ßt the signal determination signal and the transmission determination signal. The locking operation is carried out under the control of the DRAM control circuit while the transmission determination signal is generated under the control of the SRAM control circuit. In 84 Both signals, that is, the latch designation signal and the transmission designation signal are combined as one control signal

The path to read data has a sector 1613 to select either the data from the read data transmission circuit 1610 or the data on the SRAM bit line pair SBL, a first sense amplifier 1612 to amplify the data from the selector 1613 and a second sense amplifier 1614 for further amplifying the output from the sense amplifier 1612 on. The second sense amplifier 1614 is only activated if a selection signal from the column decoder 1616 is supplied, and he carries out an amplification process. The output of the amplifier is in the unselected state 1614 in a high impedance state. If data from the selector 1613 the first sense amplifier leads 1612 always a reinforcement process.

The selector 1613 selects the data on the SRAM bit line SBL depending on the signal? BWT in the buffer write transfer mode (data transfer from the SRAM field to the write data transfer circuit 1624 ). The selector 1613 selects data from the read data transmission circuit 1610 depending on the signal? DX in the buffer read mode (for reading data contained in the read data transmission circuit 1610 (DTBR) are stored outside the device) and in the second transmission mode (an operating mode for transmitting data in the read data transmission circuit 1610 are stored to the write data transfer circuit 1620 , which will be described later).

In the SRAM read mode for reading data on the SRAM bit line SBL, the selector selects 1613 the data on the SRAM bit line SBL depending on the signal

The write driver circuit 1618 reinforces that of the Din buffer 1634 applied data and transmits it depending on the output signal from the column decoder 1616 into the SRAM bit line pair SBL. The column decoder 1616 is activated when a bit is selected from the column block (a block of 16-bit memory cells that are selected simultaneously) that represents a column block that represents the column block decoder of 70 represents.

As in 84 is shown both the write driver 1618 as well as the second sense amplifier 1614 from the output signal of the column decoder 1616 driven. The write driver circuit 1618 is activated in the operating mode for writing data into the SRAM field, while the second sense amplifier 1614 is activated in data reading mode. The output signal of the column decoder determines whether they are actually activated in the respective operating mode 1616 established. The operation of the CDRAM according to the second embodiment will now be described.

85 shows in a table the states of external control signals for realizing processes which relate to the SRAM control circuit of the CDRAM according to the second embodiment and the processes implemented at this time. The processes implemented are the same as those for the first embodiment. The difference is that external control clock signals CCO # and CC1 # are used in the second embodiment, and the logic of the clock mask signal CMs # is inverted so that the SRAM power save mode and the data suspend state (continuous input / output of the same data) are next Cycle is executed when the mask signal CMs is at "L".

Another difference is there in that the Chip selection signal CS # and the DQ control signal DQC have been added are. If the chip selection signal CS # is at "H", the output becomes placed in a high impedance (Hi-Z) state, and both the The DRAM section and the SRAM section of the CDRAM are shut down.

Is the SRAM clock mask signal CMs # to "L", the SRAM power save mode is set, the transmission the clock signal is locked and the internal state is maintained. Leading to a data suspend condition.

The chip selection signal CS # is present "L" and is the SRAM clock mask signal CMs # on "H", the CDRAM is in a selected state, and the master clock signal is applied to the SRAM control circuit. In the following description, it is assumed that the chip select signal CS # and the clock mask signal CMs # are at "L" and "H", respectively.

When the control clock signals CCO # and CC1 # both are "H", the SRAM lock mode is set, and the Output is placed in a high impedance state. Internally an operation carried out. In this case, the DQ control signal DQC can be in any one Condition.

[Special operating modes]

[SRAM reading mode]

If the control clock signal CC1 # is set to "L", the control clock signal CCO # and the write activation signal WE # are set to "H" the SRAM read mode is set. Data is selected in the SRAM field. At this time, when the DQ control signal DQC is set to "H", data is read out which is read from the SRAM field. 86 shows the data flow in SRAM read mode. As in 86 is shown, a line in the SRAM field is shown in the SRAM read mode 104 selected, the data of the memory cells connected to this row are from the first sense amplifier 1512 amplified and then to the second sense amplifier 1514 transfer. The column decoder 1516 selects one of the 16 bits (if there are 4 IOs) and activates the corresponding second sense amplifier 1514 , The selected 4 bits (if the IO section has a 4-bit structure; the same applies to the following description) are from the second sense amplifier 1514 amplified and to the main amplifier circuit 1438 transfer. When the DQ control signal DQC is "H", the main amplifier circuit becomes 1438 activated, and the read data are transmitted to the input / output connection DQ ( 86 shows a state in which the common DQ arrangement is selected as the data input / output structure; the same applies to the following description).

When the DQ control signal DQC is at the "L" level in this state, the main amplifier circuit operates 1438 not, and the operation is similar to the SRAM lock mode.

[SRAM write mode]

When the control clock signal CCO # is on "H" is set, and the control clock signal CCl # and the write enable signal WE # is set to "L", the SRAM write mode is set. Lies the DQ control signal DQC to "H", which are at this time external data created and internal write data is generated. The generated internal Write data becomes corresponding to the SRAM address bits As0 to As11 fed at this time be selected Memory cells written.

As in 87 is shown, the data supplied to the DQ output terminal in the SRAM write mode is via the Din buffer 1434 applied to the write driver circuit 1518. The write driver circuit 151 writes the created data depending on the column selection signal from the column decoder 1516 into the corresponding memory cell of the SRAM field 104 ,

[Buffer read transfer mode]

If both the control clock signal CCO # as well as the DQ control signal DQC are set to "L", and the control clock signal CC1 # as well the write activation signal WE # are set to "H", the Buffer read transfer mode set. The DQ control signal DQC is set to "L" to output a high impedance state realize and avoid incorrect data output, which are transferred from the read transfer buffer circuit.

For the data holds that the data locked in the read data transfer buffer (DTBR) at the same time transferred to the SRAM field become. In this case, the SRAM address bits As4 to As11 are used as the SRAM row address and a row selection process is carried out.

As in 88 is shown in buffer read transfer mode 16 Bits of data from the read data transfer buffer circuit (DTBR) concurrently with the selected row of the SRAM field 104 transfer. In 85 the indication "used" means that the data locked therein are used. The indication "load / use" means that the data is locked and used.

[Buffer write transfer mode]

The control clock signal CC1 # is on "H" is set, and the control clock signal CCO #, the write enable signal WE # and the DQ control signal DQC set to "L", the Buffer write transfer mode set. In this case, data transferred from the SRAM field to the read data transfer buffer circuit. How later will be described in detail, the write data transfer buffer circuit and the mask register circuit both an intermediate latch and have a two-stage latch circuit structure. In buffer write transfer mode data from the SRAM field in the intermediate latch that is in the write data transfer buffer circuit is formed, saved. In the same way, in the masking register circuit the masking data of the intermediate masking register are all reset. The SRAM address bits As4 to As11 are adopted as the SRAM row address, in the SRAM field a row selection process is carried out and the data of the memory cells of the selected row are transferred to the write data transfer buffer circuit.

As in 89 is shown, in the buffer write transfer mode, the data of the memory cells associated with the selected row of the SRAM field 104 are connected by the first sense amplifier 1512 amplified and then in the write data transfer buffer circuit 1520 stored (more precisely in the intermediate register formed therein).

[Buffer read transfer and Read mode]

When the control clock signal CCO # is set to "L" and the control clock signal CCl #, the write enable signal WE # and the DQ control signal DQC are set to "H", the buffer read transfer and read modes are set. In this case, the data stored in the read data transfer buffer stored, transferred to the SRAM field and data is transferred externally. In this case, all SRAM address bits As0 to Asll are used. How out 85 it can be seen that the buffer read transfer mode coincides with the buffer read transfer and read mode, except that the state of the DQ control signal DQC differs. At this time, not only the input / output circuit, but also the activation / deactivation of the column decoder can be controlled by the DQ control signal DQC.

As in 90 is shown in buffer read transfer and read modes 16 Bits of data from the read data transfer buffer circuit 1510 to the selected line of the SRAM field 104 transmitted, and there is a data bit (more specifically 4 bits because there are 4 IOs) by the column decoder 1516 have been selected via the first and second sense amplifiers 1512 and 1514 transmitted to the data input / output terminal DQ.

[Pufferschreibtransfer- and write mode]

If the control clock signal CCO # and the write activation signal WE # are set to "L" and that Control clock signal CC1 # and the DQ control signal DQC set to "H" the buffer write transfer and write mode is set. In In this mode, externally created write data is converted into a corresponding Memory cell of the SRAM field written and the data written are also written into the corresponding register, which is in the Write data transfer buffer circuit is formed. Also in this Fall in the write data transfer buffer circuit the data of a row to which the memory cells are connected, transferred to the intermediate register. At this time, the masking data of the masking register all reset.

As in 91 is shown, more specifically, the data applied to the data input terminal DQ becomes the Din buffer 1434 fed, the write driver circuit 1518 becomes in accordance with a column selection signal from the column decoder 1516 activates and writes the data to a corresponding memory cell in the SRAM field.

The data of a row of memory cells of the selected row, which contains the memory cell which has been subjected to data writing, are transferred via the first sense amplifier 1512 for write data transfer buffer circuit 1520 transfer. 91 shows the write data as it goes through the write driver circuit 1518 have been written to the corresponding memory cell of the SRAM array, and then the data of a row of memory cells is passed through the first sense amplifier 1512 for write data transfer buffer circuit 1520 transfer. Parallel to data writing in the memory cell of the SRAM field 104 through the write driver circuit 1518 However, the data of the memory cell of the selected row in the SRAM field 104 via the first sense amplifier 1520 for write data transfer buffer circuit 1520 are transferred, and in this write data transfer buffer circuit 1520 can write data to the corresponding register at the same time as the write driver circuit 1518 be carried out.

With this structure is the column decoder 1516 represented so that it is only the write driver circuit 1518 and the second sense amplifier 1514 drives. The column decoder 1516 however, has a function for selecting registers in the latch data transfer buffer circuit 1520 are formed.

In buffer write transfer and write mode the buffer write transfer operation is carried out only when the DQ control signal DQC is set to "L".

[Buffer read mode]

When the control clock signals CCO # and CC1 # both at "L" and the control activation signal WE # and the DQ control signal DQC are set to "H", the buffer read mode is set. In buffer read mode become data in the read data transfer buffer circuit corresponding to the SRAM address bits (Block address) As0 to As3 selected, and the selected data are issued. In this case, when the DQ control signal DQC is on "L" is set, data reading is not performed and the SRAM lock mode is set.

In the buffer read mode, data from the read data transfer buffer circuit 1510 from the first sense amplifier 1512 amplified, and then a corresponding second sense amplifier is only corresponding to the column selection signal from the column decoder 1516 activated, the output signal of the activated second sense amplifier becomes the main amplifier circuit 1438 is transmitted, and then read data from the main amplifier circuit 1438 transmitted to the data input / output terminal DQ as in 92 is shown.

[Buffer write mode]

When the control clock signals CCO # and CCl # and the write activation signal WE # set to "L" are, and the DQ control signal DQC is set to "H", the Buffer write mode set. In this case, the corresponding Register of the write data transfer buffer circuit according to the Blockadreßbits As0 to As3 selected, and an external value is written to the selected register. In this case, the write data transfer buffer circuit only those masking data reset that the register correspond, which is subject to data writing.

As in 93 is shown is more precise said in the buffer write mode by a column selection signal from the column decoder 1516 (whose path is not shown) a corresponding register in the write data transfer buffer circuit 1520 selected, and a write value from the Din buffer 1434 is written to the selected register.

In the table of 85 the control signals belonging to the operation of the DRAM field and the state of the DRAM address are not shown. The SRAM field and the DRAM field are driven independently of one another. Therefore, the table below 85 the states of the control signals, which relate to the operation of the DRAM, and the state of the SRAM addresses are given arbitrarily.

94 shows in a table the operating modes of the DRAM field, the states of the control signals and the states of the data transfer buffer at this time. As in 94 shown, the operation of the DRAM array section does not affect the operation of the SRAM section and data input / output. Therefore, the states of the control signals CCO #, CCl #, WE # and DQC belonging to the SRAM can be in any state. The states of these control signals are therefore not shown.

[DRAM power saving mode]

Is the DRAM clock mask signal CMd # in the previous cycle at "L", the DRAM field enters DRAM power save mode one, and keeps the state that was set in the previous cycle. The chip selection signal CS # is used to do this, the SRAM section and the DRAM section to prevent it from entering a new operating state.

In the first embodiment, the chip activation signal E # is only supplied to the SRAM control section and is not used in the DRAM section. In the second embodiment, the chip select signal CS # is also applied to the DRAM control section. When the chip select signal CS # is set to the inactive state "H", the DRAM enters the NOP mode (no operation) in which no operation is carried out. Therefore at in 71 Structure shown the internal chip selection signal CS, the input ENA of the control circuit 1452 is supplied to the control circuit 1452 back, and it is used to control the active / inactive state.

A structure can be used in which the chip select signal CS # is the K buffer 1424 (please refer 74 ) is supplied, and if the chip selection signal CS # is at "H", the master clock signal K cannot be sent to the DRAM control circuit 128 and the SRAM control circuit 1432 be created. If the chip selection signal CS is "H", the acceptance of a new control signal is blocked in the control circuit.

[DRAM-NOP Mode]

The chip selection signal CS # is present "L" (in the following description, it is assumed that this conditions met is) and is the clock mask signal CMd # in the previous cycle au "H" (this condition also applies to the following description) and are both the row address strobe RAS # as well as the column address strobe CAS # to "H", the NOP mode of the DRAM (DNOP mode) is set. In this case, the state of the previous cycle is shown in the DRAM field maintained and no new operation is performed. This Mode is used to prevent the DRAM section from one take up new operating mode. Is a specific one in the previous cycle Operating mode has been set and the DRAM-NOP mode is set, in this state, the one defined in the previous cycle is internal Operation carried out.

[DRAM read transfer mode]

When the row address strobe signal RAS # and the data transfer designation signal DTB # are both set to "H" and the column address strobe signal CAS # is set to "L", the DRAM read transfer mode is set. In the DRAM read transfer mode, the address bits Ad4 to Ad9 in the DRAM field are used as the column block address, and it becomes a memory cell block (column block) from the block decoder 112 selected the in 70 is shown. The data of the selected column block (memory cell block) is transferred to the read data transfer buffer circuit.

As in 95 the selected column block (a memory cell block or a data block) is shown in the DRAM field 102 is selected and the selected column block becomes the read data transfer buffer circuit 1510 transferred and locked there.

[DRAM-active mode]

When the row address strobe signal RAS # is set to "L" and both the column address strobe signal CAS # and the data transfer designation signal DTD # are set to "H", the DRAM active mode is set. In this mode, the address bits Ad0 to Ad11 created at this time are adopted as the DRAM row address, and a row selection process is carried out in the DRAM field according to the row address. The DRAM active mode maintains the row selection state until the DRAM precharge mode is set, which will be described below. By using the DRAM active mode, the sense amplifier of the DRAM can be put into the data lock state by implementing data transmission using the page mode (as in the first embodiment insurance form).

[DRAM precharge]

When the row address strobe signal RAS # and the data transfer determination signal DTD # both are set to "L" and the column address strobe CAS # is set to "H", the DRAM precharge mode is set. In this mode, a word line selected in the DRAM field becomes the unselected state changed and the DRAM returns to the initial state (standby state). If another line is to be selected in the DRAM field, it is necessary to between the DRAM active mode and the following DRAM active mode Execute DRAM precharge mode.

[Self-refresh mode]

When the address strobe signals RAS # and CAS # are both set to "L" and the data transfer designation signal DTD # is set to "H", the self-refresh mode is set in the DRAM section. In this mode, an address counter (in 70 (not explicitly shown) formed in the DRAM generates a refresh address, and the memory cell data is refreshed according to the refresh address. As with the first embodiment, execution of the DRAM precharge mode is necessary to complete the self-refresh mode. The DRAM address created at this time can be used as a refresh address.

[Data transfer process from the Write data transfer buffer circuit to the DRAM field]

There are four different types of data transfers from the write data transfer buffer circuit to the DRAM array. The data transfer from the write data transfer buffer circuit to the DRAM array is determined by setting the row address strobe signal RAS # to "H" and by setting the column address strobe signal CAS # and its data transfer designation signal DTD # to "L". In this state, the address bits Ad4 to Ad9 supplied at this time are sent to the block decoder 112 (please refer 70 ) is created, and data is transferred with respect to the column block (memory cell block or data block) selected in the DRAM field. There are four different data transfer modes. These four data transfer modes are described below.

96 shows the states of the control signals in DRAM write transfer mode (which summarizes the four data transfer modes). In the first cycle of the master clock signal K, the row address scanning signal RAS # is set to "L" with the rising edge and the DRAM active mode is defined. The address bits Ad0 to Ad11 supplied at this time are adopted as the DRAM row address, and a row selection process is carried out in the DRAM field. After a predetermined latency (number of clock cycles necessary to allow the column address strobe signal CAS # to drop) has elapsed, in the fourth cycle of the master clock signal K, the column address strobe signal CAS # and the data transfer determination signal DTD # are both set to "L". As a result, the DRAM write transfer mode (DWT mode) is set. In the write transfer mode, an operation for selecting a column block (a block of memory cells or a data block) is performed in the DRAM field. Ad4 to Ad11 are used as addresses. The remaining low-order address bits Ad0 to Ad3 are used as commands for specifying the type of write transfer mode.

In the table of 94 a state is shown in which only the low address bits Ad0 to Ad1 are used. The remaining address bits Ad2 and Ad3 are reserved for future expansion. In a structure in which a command value for setting the DRAM write transfer mode is applied concurrently with the DRRM column block address when the column address strobe signal CAS # falls, it is unnecessary to form a separate terminal for data transfer setting. This can reduce the chip area.

The external control devices can also Easily generate data for write transfer mode setting are necessary so that the Control of the overall system is simplified. That will be before the detailed Description of the write transfer mode explained.

Fig. 97 shows an example of a data processing system using a CDRAM. As in Fig. 97 is shown, the data processing system has a CPU 2002 as an external processing unit to carry out the necessary data processing, a CDRAM 2000 , which acts as main memory and cache memory, a cache controller 2004 , the operating mode and other things of the CDRAM 2000 specifies an SRAM address latch 2006 that the SRAM address AO to A11 from the CPU 2002 locked, a row latch 2008 that the address A10 to A21 from the CPU 2002 locked as DRAM row address, a column latch 2010 for locking the addresses A4 to A9 from the CPU 2002 as a DRAM column block address and a multiplexer 2014 for multiplexing the addresses from the line latch 2008 and column latch 2010 to the result to the CDRAM 2000 to put on. The multiplexer 2014 sets the address of the column latch 2010 and the command data from the command latch 2012 to the CDRAM at the same time.

The cache controller 2004 assigns one Circuit section for detecting a cache miss / cache hit in accordance with the cache address A0 to A11 from the CPU 2002 for generating a control signal in accordance with the determination result. The SRAM address bits As0 to As11 of the CDRAM 2000 are from the latch 2006 generated. The DRAM address bits Ad0 to Ad11 of the CDRAM 2000 are from the multiplexer 2014 generated.

At the in 97 Address structure shown are those of the CPU 2002 created address bits A12 to A21 used as the tag address of the cache. The CPU address bits A10 and A11 are used as the way address. The CPU address bits A4 to A9 are used as the set address. The CPU address bits A0 to A3 are used as block addresses. The CPU address bits A22 to A31 (in the event that the address 32 includes) are used as the chip selection address. In the 97 namely the address arrangement shown shows a structure in which a 4-way set associative mapping between the multiple and main memory is implemented.

The cache controller 2004 decodes a chip selection address, not shown, and generates a chip selection signal (or a chip activation signal (in the case of the first embodiment)).

At the in 97 structure shown can be the multiplexer 2014 generate the DRAM column address and the command data for the write data transfer mode at the same time. Therefore, the type of write transfer mode can be set without affecting the working speed. Furthermore, this control method is used in a simple manner as a method for generating the command data for identifying the type of write transfer mode.

Now the operation of each Write transfer modes described.

[DRAM write transfer mode]

This mode is determined by Setting the address bits Ad0 and Ad1 set to "0" simultaneously with the DRAM column address supplied become. In this mode, data is transferred from the intermediate register to the Write data transfer buffer DTBW loaded, and the loaded data are transferred to the DRAM field. Synchronous to the data transfer from the intermediate register of the write data transfer buffer circuit to Data transfer buffers DTBW become masking data of the intermediate register Masking registers are transmitted in the transmission masking circuit and this data transfer is masked. In this mode, the masking data of the intermediate register after the completion of the data transfer.

Here are the intermediate register 142 the write data transfer buffer circuit and the write data transfer buffer DTBW in 70 by the reference numerals 142 or 144 shown. The intermediate register is not shown for the masking register circuit. The detailed structure will be described later. The structure is simplified in this description for easier understanding of the data transmission process.

As in 98 is shown, data from the write data transfer buffer (DTBW) 1520 to the DRAM field 102 transfer. In the DRAM field 102 a column block (a memory cell block or a data block) has been selected and the data is written all at once into the selected column block.

[DRAM write transfer read mode]

This mode is set by setting the address bits Ad0 and Ad1 to "1" and "0", respectively. In this mode, data from the write transfer buffer circuit (DTBW) is transferred both to the selected column block of the DRAM array and to the read data transfer buffer circuit. The data from the column block containing the memory cell that has been subjected to data writing is transferred to the read data transfer buffer circuit (DTBR). Thus, in a cache miss write from this read data transfer buffer circuit, reading data can be performed if the same block is set in the next cycle and because the data is from the read data transfer buffer circuit (DTBR) to the SRAM array 104 can be written, the content of the SRAM field 104 that were unsuccessfully accessed are rewritten. Therefore, the cache miss delay can be reduced and a CDRAM that operates at high speed can be formed.

As in 99 is shown, more specifically, in the DRAM write transfer mode / read mode, data from the write data transfer buffer circuit (DTBW) 1520 to the selected column block of the DRAM field 102 transferred (a masking operation corresponding to the masking data in the masking register is carried out) and the data of this selected column block of the DRAM field 102 become the read data transfer buffer circuit (DTBR) 1510 transfer.

[DRAM write transfer mode 2]

This mode is determined by Setting the column block address bits Ad0 and Ad1 to "0" and "1", respectively. In this operating mode there is a data transmission from the write data transfer buffer circuit (DTBW) to the selected one Column block of the DRAM field executed. In this case, the Write transfer buffer circuit no data transfer from the intermediate register to the write data transfer buffer (DTBW). The same applies to the masking register.

The write data transfer buffer circuit removes the intermediate register from the buffer register cut separated, which transfers the data to the DRAM field. When the DRAM write transfer mode 2 is executed repeatedly, the same data is transferred to the DRAM field. If the column block in the DRAM field is selected in page mode, the data in the DRAM field can be overwritten by the same value at high speed. Therefore, so-called "fill" (coloring in one color) can be implemented at high speed in a graphics application. The data transfer process is essentially the same as that in 98 is shown. The only difference is whether the same value is transferred or not.

[DRAM write transfer mode 2 / read mode]

This mode is determined by setting the address bits Ad0 and Ad1 to "1". In this operating mode, in addition to the DRAM write transfer mode 2 an operation for transferring data of the selected column block of the DRAM field to the read data transfer buffer circuit (DTBR) is performed. In this operating mode, too, "filling" can be carried out at high speed. Accordingly, a CDRAM can be obtained which is very effective for graphics applications.

[General data transfer process]

Fig. 100 shows a signal diagram of a data transfer sequence from the DRAM field to the read data transfer buffer circuit. Data transfer from the DRAM array to the read data transfer buffer circuit is described with reference to FIG Fig. 100 described.

In the first cycle of the master clock signal K when the row address strobe signal RAS # is set to "L", and the column address strobe signal CAS # and the data transfer designation signal DTD # are set to "H", the DRAM active mode ACT is set. In the DRAM section, the address bits Ad0 through Ad11 is used as the row address, and it becomes a row selection process carried out.

In the cycle after the RAS-CAS delay tRCD has elapsed, this means, in the fourth cycle of the master clock signal K when the column address strobe signal CAS # is set to "L" and the row address strobe RAS # and the data transfer designation signal DTD # are set to "H", the DRAM read transfer mode (DRT) is set. A column block (a memory cell block or a data block) of the selected one Row using the column block address (C1) Address selected, and the data of the selected one Column blocks are transferred to the read data transfer buffer circuit. A latency of three clock signal cycles is assumed here.

The latency means the number of Clock signals that are necessary for the new data from the read data transfer buffer circuit transmitted to the SRAM field and / or the data input / output terminal DQ as already in connection with the first embodiment has been described. This latency can be used as the access time of the read data transfer buffer circuit be considered. is the latency n clock cycles, the (n - 1) th cycle is in the "DTBR lock state" added. More precisely, the data transmission is carried out by the. Read data transfer buffer circuit locked (in this cycle, the process of accessing the Read data transfer buffer circuit blocked).

In the seventh cycle of the master clock signal K the data of the read data transfer buffer circuit is stabilized, and in this cycle, the DRAM read transfer mode is again in the DRAM section established. On the line that is in the first cycle of the master clock signal K has been determined, another column block is corresponding the column block address (C2) is selected, and after the elapse The CAS latency is the data of the newly selected column block (a memory cell block or data block) to the read data transfer buffer circuit.

In the SRAM section, the seventh Cycle of the master clock signal K the control clock signals CCO # and CC1 # are both set to "L", and the write enable signal WE # is set to "H". The DQ control signal DQC is at "H" and the data input / output is activated. In this state, the buffer read mode is set, and the column decoder leads the selection process in accordance with the address bits As0 to As3, which are created at this time, and it reads the corresponding data from the values in the read data transfer buffer circuit are saved. More specifically, in the eighth cycle of the master clock signal K read the data B1. By executing the DRAM read transfer mode and by executing the buffer read mode (BR) in one cycle after the elapse of the Latency can namely Read data after the elapse of the time tCAC from the definition the buffer read transfer mode can be obtained.

In the tenth cycle of the master clock signal K becomes the data selected by the column block address (C2) the read data transfer buffer circuit saved. In this cycle, the buffer read mode (BR) is again executed and in each clock cycle, those in the read data transfer buffer circuit stored data read one after the other (B2, B3, B4 and B5).

In parallel with the buffer read mode operation, the DRAM read transfer mode is set again in the twelfth cycle of the master clock signal, and after three clock signal cycles have elapsed, the data is the read data transfer buffer circuit stabilized. In the SRAM field section, access to the read data transfer buffer circuit is blocked in this fourteenth cycle, and therefore the SRAM address currently applied is ignored (because this represents the DTBR blocking time).

In the fifteenth cycle of the master clock signal K, the buffer read mode is set again, and that in the read data transfer buffer circuit (B6) saved data is read.

In the fifteenth cycle of the master clock signal K become the row address strobe signal RAS # and the data transfer determination signal DTD # is set to "L" and the column address strobe signal CAS # becomes "H" set. This sets the DRAM preload mode (PCG). Therefore, the row that has been selected in the DRAM field becomes the unselected state added.

As described above can by the combined use of the DRAM read transfer mode and the buffer read mode the data of the DRAM field the read data transfer buffer circuit read without affecting the SRAM field. Because of this Operation can be performed by using the DRAM's page mode (The DRAM active mode continues until a DRAM precharge mode accomplished will) the data is read at high speed.

Fig. 101 shows a signal diagram of the data transfer sequence from the write data transfer buffer circuit to the DRAM array. With reference to Fig. 101 describes the DRAM write transfer mode for transferring data from the write data transfer buffer circuit to the DRAM array.

In the first cycle of the master clock signal K becomes the row address strobe signal RAS # is set to "L", and the column address strobe signal CAS # and the data transfer designation signal DTD # are both set to "H" so DRAM active mode (ACT) is set. A row selection process is carried out in the DRAM field.

In the SRAM section, the first through the fourth cycle of the master clock signal K does a buffer write (BW), and in the second through fourth cycles of the master clock signal K, the data B1 to B4 become sequential stored in the intermediate register in the write data transfer buffer circuit is formed. The buffer write mode (DBW) is defined by Setting the clock signals CCO # and CCl # as well as the write activation signal WE # at "L" and by setting the DQ control signal DQC to "H".

In the fourth cycle of the master clock signal K is set to "H" by setting the row address strobe signal RAS # and by adjusting the column address strobe signal CAS # and of the data transfer designation signal DTD # set to "L" of DRAM write transfer mode (DWT1). If the DRAM write transfer mode is set, those in the intermediate register stored data (B1 to B4) transferred to the write data transfer buffer (DTBW). The data transferred to the write transfer buffer (DTBW) are stored in the Column block (a memory cell block or data block) after the Lapse of latency (three clock cycles) stored in the DRAM field selected is.

When the latency has passed, that is, in the seventh cycle of the master clock signal K, the column address strobe signal CAS # and the data transfer determination signal DTD # are reset to "L" and the row address strobe signal RAS # to "H". In this mode, by setting the SRAM address bits As0 to As3, which are set at that time, as the command data, the DRAM write transfer mode 2 (DWT2) set. When the DRAM write transfer mode 2 is set, the intermediate register is separated from the write data transfer buffer (DTBW) and no data transfer from the intermediate register to the write data transfer buffer (DTBW) is carried out. The data stored in the write data transfer buffer (DTBW) is transferred to the selected column block of the DRAM field after the latency has elapsed.

As in Fig. 101 is shown, in the DRAM write transfer mode, the mode setting is carried out in accordance with the DRAM address bits Ad0 to Ad3 at the time of the DRAM write transfer mode setting. Therefore, the DRAM write transfer mode can be set without affecting the operation in the SRAM section.

In the tenth cycle of the master clock signal K the buffer write mode (BW) is set again, and in the tenth to twelfth Cycle of the master clock signal K, data B5, B7 in the write data register (Intermediate register) saved.

In the twelfth cycle of the master clock signal DRAM write transfer mode again set, and the data stored in the intermediate register B5 to B7 are transferred to the write data transfer buffer. After a predetermined latency has elapsed, the new data B5 to B7 in the selected one Column block of the DRAM saved. In the thirteenth cycle of the master clock signal K, the buffer write mode (BW) has been set in the SRAM section. However, in this cycle, data stored in the intermediate register are transferred to the write data transfer buffer, access to the intermediate register is blocked. Hence the Buffer write mode set in the thirteenth cycle of the master clock signal K. not executed.

In the fifteenth cycle of the master clock signal K becomes the DRAM precharge mode (PCC) is set, and the DRAM array returns to the precharge state.

More specifically, in the DRAM write transfer mode, the data transfer of the DRAM field which are executed in the manner of a pipeline or independently of the operation of the SRAM section, because an intermediate register and a write data transfer buffer are formed. In write transfer mode, the intermediate register is connected to the write data transfer buffer in the first cycle. The intermediate register and the write data transfer buffer are separated from each other at the beginning of the next cycle. At the time of this separation, the masking data in the masking register circuits corresponding to the intermediate registers are all set.

After the separation of the intermediate register and the write data transfer buffer can Data from the SRAM field or from outside be written into the intermediate register.

In DRAM write transfer mode 2 the intermediate register and the write data transfer buffer are kept separate. Therefore, no data transfer from the intermediate register to the write data transfer buffer is carried out and the data stored in the write data transfer buffer in the previous cycle are transferred to the selected column of the DRAM field.

In DRAM write transfer mode additionally for data transmission a transmission mode to the DRAM field for read data transfer buffer circuit educated. This is useful, when used as a cache.

[Write Transfer Control System]

Fig. 102 Figure 10 shows a structure for controlling the DRAM write transfer process. As in Fig. 102 the write transfer control system includes a write transfer detection circuit 2110 dependent on an internal DRAM master clock signal DK, an internal row address strobe signal RAS, an internal column address strobe signal CAS and an internal data transfer designation signal DTD for detecting the determination of the DRAM write transfer mode, a command register 2112 which stores the two least significant bits Ad0 and Ad1 of the DRAM column address currently applied when the DRAM write transfer mode is set in accordance with the signals DK, RAS, CAS and DTD, and a read transfer detection circuit 2114 , which is dependent on the signals DK, RAS, CAS and DTD, for detecting the determination of the data transfer from the DRAM field to the read data transfer buffer circuit 2106 on. The write transfer detection circuit 2110 , the command register 2112 and the read transfer determination circuit 2114 are in the DRAM control circuit 128 included that in 70 is shown. The command register 2110 is shown so that it only receives the low-order address bits Ad0 and Ad1. Address bits Ad0 to Ad3 can also be used (to expand the functionality).

When the DRAM write transfer mode is set, the read transfer detection circuit generates 2110 a signal? BW for defining the data transfer from the write data transfer buffer (DTBW) 2100 to the DRAM field (what the global IO line pair GIO in Fig. 102 indicates) and a transfer signal? TBE for performing the data transfer from the intermediate register 2104 to the write data transfer buffer (DTBW) 2100 when the DRAM write transfer mode is set.

The control system also has a gate circuit 2116 that the signal 2110 and the address bit Ad1 from the instruction register 2112 receives and generates a transfer designation signal when the DRAM write transfer mode is set (by performing data transfer from the latch to the write data transfer buffer), a gate circuit 2118 which the address bit Ad0 from the command register 2112 and the signal is output to generate the mode detection signal when the write transfer mode with the data transfer to the read data transfer buffer (DTBR) 2106 is set, a gate circuit 2120 from the read transfer mode determination signal? DRM from the read transfer detection circuit 2114 and the output signal from the gate circuit 2118 is dependent on generating a signal for specifying the data transfer from the DRAM field to the read data transfer buffer, and a read transfer driver circuit 2112 by the output signal from the gate circuit 2120 for generating a driver signal? DR for driving the data transfer to the read data transfer buffer (DTBR) 206 on. If the output signal of the gate circuit 2118 or read transfer mode detection signal? DRM is activated, the read transfer driver circuit generates 2112 the signal? DR for driving the data transfer to the read data transfer buffer (DTBR) 2106 ,

Between the write data transfer buffer (DTBW) 2100 and the intermediate register 2104 is a transmission gate 2102 educated. The transmission gate 2102 transfers depending on the output signal of the gate circuit 2116 the output signal from the intermediate register 2104 to the write data transfer buffer (DTBW) 2100 ,

By using the structure described above the type of DRAM write transfer mode can be detected, and the data transfer process can exactly match with the captured Operating mode carried out become.

It will now operate the DRAM write transfer mode 2 (with a mode in which a data transmission to the read data transfer buffer circuit).

[DRAM write transfer mode 2]

As in Fig. 103 is shown, it is assumed that data corresponding to the buffer write mode (BW) is written into the write data transfer buffer circuit, then the write transfer modusl (DWT1) is executed, and then the DRAM write transfer mode 2 (DWT2) is repeated several times. The type of DRAM write transfer mode is determined by specifying the value of the two least significant bits A0 and A1 (corresponding to Ad0 and Ad1) of the DRAM address Ad in the respective mode.

Fig. 104A shows the data flow in DWT1 mode. As in Fig. 104A 16 bits of data D1 to D16, which are stored in the intermediate register, are transferred to the write data transfer buffer circuit (DTBW) in the DRAM write transfer mode 1. At the same time, the masking data of the intermediate masking register are stored in the masking register because the masking register has a similar hierarchical structure to the intermediate register. The data D1 through D16 stored in the write data transfer buffer circuit (DTBW) are masked in accordance with the masking data M1 through M16 stored in the masking register and transferred to the column block (hatched area A) selected in the DRAM field , The masking data of the intermediate masking register are all set after the transfer of the masking data to the masking register to reset the corresponding masking data when data is subsequently written to the intermediate register in the buffer write mode (BW).

Fig. 104B shows the data flow in DRAM write transfer mode 2 , In DRAM write transfer mode 2 no data transfer from the intermediate register to the write data transfer buffer circuit (DTBW) is carried out, as in Fig. 104B is shown. Therefore, the data stored in the write data transfer buffer circuit (DTBW) is the data that was transferred from the intermediate register in the previous cycle. The masking data is also not transmitted in the masking register from the intermediate masking register. Therefore, the same data as in the previous cycle is transferred to another column block of the selected row in the DRAM field. The same data is written column-by-column in the DRAM field.

By repeating the in Fig. 104B illustrated operation, a predetermined area B of the screen CRT of the display unit can be changed by the same data as in Fig. 105 is shown. This enables the so-called "filling process" to be carried out at high speed in a graphics application. The structure of the masking register will be described later in detail.

In DRAM write transfer mode the data transmission to the DRAM field the masking data of the masking register are masked. If the data of the DRAM field is overwritten by external write data Therefore, it is not necessary to execute the read-write mode (read-modify-write mode), and therefore, the content of the DRAM field can run at high speed changed become.

Once manufactured, the CDRAM is tested as a single chip or part of a circuit to determine if it is working properly. More specifically, as in Fig. 106 shown a test pattern with different patterns from a tester 2510 to the CDRAM 2500 created. It is necessary to determine whether the CDRAM 2500 works normally by looking at the operating states of the CDRAM 2500 determined in accordance with the test pattern. In this case, the test of the CDRAM should preferably be carried out simply in view of the test reliability and the time required for the test. A structure for simplifying the test is described below.

[Command register setting mode]

The command register setting mode (SCR cycle) is set by setting the row address strobe signal RAS #, column address strobe signal CAS # and of the data transfer determination signal DTD # with the rising edge of the master clock signal K set to "L". At this point, the DRAM address is used as the command value. The command data is stored in the command register, and the Setting the latency and the output modes (transparent, register and latch) and the CDRAM connection arrangement (IO structure) executed. Preferably, the tester's command data should be simple Way can be generated.

Fig. 108 shows a structure for the command register in the command register setting cycle. Under the DRAM address Ad, the low-order nine bits Ad0 to Ad8 are regarded as the content of the command and stored in the command register. The address bit Ad9 is used as a bit which indicates the activation / deactivation of the data transfer to the read data transfer buffer circuit in the DRAM write transfer mode.

The address bit Ad10 is used to indicate whether the DRAM write transfer mode a DWT1 mode or DWT2 mode. The address bit Ad11 becomes to set / reset test mode. Once the test mode has been set, DRAM write transfer mode the command data Ad0 to Ad3 set, this command data but ignored at this point.

With this structure, the tester can only generate the command data by using the DRAM address bits Ad0 to Ad11. It is not necessary to simultaneously create the DRAM column block address and the command data indicating the type of the DRAM write transfer mode. Therefore, the tester structure can be simplified, the setting of the command data can be performed easily, and the test can be performed with high reliability be carried out.

Fig. 109 shows the correspondence between the command data and the DRAM write transfer mode in the test mode. As in Fig. 109 is shown, the test mode is set when the address bit Ad11 is pale "1"("H") in the command register setting mode. The test mode is reset when it is "0". When the test mode is set and the address bits Ad10 and Ad9 are both "0", the DWT1 mode is set. When the address bits Ad10 and Ad9 are "0" and "1", respectively, the DWT1R mode is set. If the address bits Ad10 and Ad9 are "1" and "0", respectively, the DWT2 mode is set. If the address bits Ad10 and Ad9 are both "1", the DWT2R mode is set.

In test mode, the test mode state is maintained until the self-refresh mode is executed or accordingly a test mode reset is performed in the command register setting mode. In the test mode state, the DRAM field is self-refreshed executed. Alternatively, only the setting of the command register in the Command register setting cycle can be performed.

Fig. 110 Fig. 14 shows an example of the circuit structure for determining the DRAM write transfer mode in accordance with the setting / resetting of the test mode. As in Fig. 110 the test mode control system includes an SCR mode detector 2600 receiving the internal control signals RAS, CAS, DTD and the DRAM master clock signal DK for determining whether or not the command register setting mode (SCR) is set, a command register 2602 from the detection of the SCR mode by the SCR mode detection circuit 2600 is dependent on locking the DRAM address Ad0 to Ad11 as a command value, and a test mode detection circuit 2604 which the data corresponding to the address Ad11 from the command register 2602 receives to determine whether the test mode has been set or not.

The SCR mode detection circuit 2600 determines that the SCR mode is set when the signals RAS, CAS and DTD with the rising edge of the master clock signal DK all have the level "L". Depending on the SCR mode detection by the SCR mode detection circuit 2600 locks the command register 2602 the DRAM address bits Ad0 to Ad11 that are being supplied at this time. In Fig. 110 is the command register 2602 shown as a simple latch circuit. The DWT mode detection circuit 2110 and the command register 2112 agree with those in Fig. 101 and are the circuit for detecting the type of DRAM write transfer mode. The command register 2112 locks depending on the detection of the DWT mode by the DWT mode detection circuit 2110 the command value indicating the type of DRAM write transfer mode.

The test mode control system also includes a selection gate circuit 2606 by the output signal from the test mode detection circuit 2604 is dependent on passing either address bits Ad9 and Ad10 from the command register 2602 or the address bits Ad0 and Ad1 from the command register 2112 on (Here the internal signals, which have the same reference numerals as addresses, represent the command data). When the test mode detection circuit 2604 the test mode are detected in the selection gate circuit 2606 the transmission gates 2611 and 2613 switched through and the transmission gates 2615 and 2617 blocked. Therefore, the gate circuits 2116 and 2118 , in the Fig. 102 are shown, the address bits Ad10 and Ad9 transmit. When the test mode is reset, the output of the test mode detection circuit reaches 2604 the level "L", the transmission gates 2611 and 2613 are blocked and the transmission gates 2615 and 2617 switch through.

When the test mode operation is set by the SCR mode, the test mode is maintained until the self-refresh mode (ARF mode) is set, or the test mode reset (setting the Ad11 bit to "0") is carried out by using the SCR mode again. In test mode operation, the output signal of the test mode detection circuit is therefore 2604 held high, the command value from the command data register 2112 is ignored when the DRAM write transfer mode is set, and the address bits Ad10 and Ad9 set when the SCR mode is set are transferred as the DRAM write transfer mode type identification bits.

At the in Fig. 110 structure shown, external address bits Ad0 to Ad11 are the command registers 2602 and 2112 fed. Because self-refresh is performed in the DRAM field when the SCR mode is set, the refresh address may be generated as an internal address and the above signals are supplied to prevent this condition. Because the external addresses are adopted as command data, the command data can be set in the command register without affecting the operation of the DRAM when the DRAM field is active (by executing the DRAM active mode).

[Cache operation]

Fig. 111 shows an example of the cache system structure. As in Fig. 111 is shown, the cache system has a CPU 3000 as an external processing unit, a CDRAM 3200 , which serves as the main memory and the cache memory, and a cache control circuit 3100 to control access to the CDRAM 3200 on. The CDRAM 3200 has an SRAM section 3210 and a DRAM section 3230 , which are driven independently of one another, as well as a bidirectional data transmission circuit (DTB) 3220 for performing data transfer between the SRAM section 3210 and the DRAM section 3230 and a data output to the outside.

The cache control circuit 3110 has a decoder 3102 for decoding a set address by the CPU 3000 is created to generate a signal for selecting a corresponding set, a tag memory 3106 a write indicator bit memory for storing a tag address for the respective set 3104 to save whether the content of the SRAM section 3120 and the DRAM section 3230 a controller in accordance with the tag address in the tag memory 3108 which the chip selection address and the tag address from the CPU 3000 receives to read the tag address of the set from the decoder 3102 is set in the tag memory 3106 to determine whether the tag addresses match or not and to determine whether the chip select address is the CDRAM 3200 and for generating a control signal in accordance with the determination result, and a (write-back) selector 3100 to save the tag address from the CPU 3000 in the corresponding set of the tag memory 3106 in the event of a cache miss (if the tag address does not match) and to create the internal address from the tag memory 3106 is read to the CDRAM 3200 on.

In the CDRAM 3200 enables a line in the SRAM section 3210 data transfer with any column block of the DRAM section 3230 , Therefore, a desired mapping type (direct mapping, set associative and fully associative mapping) can be carried out.

As in Fig. 111 the multiplexer circuit is multiplexed 3300 the row address and the column address when the DRAM section is accessed 3230 and selects one of the addresses from the CPU 3000 and from the selector 3110 in the cache control circuit 3110 out. The operation will now be described.

In the CDRAM 3200 a line in the DRAM field can be kept in the selected state by the DRAM active mode (ACT mode). The data of the memory cells connected to this one row are amplified and locked by the DRAM sense amplifier. The DRAM sense amplifier is used as a cache in the present invention.

[Write-back cache system]

In the write-back system (system with write-back strategy), the contents of the cache memory are transferred to the main memory in the event of a cache miss. More specifically, data is from the SRAM section 3210 to the DRAM section 3230 transferred (write back). There are two different types, the CDRAM 3200 address in the write-back cache. Specifically, this is (a) no assignment at the time of data write (data is not written to the SRAM section) and (b) data is written in both read and write operations in the event of a cache miss (assignment).

(i) Unassigned mode

Referring to the flowcharts of Fig. 112 and 113 access to the CDRAM is described without assignment.

When an access request from the CPU 3000 is present (step S2), it is determined (step S4) whether the process is a data read or a data write process. The in Fig. 111 shown controller 3108 determines whether there is an access request (chip selection connection).

If it is determined in step S4 that there is a data read, then it is determined whether the data from the CPU 3000 requested data are stored in the SRAM field or not (step S6). If it is determined that the CPU 3000 required value is in the SRAM field (which is due to a match, mismatch between the tag address stored in the external memory of the cache control circuit 3100 is saved, and the tag address by the CPU 3000 is established, determined), the SRAM read mode (SR cycle) is determined (step S7). Consequently, in the SRAM field, the selection of the memory cell is made in accordance with the block address and the set of the CPU address. The data of the selected SRAM memory cell are read. After step S7, the process returns to step S2.

When it is determined that the CPU 3000 requested data is not in the SRAM field (cache miss), it is first determined in step S6 whether the write indicator bit is set or cleared (step S8). If the write indicator bit is cleared, it means that the content of the cache matches the content of the main memory. The change in the data in the SRAM field has already been transferred to the data in the memory cell of the DRAM field. In this case it is determined whether the same page is addressed or not. More specifically, it is determined whether the CPU determines the row that has been selected in the DRAM field (step S10).

In the DRAM field, the line that was selected in the previous cycle is always kept in the selected state. Because part of a set address and a tag address from the CPU or a CPU address corresponds to a DRAM row address, it is determined by comparing the address sections whether the same page is accessed or not. This process is done in the controller 3108 who in Fig. 111 is shown performed. The line of the DRAM that is in the selected Zu stand is the line that was selected according to the tag address in the tag memory in the event of a cache miss in a previous cycle, or the line that is determined by the CPU address. After the write-back process, a new line can be selected according to the CPU address. Alternatively, the line that is selected in accordance with the tag address can be set to the selected state. Both structures can be used.

If determined in step S10 won't that the same page is addressed, that is, if it is determined that another Line of the DRAM field is set, the DRAM precharge mode (PCG cycle) accomplished (Step S12). As a result, the row that was in the selected state has in the unselected State shifted.

Then a DRAM active mode operation (ACT cycle) (Step S14). As a result, one line of the DRAM field becomes the one currently applied CPU address in the selected State, and the data of the memory cells associated with the chosen a row connected are detected, amplified and locked by the DRAM sense amplifier.

If determined in step S10 will that on the same Page is accessed, or if the DRAM active mode in step S14 accomplished the DRAM read transfer mode (DRT cycle) is executed (step S16). Consequently, the data of those memory cells are transferred to the read data transfer buffer circuit the one with the selected one Row of the DRAM field are connected, which is different from the column block address specified column block.

Then the buffer read transfer / read mode (DRT cycle) accomplished (Step S18). In this operating mode, the data stored in the Read data transfer buffers are stored according to the CPU address to the selected one Transfer line in SRAM field, and data become corresponding to the SRAM field in parallel with the data transmission the CPU address read (data can can be read directly from the read data transfer buffer circuit).

In step S8 shows a set Write indicator bit indicates that the Contents of the SRAM field and the corresponding set of the DRAM field differ are. In this case, the SRAM buffer write transfer mode (BWT cycle) executed (step S9). As a result, the data of the memory cells becomes that of the CPU address in the SRAM field chosen Transfer line to the write data transfer buffer circuit. Then, as in step S10, it is determined whether the same page is accessed is or not (step S11).

If determined in step S11 won't that the same page is addressed, the DRAM precharge mode is successively (PTG cycle) and DRAM active mode (ACT cycle) performed (steps S13 and S15). As a result, a row selection becomes corresponding in the DRAM field the present executed by the CPU applied address, and the data of the memory cells, the one with the selected one Line connected, are detected, amplified and locked by the sense amplifier. Then the DRAM read transfer mode (DRT cycle) and the buffer read transfer / read mode (DRTR cycle) performed (steps S17 and S19). Hence can Data even in the event of a cache miss or a page miss can be read at high speed.

Then the control waits for the next access request (Step S21). It is determined whether the next access request is the same Page concerns or not (step S27). Determining if on the same Page is accessed as follows: It is determined whether the line to which the memory cells with those in the buffer write transfer mode (BWT cycle) in step S9 in the write data transfer buffer circuit stored data belong to and the line that is currently selected in the DRAM field is the same line. This determination can be made using of the tag addresses. It is determined in step S23 that the same Page is accessed, the DRAM write transfer mode (DWT1 cycle) carried out (S29). Therefore, those in the write data transfer buffer circuit stored data transferred to the corresponding location of the DRAM field.

If it is not accessed Page, the DRAM precharge mode (PCG cycle) and the DRAM active mode are activated again (ACT cycle) one after the other accomplished (Steps S25 and S27), and the row of the DRAM field in which the in the write data transfer buffer circuit stored data are saved in the selected state added. After step S27, the flow proceeds to step S29. In order to the content of the set in the SRAM field matches the content of the corresponding one Of the DRAM field.

After steps S18 and S29 returns the river again back to step S2, around to the next Wait access.

If it is determined in step S4 that there is a data write operation, the in Fig. 113 shown control flow performed. If a data write operation is specified, it is first determined whether the memory cell in the SRAM field that the CPU wants to access exists (step S30). If this is the case, that is to say in the case of a cache hit, the SRAM write mode (SW cycle) is executed (step S32), and data are written into the corresponding memory cell of the SRAM field in accordance with the CPU address. Then the corresponding write indicator bit in the control circuit 3100 set. As a result, a state is displayed in which the contents of the SRAM field and the Contents of the corresponding data block of the DRAM field are different from one another (step S34). Upon completion of step S34, control returns to step S2, which is in Fig. 112 is shown.

It is determined in step S30 that a cache miss the buffer write mode (GW cycle) is executed (step S31). As a result, write data becomes corresponding to the CPU address of the SRAM written to the appropriate location of the write data transfer buffer circuit. With locking this write data in the write data transfer buffer circuit holds the Tax flow on, around to the next Wait for access request (step S33). If the next access request is made, it is determined whether this access request concerns a row, which is currently in the DRAM field in a selected one State is (step S35).

It is determined that the CPU requests access to a row that is different from the row, the present is selected in the DRAM field, steps S37 and S39 are carried out, the DRAM field is preloaded and activated, and a line corresponding to the CPU address will in the selected State shifted. Subsequently becomes the DRAM write transfer mode (DWT cycle) executed, and the data stored in the write data transfer buffer circuit are written to a corresponding position on the line, the present selected in the DRAM field is (step S41). Step S41 is carried out even if it is determined in step S35 that the same page is accessed shall be. After completing Step S41 returns control to step S2.

As described above can be used by using the sense amplifiers of the DRAM section as Cache the data write / read are executed at high speed, if the data of a memory cell requested by the CPU is not stored in the SRAM field, but locked in the DRAM field by the sense amplifier are.

When transferring data from the write data transfer buffer circuit for the DRAM field, the command DWT (DWT1) is executed continuously as long as the CPU addresses the same line of the DRAM field. That enables one Data writing at high speed.

(ii) Assignment mode

The Fig. 114 and 115 Figure 14 shows flow diagrams of cache access when an assignment is made to a cache miss in a write-back strategy cache. With reference to the Fig. 114 and 115 the access operation of the CDRAM is described.

Fig. 114 shows a flow chart of the operation of data reading. The in Fig. 114 The process flow shown matches the previous unassigned process flow that is in Fig. 112 is shown. Corresponding steps are therefore designated by the same reference numerals and their detailed description is not repeated here.

Fig. 115 shows a flow diagram of the data write operation with assignment in a cache system with write-back strategy. In the data write process, it is first determined in S50 whether there is a cache hit or not. If a cache hit is detected, the SRAM write mode (SW cycle) is executed (step S51). In accordance with the CPU address, data is written into the corresponding memory cell of the SRAM field. Then in the cache control circuit 3100 set the write indicator bit corresponding to that of the CPU address set (step S51). Then the control sequence returns to step S2 shown in FIG Fig. 114 is shown.

If it is determined in step S50 that the Access a cache miss the buffer write mode (BW cycle) is executed (step S53). It is then determined whether the CPU's access request is a Memory cell in the row determined that is in the DRAM field currently in the selected State is (step S54). If the CPU address does not match the row address the line in the DRAM field matches, currently in the chosen State, the DRAM precharge mode (PTG cycle) is executed (step S55). Then in agreement the DRAM active mode (ACT cycle) was carried out with the CPU address (step P.56).

If it is determined in step S54 that on the same page is accessed, the DRAM write transfer mode / read mode (DTW1R cycle) after step S56 accomplished (Step S57). Accordingly, those in the write data transfer buffer circuit stored data to the corresponding column block position in the selected line of the DRAM field. With the command DWT1R the data of the selected column block transferred to the read data transfer buffer circuit simultaneously with the data writing in the DRAM field. Subsequently the buffer read transfer mode (BRT cycle) is executed (step S58). consequently are transferred to the read data transfer buffer circuit Data stored in the corresponding line of the SRAM field. So be the write data is stored both in the DRAM field and in the SRAM field.

It is then determined whether the write indicator bit is set or cleared (step S59). If the write indicator bit is cleared, control returns to step S2. If the write indicator bit is set, the buffer write transfer mode (BWT cycle) is executed, and the memory cell data of the SRAM specified by the CPU address is transferred to the write data transfer buffer circuit (step S60). When the next access request is pending (step S61), it is determined whether the data that the CPU wants to access at that moment is on the row that is currently in the DRAM field in the selected state (step S62). It is determined that the same page is not accessed, the precharge mode (PCG cycle) and the DRAM active mode (Acc cycle) are performed in succession (steps S63 and S64), and the row selection process of the DRAM field becomes the same CPU address carried out. If it is determined in step S62 that the same page is being accessed, or after step 564 is completed, the DRAM write transfer mode (DWT cycle) is executed. Accordingly, the data stored in the write data transfer buffer circuit is transferred to the corresponding position of the selected row of the DRAM field (step S65). Due to the operating mode described above, the line in the DRAM field corresponding to the CPU address is always in the selected state, the DRAM sense amplifier can be used as a pseudo cache in the event of a cache miss, and thus the deterioration in the access time for a cache Misses are minimized.

[Write-through mode]

In write-through mode be for the case that data the written data is always written into the SRAM field written in the corresponding memory cell of the DRAM field. In this case, the process flow differs depending of the presence / absence of an assignment.

(a) Copy procedure with assignment

The Fig. 116 and 117 show flowcharts of the operation according to the write-through procedure when an assignment is made. With reference to the Fig. 116 and 117 the access to the CDRAM in the cache memory system is described.

First, referring to Fig. 116 the data reading process is described.

There is an access request from the CPU before (step S70) determines whether the access request represents a data read or write (step S72). If it is found that a If there is a data read, a cache hit / miss is determined (Step S74). In the event of a cache hit, the SRAM read mode (SR cycle) is executed, and the data of the memory cell, from the CPU address in the SRAM field are read, are read (step S75). After step S75 returns control returns to step S70.

In the event of a cache miss first determined whether the CPU address true that currently in the DRAM field in the selected State (step S76). Is it determined that the CPU that line of the DRAM field that is currently selected then the DRAM read transfer mode (DRT cycle) is performed (step S78). Therefore, the data of the column block by the CPU address is set in the DRAM field, transferred to the read data transfer buffer circuit. It is determined in step S76 that the CPU address is different Line of the DRAM field, the DRAM precharge mode (PTG cycle) and the DRAM active mode (ACT cycle) is executed (steps S77 and S79). In the DRAM field, the line specified by the CPU address is in the selected state offset, and from the DRAM sense amplifiers the data of the memory cells connected to the selected row, locked. After step S79, step S78 is executed, and the data block specified by the CPU address is transferred to the read data transfer buffer circuit.

Then the buffer read transfer / read mode (BRTR cycle) accomplished (Step S80), the data stored in the read data transfer buffer circuit are transmitted to the corresponding position of the SRAM field, and the data requested by the CPU is read. After completing step S80 turns the control flow Step S70 back.

In step S72, the in Fig. 116 is determined that the write mode is set, the in Fig. 117 shown operation performed. First, a cache hit / miss is determined (step S82). When a cache hit is detected, the buffer write transfer / write mode (BWTW cycle) is performed. As a result, external write data is written into the memory cell of the SRAM array specified by the CPU address and the corresponding register of the write data transfer buffer circuit. In this mode of operation, the data of the row selected in the SRAM field and the write data are stored in the write data transfer buffer circuit.

If the next access request after step S74 is created (step S86), it is determined whether this access request defines the line of the DRAM field that is in the selected state is located (step S88). It is determined that the same row is set is, that is, same page is set, the DRAM write transfer mode (DWT cycle) accomplished (Step S90). As a result, those stored in the write data transfer buffer circuit are stored Data on the selected Transfer the column of the DRAM field (which is determined by the CPU address).

If a line other than the selected line of the DRAM array is set in step S88, the DRAM precharge mode (PCG cycle) and the DRAM active mode (ACT cycle) are executed in accordance with the CPU address to the line specified by the CPU address in the selected Set state (steps S92 and S94). Through step S94, the row corresponding to the CPU address in the DRAM field is set to the selected state, the data of the memory cells connected to the selected row are acquired, amplified and locked by the sense amplifier, the control flow returns to step S90 , and the DRAM write transfer mode is executed.

It is determined in step S82 that the access is a Cache miss the buffer write mode (BW cycle) is executed (step S81). As a result, external write data becomes the corresponding buffer the write data transfer buffer circuit. The control flow stops in this state to move on to the next Wait for access request. The next access request is created (Step S83) becomes similar Way as in step S88 determines whether the same page is set is or not. If the same page is set, the DRAM write transfer mode is (DWT1 cycle) performed (Step S87). Therefore, the write data stored in the write data transfer buffer circuit have been selected Transfer column of the DRAM field.

If it is determined in step S85 that another page the DRAM precharge mode and the DRAM active mode executed (steps S89 and S91), and the line specified by the CPU address in the DRAM field in the selected State shifted. Is closing Carried out step S87, and those written in the write data transfer buffer circuit Data is transferred to the corresponding location in the DRAM field. After the steps S90 and S87 reverse the control flow Step S70 back.

(b) Copy procedure without assignment

The Fig. 118 and 119 show flowcharts of the CDRAM access process without allocation in a write-through cache. With reference to the Fig. 118 and 119 the process flow is described. Fig. 118 shows the process flow in data read mode. This is the same process as for the copy-through procedure with assignment, like that in Fig. 116 is shown, and therefore the corresponding steps are indicated by the same reference numerals and their detailed description is not repeated here.

Referring to the flow chart of Fig. 119 the data write process with assignment according to the copy procedure is described.

In step S100, a cache hit / miss determined. If a cache hit is detected, the buffer write transfer mode (BWTW cycle) executed (Step S102). This BWTW cycle makes external write data written in the corresponding memory cell of the SRAM field, and the data block (one line) of the SRAM that contains the written ones Contains data, is written into the write data transfer buffer circuit. In In this state, the controller waits for the next access.

At the next access request (step 104) it is determined whether the CPU address specifies that line, which is currently in the DRAM field in the selected State is (step 106). Sets the CPU address of the selected line in the DRAM field, the DRAM write transfer mode (TWT cycle) accomplished (Step S108). Consequently, those in the write data transfer buffer circuit stored data for the corresponding column block of the selected row in Transfer DRAM field.

It is determined in step S106 that the CPU address not the selected one Line of the DRAM field, the DRAM precharge mode becomes in the DRAM field (PCG cycle) executed, being the DRAM field returns to the precharge state (Step S107). Then, using the CPU address, the DRAM active mode (ACT cycle) executed in DRAM field a row is selected and the data of the memory cells associated with the selected row connected, are recorded reinforced and from the sense amplifier locked (step S112). Then step S108 is executed, and the data stored in the write data transfer buffer circuit are transferred to the corresponding position of the selected line of the DRAM.

It is detected in step S100 that a cache miss the buffer write mode (BW cycle) is executed first, and external data is written into the write data transfer buffer circuit (Step S101). Then it is detected whether the CPU address specifies the line that is selected in the DRAM field (Step S103). If so (that is, it will be on the same page accessed), the DRAM write transfer mode / read mode (DWT1R cycle) performed (Step S105). So that in the write data transfer buffer circuit stored data for the corresponding position of the selected line transmitted in the DRAM field and further to the read data transfer buffer circuit.

If it is determined in step S103 that not same page is set, the DRAM precharge mode (PCG cycle) carried out (Step S107), and then in accordance with the CPU address the DRAM active mode (ACT cycle) is executed (step S109). consequently the page specified by the CPU address is selected in the DRAM field and the DWT1R cycle executed (step S105). Then the buffer read transfer mode (BRT cycle) is executed, and the data in the read data transfer buffer circuit are transferred to the line that from the CPU address in the SRAM field is set.

As described above the hit process for another address can be done quickly in data write mode accomplished when data is in the SRAM array or the write data transfer buffer circuit to be written. This allows access at high speed.

[Detailed structure of the bidirectional data transmission circuit]

Fig. 120 shows the structure of the bidirectional data transmission circuit. As in Fig. 120 is shown, the bidirectional data transmission circuit has a write data transmission circuit 3520 for transferring data to the DRAM section 3500 and a masking circuit 3530 for masking the transfer of write data to the write data transfer circuit 3520 on. the write data transfer circuit has an intermediate write data register TDTBW for temporarily storing data and a write data transfer buffer TDBW, which receives data from the intermediate register TDTBW, for transferring the data to the DRAM section 3500 on. Sometimes the write data transfer buffer DTBW also transfers data to the read data transfer buffer DTBR.

The masking circuit 3530 comprises an intermediate masking register TNR, a master masking register MR which receives the masking data from the intermediate masking register TMR, and a masking gate circuit 3540 , which receives the masking data from the master masking register MR, for masking the write data from the write data transfer buffer DTBW. The operation for masking the write data transfer will now be briefly described.

First, referring to Fig. 121 describes an operation when the block write mode is executed.

In this case, externally created Data in a corresponding register of the intermediate register TDTBW written according to the output from the column decoder. Parallel the masking data are used for writing data into the intermediate register TDTBW the corresponding register in the intermediate masking register TMR reset. The deferred Enable masking data the passage of the data. Set masking values block the passage of data.

With reference to Fig. 122 the write data transfer process to the DRAM field is described. When the DRAM write transfer mode is set, the data stored in the intermediate register TDTBW is transferred to the write data transfer buffer DTBW. In parallel with this transfer, the masking values of the intermediate masking register TMR become the master masking register MR and data for the masking gate circuit 3540 transfer. The masking gate circuit 3540 masks the write data from the write data transfer buffer DTBW in accordance with the masking data applied and transfers it to the DRAM field.

The data transfer from the intermediate registers TDTBW and TMR to the corresponding buffers DTBW and MR is in the first cycle after the data transfer has been defined. At the At the end of the first cycle, the masking data of the intermediate masking register TMR all set. From the next cycle Is it possible, Data in the write data transfer circuit (intermediate data register) to write according to the buffer write mode. Because the masking register is formed, it is possible write only the required data in the DRAM field. If Transfer data from the SRAM field the masking data will be in the intermediate masking register all reset. In this case, the data of the write data transfer buffer all transferred to the DRAM field section. With reference to the special signal diagrams, the transmission process of the write data.

Fig. 123 Fig. 14 is a signal diagram of the operation of the bidirectional data transfer circuit when data transferred from the SRAM array is written into the DRAM array. As in Fig. 123 is shown, the DRAM active mode (ACT cycle) is executed in the first cycle of the master clock signal K in the DRAM section. As a result, a row selection operation is performed in the DRAM field. In the SRAM field, the buffer write transfer mode (BWT cycle) is determined in accordance with the conditions of the control clock signals CCO #, CC1 # and the write activation signal WE #. As a result, the data of one row of memory cells ( 16 Bits) selected in the SRAM field are transferred to the intermediate data register (value 0 to value 15). In the data transfer cycle from the SRAM field to the intermediate data register, the masking data (masking 1 until masking 15 ) of the intermediate masking register all reset.

In the fourth cycle of the master clock signal K becomes the DRAM write transfer mode (DWT1 cycle) by the column address strobe signal CAS # and the data transfer determination signal DTD # established. In the DWT1 cycle, the data (value 0 to value 15), which are stored in the intermediate register to the write data transfer buffer DTBW <0 - 15> (DTBWO - DTBW15) transmitted. At the end of the first cycle of the DWT1 cycle, the masking data all set in the intermediate masking register. From the fifth cycle of the master clock signal K, the data transmission from the SRAM field to Intermediate data register possible.

After the latency of the DWT1 cycle has passed, the write data have already been transferred from the write data transfer buffer DTBW in accordance with the masking data to the DRAM field. In the seventh cycle of the master clock signal K, the BWT cycle and the mask are determined again Intermediate mask register data are all reset. In the eighth cycle of the master clock signal K, the DRAM write transfer mode 2 (DWT2 cycle). In this case, no data transfer between the intermediate data register and the write data transfer buffer is carried out. The data stored in the write data transfer buffer is transferred to the selected memory block of the DRAM field.

After the ninth cycle of the master clock signal K becomes NOP mode (no operation) and the internal state of the CDRAM changes Not.

When transferring write data from the SRAM field the masking data of the intermediate masking register all reset. In contrast, are in data transmission from the write data transfer buffer to the DRAM field, that is, at the data transmission from the intermediate data register to the write data transfer buffer, the masking data of the intermediate masking register after completion of this Cycle (clock signal cycle) all set.

Fig. 124 Fig. 12 shows a signal diagram of the change in masking data when the buffer write mode is executed. As in Fig. 124 is shown, the DRAM active mode (ACT cycle) is executed in the first clock signal cycle of the master clock signal K. In contrast, the block write mode (BW cycle) is carried out in the SRAM section, and externally applied data (value 0) are written into the corresponding registers of the intermediate data register in accordance with the address bits As0 to As3. In parallel to data writing, the masking data (masking value 0) of the corresponding intermediate masking register are reset: Subsequently, a maximum of 16 data bits can be repeatedly written to the intermediate data register (the intermediate data register and the write data transfer buffer are 16 bits wide). When the respective data is written, the masking data of the corresponding intermediate masking register are reset.

In the fourth cycle of the master clock signal K is in the DRAM section the DWT1 cycle creates. When this mode of operation is set, becomes one in the first cycle (the fourth clock signal cycle of the master clock signal K) data transfer from the intermediate data register to the write data transfer buffer. With the conclusion of the The first cycle becomes the masking data of the intermediate masking register all set. Then the write data is transferred to the write data transfer buffer have been selected Transfer memory cell block of the DRAM array. After data transfer from the intermediate data register to the write data transfer buffer, that is, in the second Cycle of DWT1 mode it is possible Write data to the intermediate data register. As in Fig. 124 is shown, is from the fifth Cycle of the master clock signal K again the buffer write (BW cycle) executed. In parallel to data writing, the masking data of the corresponding Intermediate mask register reset.

When performing the process described above can the data transfer to the DRAM field by transferring masking data is securely masked. Because the two-stage structure of the intermediate register and write data transfer buffer is formed, it is possible to write data from the outside or from the SRAM field itself during the data transmission to pass to the DRAM field. This allows access at high speed.

Fig. 125 shows the structure of the write data transmission system. As in Fig. 125 is shown, the write data transfer buffer circuit 3520 an intermediate data register 4002 and a write data transfer buffer 4004 on. The intermediate data register 4002 and the write data transfer buffer 4004 both have the structure of an inverter latch.

The write data transfer buffer circuit 3520 also has a transfer gate 4010 which receives an output signal / SSA of the SRAM sense amplifier, a transfer gate 4012 , which switches in response to the buffer write transfer activation signal WWTE, a transfer gate 4018 , which switches depending on the output signal SSA0 from the SRAM sense amplifier, a transfer gate 4020 , which switches through depending on the buffer write transfer activation signal BWTE, and transfer gate 4014 and 4016 , which switch in response to the buffer gate write signal DYW, which is generated in the buffer write mode only for the selected register. The buffer gate write signal DYW is generated only for the register in data writing which is subjected to data writing. The output signals SSA0 and / SSA0 of the SRAM sense amplifier correspond to the output signal of the first sense amplifier 1612 who in 84 is shown.

The transfer gates 4010 and 4012 are connected in series. If both are switched through, they set the latch node / E of the intermediate data register 4002 to the ground potential level. The transfer gates 4018 and 4020 represent the latch node E of the intermediate data register 4002 to the ground potential when the output signal SSA of the SRAM sense amplifier and the buffer write transfer activation signal BWTE both reach level "H". The output signals / SSA0 and SSA0 of the sense amplifier are complementary to one another. Therefore, when the buffer write transfer mode is set, the transfer gates 4012 and 4020 both are turned on, and complementary data is sent to latch nodes / E and E of the intermediate data register 4002 locked.

When the buffer write mode is set, the buffer gate write signal BYW is generated only for those data registers which are subjected to data write. So that the gates 4014 and 4016 switched through, and the data on the internal write data lines DBW and / DBW are from the intermediate data register 4002 locked. Complementary data is transferred to the internal write data lines DBW and / DBW.

The write data transfer buffer circuit 3520 also has a transfer gate 4022 , depending on the output signal of the latch node / E of the intermediate data register 4002 is switched through, a transfer gate 4004 , which is switched on depending on the DRAM write transfer activation signal BWTE, a transfer gate 4026 , depending on the output signal of the latch node E of the intermediate data register 4002 is switched through, and a transfer gate 4024 , which is switched on depending on the DRAM write transfer activation signal DWTE. The transfer gates 4022 and 4023 are connected in series. They transmit data that represent the inverse of the data at the latch node / E of the intermediate register 4002 are locked to the latch node / F of the write data transfer buffer 4004 depending on the DRAM write transfer activation signal DWTE. The transfer gates 4024 and 4026 are connected in series and transmit the data that is the inverse of the data at the latch node E of the intermediate data register 4002 represent, to the latch node F of the write data transfer buffer 4004 depending on the DRAM write transfer activation signal DWTE.

And the masking circuit 3530 has an intermediate masking register 4006 , a master masking register 4008 and a mask gate circuit 3540 on. The registers 4006 and 4008 are both formed by inverter latches.

The masking circuit 3530 also has a transfer gate 4028 , which is dependent on the buffer gate write signal DYW, for setting the latch node / G of the intermediate masking register 4006 to ground potential, a transfer gate 4030 , which is dependent on the buffer write transfer activation signal BWTE, for setting the latch node / G of the intermediate masking register 4006 to ground potential, a transfer gate 4032 which is switched by the command register depending on the mask register setting command / MRS, a transfer gate 4034 , which is turned on in response to the buffer gate write signal WYW, and a transfer gate 4036 , which is switched on depending on the DRAM write transfer activation signal DWTE.

The transfer gates 4032 . 4034 and 4036 are connected in series and switch through when the signal supplied to the respective gate reaches the "L" level. Are the gates 4032 . 4034 and 4036 all switched through, a signal with supply potential level becomes the latch node / G of the intermediate masking register 4006 transfer.

The masking circuit 3530 also has a transfer gate 4037 , depending on the value of the latch node / G of the intermediate masking register 4006 is switched through, a transfer gate 4039 , which is switched depending on the DRAM write transfer activation signal DWTE, a transfer gate 4040 , depending on the output signal at the latch node G of the intermediate masking register 4006 is switched through, and a transfer gate 4030 , which is switched on depending on the DRAM write transfer activation signal DWTE. The transfer gates 4037 and 4039 are connected in series and transmit a signal with ground potential level to the latch node / H of the master masking register 4008 when both are switched through.

The transfer gates 4038 and 4040 are connected in series and transmit a signal with level "L" (ground potential level) to the latch node H of the masking register 4008 when both are switched through. The intermediate masking register 4006 is set when its masking node / G is set to "H" and is reset when its masking node / G is at "L".

The masking gate circuit 3540 has a 3-input gate circuit 4042 , the DRAM write data activation signal DWDE, the output signal of the latch node / F of the write data transfer buffer 4004 and the output of the latch node / H of the masking register 4008 receives an inverter circuit 4046 for inverting the output signal of the gate circuit 4042 , a 3-input gate 4044 , the DRAM write data activation signal DWDE, the locked data at the latch node S of the write data transfer buffer 4004 and the latched data at latch node / H of the mask register 4100 receives, as well as an inverter circuit 4048 for inverting the output signal of the gate circuit 4044 on.

The gate circuit 4042 sets its output signal to "L" only when its three inputs all reach "H" (it represents a NAND circuit). The gate circuit 4044 only emits a signal with level "L" if its three inputs are all at "H".

Between the mask gate circuit 3540 and the global IO lines GIOa and / GIOa is a write amplifier 3550 educated. The write amplifier 3550 has n-channel MOS transistors 4052 and 4054 , the output signal of the inverter circuit at their gates 4046 received, and n-channel MOS transistors 4050 and 4056 , the output signal of the inverter circuit at their gates 4048 received on. The transistors 4050 and 4054 are connected in series between the supply potential and the ground potential, while the transistors 4052 and 4056 between the supply potential and the ground potential are connected in series. The connection point between the transistors 4050 and 4054 is connected to the global IO line GIOa while the connection point between the transistors 4052 and 4056 is connected to the global IO line / GIOa.

The operation will now be briefly described. When write data is to be transferred from the SRAM field, the buffer gate write signal DYW is not generated, but is kept in the "L" state. The data on the SRAM bit line pair SBL is amplified by the SRAM sense amplifier and to the gates of the transfer gates 4010 and 4016 transfer. The sense amplifier output signal SSA0 is assumed to be "H". In this case the transfer gate 4010 locked and the transfer gate 4018 connected through.

When the output of the SRAM sense amplifier has stabilized, the buffer write transfer enable signal BWTE rises to "H" and the transfer gates 4012 and 4020 are switched through. Because the transfer gate 4010 locked and the transfer gate 4018 is switched through, the potentials "L" and "H" become the latch nodes E and / E of the intermediate data register 4002 transferred and locked there.

In the masking circuit 3530 switches the transfer gate 4030 depending on the rise of the buffer write transfer activation signal BWTE and the potentials at the latch nodes / G and G of the intermediate masking register 4006 reach the "L" or "H" level. The mask register setting bit / MRS is assumed to be "L". The transfer gates 4032 . 4034 and 4036 are connected. If the transfer gate 4030 is switched on as a function of the buffer write transfer activation signal DWTE, the potential of the latch node / G becomes slightly lower than the potential at the latch node G. This drop in the potential is detected by the inverter in the intermediate masking register 4006 amplified and accordingly the potentials at the latch nodes G and / G reach the levels "H" and "L".

As a result of the sequence of operations described above, the masking data in the intermediate masking register become in the data transfer from the SRAM field to the write data transfer buffer circuit 4006 synchronous with the data transfer to the intermediate data register 4002 reset.

In the buffer write mode, that is, when external data is to be written into the write data transfer buffer circuit, the buffer gate write signal BYW is generated only for the corresponding write data transfer buffer. In this case, external write data via the transfer gates 4014 and 4016 to the intermediate data register 4002 transferred while the corresponding intermediate masking register 4006 is reset.

Around the DRAM write transfer enable signal (DWTE), which indicates the data transfer from the write data transfer buffer to the DRAM field, is now generated (by setting the DRAM write transfer mode). As a result, the transfer gates switch 4023 . 4024 . 4039 and 4038 by. The potentials at the latch nodes E and / E of the intermediate data register are now at "L" and "H" (the SRAM sense amplifier output signal SSA0 is at "H"). As a result, the transfer gate switches 4022 through, the transfer gate 4026 locks, and the latch nodes F and / F of the data transfer buffer 4004 reach the "H" or "L" level.

In the master masking register 4008 the potential of the latch node / G is at "L", the transfer gate 4037 is locked and the transfer gate 4040 connected through. Therefore, the latch nodes H and / H are at "L" and "H", respectively.

While the DRAM write transfer enable signal WRTE is being generated, the transfer gate 4036 blocked. The transfer gate 4030 is also blocked. Although the potential of the latch node / G of the intermediate masking register 4006 is locked by the inverter latch, it is placed in an electrically floating state during this period. When the DRAM write transfer enable signal DWTE drops to "L", the transfer gate switches 4036 by, the signal with supply potential level is transmitted to the latch node / G, and that in the intermediate masking register 4006 stored masking value is set (the potential at the latch node / G is at "H").

After data transfer to the write data transfer buffer 4004 and master masking register 4008 the DRAM write data activation signal DWDE is generated. Consequently, those in the write data transfer buffer 4004 stored data and that in the master masking register 4008 stored masking data to the masking gate circuit 3540 created. The potential is now at the latch node F of the write data transfer buffer 4004 to "H" and the potential at latch node F is at "L". The potential at the latch node / H of the masking register 4008 lies on "H". As a result, the output signal of the gate circuit reaches 4042 the level "N" and the output signal of the gate circuit 4044 the level "L". The output signals of the circuits 4042 and 4044 are from the inverter circuits 4046 and 4048 inverted. Consequently, in the write driver (amplifier) 3550 the transistors 4050 and 4056 turned on and the transistors 4052 and 4054 blocked. The potential on the global IO line GIOa reaches level "H" and the potential on the global IO line / GIOa level "L".

If the potential at the latch node / H of the master masking register 4008 is at "L" to mask the data transmission, the output signals of the gate circuits reach 4042 and 4044 both the "H" level and the output signals of the inverter circuits 4046 and 4048 the level "L". Consequently, the transistors 4050 . 4052 . 4054 and 4056 of the write amplifier 3550 all locked, the potential on the global IO lines GIOa and / GIOa does not change, and the data from the write data transfer buffer circuit are not transferred.

The sequence of operations described above can securely transfer write data at high speed. After the data transfer from the intermediate register to the write data transfer buffer, the masking data of the intermediate masking register are always kept in the set state. Also in the buffer write mode, after the data transfer to the master masking register, that is, after the generation of the BWTE signal, the masking data of the intermediate masking register 4006 kept in the set state. The signals of this sequence of processes are in Fig. 126 shown.

In Fig. 126 SWL denotes the SRAM word line, SBL the SRAM bit line pair and DWL the DRAM word line. The dashed lines show the signals when writing the buffer.

Fig. 127 shows a structure for the read data transfer buffer circuit. As in Fig. 127 is shown, the read data transfer buffer circuit has sense amplifiers 5004 and 5008 , which are dependent on the DRAM preamplifier activation signal DPAE, for amplifying the potential on the global IO lines GIOa and / GIOa, a preamplifier 5006 for further amplifying the data from the sense amplifiers 5004 and 5008 have been amplified, depending on the DRAM preamplifier activation signal DPAE, a slave data register 5000 to lock the data from the preamplifier 5006 and a master data register 5006 to receive the data in the slave data register 5000 are stored, depending on the DRAM read transfer activation signal DATE.

The sense amplifier 5004 has a p-channel MOS transistor 5040 which receives the signal on the global IO line GIOa at its gate, an n-channel MOS transistor 5044 , which receives the signal on the global IO line GIOa at its gate, and an n-channel MOS transistor 5040 , which becomes conductive depending on the DRAM preamplifier activation signal DPAE. The transistors 5040 . 5052 and 5044 are connected in series between the supply potential and the ground potential. From the connection node between the transistors 5040 and 5042 an amplified output signal is emitted.

The sense amplifier 5008 has a p-channel MOS transistor 5041 and an n-channel MOS transistor 5045 , which receive the signal on the global IO line / GIOa at their gates, and an n-channel MOS transistor 5043 , which switches in response to the DRAM preamplifier activation signal DPAE. The transistors 5041 . 5043 and 5045 are connected in series between the supply potential and the ground potential. The signal on the global IO line / GIOa that is amplified is from the connection node between the transistors 5041 and 5043 output as an output signal.

The preamplifier 5006 has p-channel MOS transistors 5060 and 5062 , which are connected in parallel between the supply potential and a node J, and p-channel MOS transistors 5064 and 5066 connected in parallel between the supply potential and a node / J. The transistors 5060 and 5066 receive the DRAM preamplifier activation signal DPAE at their gates. The gate of the transistor 5062 is with the node / J and the gate of the transistor 5064 connected to node J.

The slave data register 5000 has the structure of an inverter latch. The p-channel MOS transistors 5068 and 5070 are between the output nodes J and / J of the preamplifier 5006 and the latch nodes N and / N of the slave data register 5000 are formed and are selectively switched depending on the signal potential from the nodes J and / J in order to transmit the supply potential to the nodes N and / N.

For the slave data register 5000 are n-channel MOS transistors 5072 and 5074 , which are turned on in response to the DRAM preamplifier activation signal DPAE, and n-channel MOS transistors 5076 and 5078 which receive the signals at nodes J and / J at their gates. The transistors 5072 and 5076 are between the latch node N of the slave data register 5000 and the ground potential connected in series. The transistors 5074 and 5078 are connected in series between the latch node / N and the ground potential.

The masking data register 5002 has the structure of an inverter latch. For the mask data register 5002 are n-channel MOS transistors 5080 and 5082 , which are turned on in response to the DRAM read transfer activation signal DRPE, and n-channel MOS transistors 5084 and 5086 , the signals to the latch nodes N and / N of the slave data register at their gates 5000 received, educated. And the transistors 5080 and 5084 are between the latch node N of the master data register 5002 and the ground potential connected in series. The transistors 5082 and 5086 are connected in series between the latch node / N and the ground potential.

The read data transfer buffer circuit also has inverter circuits 5052 and 5054 for inverting and amplifying the potentials at the latch nodes N and / N of the masking data register 5002 and transfer gate 5058 and 5056 , which are dependent on the buffer read transfer activation signal, for transmitting the output signals of the inverters circuits 5052 and 5054 to the SRAM bit lines SBLa and / SBLa. The signals at the latch nodes N and / N of the master data register 5002 are selected using a selector ( 1013 ) who in 84 is shown, and signal lines Buf and / Buf are transmitted to the first sense amplifier. The signal lines Buf and / Buf form a path for reading data from the read data transfer buffer in the buffer read mode.

The operation will now be described. When the DRAM read transfer mode a row and a memory cell block are set in the DRAM field selected, and change according to the data read from the DRAM memory cell the signal potentials on the global IO lines GIOa and / GIOa.

When the DRAM preamplifier enable signal DTAE is subsequently generated, the sense amplifiers become 5004 and 5008 as well as the preamplifier 5006 activated. It is assumed that the signal potential on the global IO line GIOa is "H", while the signal potential on the global IO line / GIOa is "L". In this case, the potentials at nodes J and / J are "L" and "H", respectively. The signal potential transmitted to the nodes J and / J is from the transistors 5062 and 5064 amplified at high speed. The transistors 5060 and 5066 have been disabled in response to the DRAM preamplifier enable signal DPAE. The transistors 5060 and 5066 are used to precharge nodes J and / J to the supply potential. The transistors 5062 and 5064 have the task of keeping nodes J and / J pre-charged at the same potential (when the DRAM preamplifier enable signal is at "L").

The signal transmitted to nodes J and / J is through the transistors 5068 . 5070 . 5076 . 5078 . 5072 and 5074 to the slave data register 5000 transfer. The transistors 5072 and 5074 have been switched depending on the DRAM preamplifier activation signal DPAE.

Now the potential of node J is at "L" and the potential of node / J is at "H". Hence the transistors 5068 and 5078 turned on and the transistors 5070 and 5076 lock. The potentials are therefore at the latch nodes N and / N of the slave data register 5000 to "H" or "L". The sequence of these operations completes the data transfer to the slave data register in the read data transfer buffer circuit.

The DRAM read transfer activation signal is then generated. As a result, the transistors switch 5080 and 5082 through, and to the latch nodes N and / N of the slave data register 5000 Stored data becomes latch nodes N and / N of the master data register 5002 transfer. Because the potential at latch node N is "H", the transistor switches 5084 through and the transistor 5086 locks. As a result, the signal potentials at the latch nodes N and / N reach the levels "L" and "H", respectively. The sequence of these operations will save data in the master data register 5002 completed in the read data transfer buffer circuit. The signal potentials at the latch nodes N and / N can be read via the signal lines Buf and / Buf. More specifically, after the latency has passed, the data stored in the read data transfer buffer can be read at a high speed by a buffer read mode operation.

The buffer read transfer activation signal BRTE is generated at the time of the data transfer to the SRAM field. As a result, the output signals of the inverter circuits 5052 and 5054 over the gates 5058 and 5056 to the SRAM bit lines SBLa and / SBLa. At the in Fig. 127 shown structure can the inverter circuits 5052 and 5054 have the structure of a 3-state inverter circuit which is activated in dependence on the buffer read transfer activation signal BRTE.

Fig. 128 shows a signal diagram of the read data transfer buffer circuit shown in FIG Fig. 127 is shown. In Fig. 127 the global IO lines Gloa and / GIOa are shown in such a way that they are precharged to an intermediate potential (Vcc / 2; Vcc represents the supply level). These lines can also be precharged to the level of the supply potential, as shown by the dashed line in Fig. 128 is indicated. In Fig. 128 the precharge potential of the SRAM bit line SBLa and / SBLa is shown as an intermediate potential. In this case too, the lines can be precharged to the level of the supply voltage using a clamp circuit, as shown by the dashed line. The length of time that the DRAM bit line is kept in the selected state can be determined by the latency. The timing of the generation of the DWDE signal is determined by the latency. The generation period of the DPAE signal can be determined by the master clock signal. The same applies to the signals in the diagram below Fig. 126 ,

Because the read data transfer buffer circuit also the 2-stage latch circuit structure with slave data register and master data register, can the data transmission run safely and the latency control (control of the amount of time that is necessary so that stable data appears at the SRAM field or the data input / output connector DQ) can be done easily and safely.

Fig. 129 Fig. 14 shows a circuit structure for executing control related to data transmission. As in Fig. 129 is shown, generates the SRAM control circuit 6000 a signal BWT which is dependent on the internal control clock signals CCO, CC1 and the write activation signal WE, setting the data write mode for the write data transfer buffer circuit, a signal BRT which a process of reading data from the read data transfer buffer circuit for the data input / output port (or the SRAM array) and a signal W / R indicating whether data write or data read should be performed. The SRAM driver circuit 6006 generates the necessary control signals, namely the buffer write transfer enable signal BWTE, the buffer read transfer enable signal BRTE and similar signals depending on the signals BWT and BRT, and drives the sense amplifier and selects a row in the SRAM field.

The column decoder 6002 decodes block address bits As0 to As3 and generates a signal to select a corresponding bit position. The gate circuit 6004 generated in response to the W / R signal from the SRAM control circuit 6000 which specifies the data input / output operation and the inverted signal of the mask activation signal M and the buffer gate write signal BYW by selectively applying a bit selection signal from the column decoder 6002 is let through. The gate circuit 6004 leaves the output signal of the column decoder 6002 as a buffer gate write signal BYW only if data write is specified (in BW mode). The bit selection signal RYW from the column decoder 6002 is also used for bit selection of the data output system.

It can use a structure where the column decoder 6002 is activated only when an operation mode for performing data input / output with the environment such as the SRAM read mode, the SRAM write mode, the buffer read mode, the buffer write mode, etc. under the control of the SRAM control circuit 6000 is performed. In the SRAM driver circuit 6002 the master clock signal K is applied because a structure is used in which the transmission control signal is generated depending on the clock signal at the time of data transmission. This structure effects latency control. The length of the latency is previously set in the command register.

The DRAM control circuit 6008 determines the set mode in accordance with the master clock signal K, the row address strobe signal RAS, the column address strobe signal CAS and the data transfer designation signal DTD, and generates a signal DWT indicating the DRAM write transfer mode, a signal DRT indicating the DRAM -Read transfer mode indicates, etc. If the DWT1 mode and the DWT2 mode are set, the signals DWT and DRT are both generated. The DRAM driver circuit generates depending on the signals DWT and DRT 6009 the necessary signals, that is, the DRAM preamplifier enable signal DTAE, the DRAM read transfer enable signal DRTE, the DRAM write transfer enable signal DWTE and the DRAM write data enable signal DWDE. The DRAM driver circuit 6009 also drives the row and column selection of the DRAM field (namely, it increases the potential of the selected word line, drives the DRAM sense amplifier, etc.).

The mask register setting signal / MRS, which in Fig. 125 is set in the command register setting cycle in the command register. The inverted mask activation signal / M, which in Fig. 129 is shown, is applied by the mask activation connections N0 to N3 during data writing.

Embodiment 3

[Connection arrangement and definition of the signals)

Fig. 130 shows the connection arrangement of the CDRAM according to the third embodiment. As in Fig. 130 is shown, the CDRAM is housed in a 70 port, 400 mil TSOP (Type II) package. The housing has a connection distance of 0.65mm and a housing length of 23.49mm. The signal input / output can be carried out with an LVTTL periphery. The LVTTL level is lower than the ordinary TTL level. The CDRAM can be connected directly to a TTL compatible device. The CDRAM can be connected directly to an external data processing unit, such as a CPU. More specifically, the CDRAM has a controller for determining a cache hit / miss, as will be described later.

The master clock signal TLQ is the port with the number 27 fed. The CDRAM takes over the external signals synchronously to the master clock signal CLK and the clock frequencies of the internal processes are determined by the master clock signal. The connections with the numbers 11 . 13 . 14 . 16 . 19 . 21 . 22 . 24 . 47 . 49 . 50 . 52 . 55 . 57 . 58 and 60 are used from data input / output connections DQ0 to DQ15. For example, the CDRAM has a dynamic memory field with a memory capacity of 2 ²⁰ words * 16 bits and a static RAM with a 2 ¹⁰ words * 16 bit structure.

The address signal bits A0 to A21 are the connections with the numbers 2 to 5 . 37 to 45 and 61 to 69 fed. The address signal bits A0 to A21 include a memory address and a bank address for determining the SRAM field or DRAM field. If the memory system is formed using a plurality of CDRAMs, the memory system can be divided into a maximum of four banks. If it has a 1-bank structure, the address signal bits A0 to A19 are used as the memory address, and the address signal bits A20 and A21 are not used.

If the number of banks is 2k, the address signal bits A0 to A7 and A9 to A20 are used as the memory address while the address sig nalbit A8 is used as the bank address. In this case the address signal bit A21 is not used. If the number of banks is 4, the address signal bits A0 to A7 and A10 to A21 are used as the memory address, and the address signals A8 and A9 are used as the bank address.

The byte activation signals BE0 # and BE1 # become the connections with the numbers 28 and 29 fed. The byte enable signal BE0 # controls the least significant bytes (DQO to DQ7) and the byte enable signal BE1 # controls the more significant bytes (DQ8 to DQ15) when data writing is performed. When reading data, the byte activation signals BE0 # and BE1 # are ignored and all 16 bits of connections DQ0 to DQ15 are driven.

The port with the number 6 becomes an address status signal ADS # fed. The address status signal ADS # corresponds to the chip activation signal E # of the first embodiment. This signal ADS # is in the active state (at the "L" level in the following embodiment) with the rising edge of the master clock signal CLK external control signal and addresses taken over, and the CDRAM occurs in the data transfer cycle to transfer of data between the SRAM field and the DRAM field.

A memory / IO signal M / IO # that the connection with fed to number 8 the read / write signal W / R #, which is connected to the Number 9 is applied, and the data / code signal D / C # that the Connection with added to number 7 will set the type of operation according to their combinations firmly. These signals M / IO #, D / C # and W / R # are adopted when the address status signal ADS # is active.

• (i) M / IO # is D / C # is W / R # is 0 (equal to "L") No reaction and wait for the next address cycle.
• (ii) M / IO # is D / C # is 0 and W / R # is 1 (is "H") In this case, too, there is no response and wait for the next address cycle.
• (iii) M / IO # is W / R # is 0 and D / C # is 1 in this Fa11 reads the contents of the command register (to the data input / output ports).
• (iv) M / IO # is 0 and D / C # is W / R # is 1 In this In this case, predetermined values are written into the command register and a certain mode of operation is determined.
• (v) M / IO # is 1 and D / C # is W / R # is 0 in this case a code, such as an instruction, is read from memory.
• (vi) M / IO # equals W / R # equals 1 and D / C # equals 0 in this If there is no reaction, the cycle returns to the address cycle returns to the address cycle Ca back to wait for an access request.
• (vii) M / IO # equals D / C # equals 1 and W / R # equals 0 in this In this case, data are read from the memory.
• (viii) M / IO # equals D / C # equals W / R # equals 1 in this case data is written to memory.

The signal ADCl / CME # is sent to the Connection with number 32. The CME # signal is an instruction register enable signal. If the command register read command or the command register write command supplied will and this signal in the next Cycle is activated, reading or writing the content executed in the command register. When the command register read command or the command register write command is supplied, is the command register activation signal more specifically CME # on "H" and it will be active in the next cycle State "L" shifted. The signal ADC1 is an address control signal and provide a bank address.

An end of block signal (burst load signal) BLAST # is connecting with number 31. This end of block signal BLAST # gives the last of the data transfer cycles the CPU. Because there is that at Read or write data from or to memory and when writing data the last value is transferred to the command register. Will the signal BLAST # activated, is the next Cycle the address cycle Ta to the next Address details to wait.

The connection with the number 30 becomes a data hold / sleep signal DH # / SB # supplied. In the data cycle Td, the data management cycle Tdw or the data holding cycle Tdh (the cycles become later the signal DH # / SB # is used as the data hold signal DH # and controls the output buffer. When the data hold signal DH # is activated CDRAM enters the data hold cycle Tdh and holds the output data until the end of the clock signal cycle.

This signal becomes in the address cycle Ta used as sleep signal SP # and controls the sleep mode. Remains the sleep signal SP # for With 32 clock signal cycles continuously active, the CDRAM enters a sleep cycle Ts a. In the sleep cycle Ts, the sleep signal SP # becomes asynchronous Treated signal that is not synchronized with the clock signal.

The connection with the number 34 is supplied with the reset signal RST #. The reset signal RST # resets the CDRAM. During the reset process, the CDRAM (i) sets the values in all instruction registers to default values, (ii) the DRAM field initializes, and (iii) resets the valid bit of the tag memory. The reset signal RST # is adopted asynchronously to the master clock signal CLK. If the signals DS # and SB # are active, the reset signal RST # is ignored. A signal ADCO / REF # is fed to the connection with the number 33. The refresh signal REF # indicates the self-refresh cycle. The signal REF # is an input signal or an output signal (the structure will be described in detail later). The command register determines whether the signal REF # is used as an output signal or as an input signal established. If the refresh signal REF # is set as an input signal, this signal is sampled on the rising edge of the master clock signal CLK and the self-refresh mode begins with the next clock signal cycle. If the refresh signal REF # is set as an output signal, the signal REF # is controlled by an internal refresh timer and is output in synchronism with the master clock signal CLK. The refresh signal REF # in this output state controls other CDRAMs in the memory system whose refresh signal REF # is set as an input signal. Therefore, the CDRAM memory system can perform the refresh in synchronism with a CDRAM formed therein, and thus a self-refresh can be carried out during normal operation, as will be described later.

The signal ADC0 gives the bank address on. The signal ADC0 is together with the address control signal ADC1, the above is sampled when the signal ADS # is activated.

The signals listed above represent all input signals to the CDRAM (except when the refresh signal REF # is put in the output state is). The CDRAM has a controller formed therein and comprises an output signal to the state of the internal operation of an external unit tell.

The block ready signal BRDY is connected to the No. 26 issued. The block completion signal BRDY # indicates that in the CDRAM the data transfer cycle has been completed and that the CDRAM can be addressed.

A signal LNE # / KEN # is from the connection with the Number 10 submitted. The cache activation signal KEN # indicates that in CDRAM a data transfer cycle accomplished and data can be buffered in the CPU. More accurate it is said that the external CPU the addressed data in an internal Can store cache. When reading data in an area should be the one for a cache is not available (the CDRAM has an area that is not used as a cache and an area that can be used as a cache how later ), at least one waiting cycle is necessary in order to to deactivate this signal.

An activation signal for one local memory LME # indicates that the CDRAM has been selected is. This activation signal is used as a hit signal / or as a bus direction control signal used.

[Internal structure]

Fig. 131 Fig. 12 is a block diagram schematically illustrating the internal structure of the CDRAM according to the third embodiment of the present invention. As in Fig. 131 has a CDRAM 7000 an external control unit 3100 on that in Fig. 111 is shown. More specifically, the CDRAM points 7000 a DRAM field 7001 , an SRAM field 7002 , a bidirectional data transmission circuit (DTB) 7003 for transferring data between the DRAM field 7001 and the SRAM field 7002 , an address buffer / processing circuit 7004 which takes external address signal bits A0 to A21 and processes them to generate internal address signals, a row address buffer 7006 which receives the internal address signal bits A8 to A19 from the address buffer / processing circuit 7004, a line decoder 7008 that the from the row address buffer 7006 Output addresses decoded to one line in the DRAM field 7001 to select a column address buffer 7030 which receives address signal bits A0 through A7 from address buffer / processing circuit 7004 to generate internal column addresses, a latch circuit 7032 to lock the internal column address signals from the column address buffer 7030 and a column decoder 7034 which is the address signals from the latch circuit 7032 decoded to a corresponding column block in the DRAM field 7001 to put it in a selected state.

The CDRAM 7000 also has a tag memory (DG) 7036 for storing the addresses of data contained in the SRAM field 7002 are stored, that is, the tag address, a determination circuit 7038 for comparing the address signal bits A10 to A19 from the address buffer / processing circuit 7004 with the tag address of the tag memory 7036 to determine a cache hit / miss, a determination circuit 7020 to compare the internal row address from the row address buffer 7006 is latched, with address signal bits A8 through A19 from address buffer / processing circuit 7004 to determine a page hit / miss, a return address latch circuit 7024 to save the tag address from the tag memory 7036 in the case of a cache miss, and a DRAM control and cache / refresh control section 7026 for performing various necessary control operations depending on the page hit / miss and cache hit / miss indication by various external control signals and the determination circuitry for generating external control signals LME # / KEN # and BRDY # on.

The DRAM control and cache / refresh control section 7026 controls the driving of the DRAM array 7001, the driving of the SRAM array 7002 , the transmission process of the bidirectional transmission circuit (DTB) 7003 and the process of changing the latch data of the latch circuits 7008 and 7032 , In the event of a cache miss and a page hit, this is done in the latch circuit 7032 interlocked address changed to address by the column address buffer 7030 is fed. In the event of a cache miss and ei A page miss is the one in the latch circuits 7008 and 7032 held address changed. The one in the latch circuit 7008 latched address is changed to the return address at that time by the return address latch 7024 is created (for the purpose of writing back). Similarly, those in the latch circuit 7032 latched data replaced by the address signal by the return address latch circuit 7024 is locked (when writing back). The line decoder 7008 has the function of locking the created address. Consequently is in the DRAM field 7001 one line always in the selected state, which causes the sense amplifier of the DRAM field 7001 can be used as a quasi-page and also enables a page note transmission. Because the latch circuit 7032 in the page note transfer, the data transfer can be performed by selecting the DRAM column block, and a fast write-back operation can also be performed.

Although it has not been described in detail in connection with the above terminal arrangement, there are supply voltage terminals VccQ and ground potential terminals VssQ for the supply potential Vcc and the ground potential Vss, which are used only by the data input / output section in the central region of the chip. In Fig. 131 are supply voltage connections VccQ ( 0 to 3 ) and ground potential connections VssQ ( 0 to 3 ) between the data connections and the supply voltage Vcc and the ground potential Vss, which are supplied to the other circuit sections.

The DRAM control and cache / refresh control section 7026 samples external control signals with the rising edge of the master clock signal CLK and performs the necessary operation control according to the combination of these signal states. It also performs the necessary data transfer process and the change of latch addresses in accordance with the cache hit signal and the page hit signal from the detection circuits 7038 and 7020 out.

Because a tag memory 7036 is formed for storing the tag address in the CDRAM, and the circuits for determining a cache hit / miss and page hit / miss are formed internally, a memory system with a desired bank structure can be easily created. The hit / miss operation can be carried out at high speed.

[Command types]

As described above, the CDRAM takes various external control signals with the rising edge of the master clock signal CLK (samples them) and carries out the necessary operation according to the states of the external control signals. These external control signals are all applied by an external data processing unit, such as a CPU. Therefore, the DRAM control cache refresh control section shown in Fig. 131 has 7026 a function for decoding instructions supplied from the external CPU and for controlling the necessary operations.

Fig. 132 and 133 show various commands and the states of the external control signals at this time. In the Fig. 132 and 133 the reference symbol "V" indicates the state "valid", the reference symbol "X" the state "unimportant", the reference symbol "L" the "logic low level" and the reference symbol "H" the "logic high level". Furthermore, the reference symbols "Hi-Z" denote the "high impedance state", "DIS" the "deactivation state" and "INA" the "activation state". In the command register read mode CNRR and command register switch mode CNRW, in the data input / output section DQ, the data input / output ports DQ0 to DQ7 are used, and the other data input / output ports DQ8 to DQ15 are set in the high impedance state. At the input / output terminal DQ, the reference symbol "RD" indicates the read data, while the reference symbol "WD" indicates the write data.

Also referred to as a shadow RAM an area called the shadow table available for example to form an address conversion table for conversion virtual memory addresses into real memory addresses. So that can a virtual address space can be easily created.

The following are different operations described.

[Read mode (block mode, Cache mode)]

The read command (block, cache) is set when the N / IO # and D / C # signals are set to "H" and the W / R # signal is set to "L" when the address status signal ADS # drops. As in Fig. 134 is shown, the output data DOUT are stabilized in this operating mode and successively output synchronously with the rise of the master clock signal CLK from the next clock signal cycle. When the BLAST # signal drops to "L", indicating the completion of the block read mode, the data input / output terminal DQ is placed in the high output impedance state from the next clock signal cycle (when the next cycle is an address cycle). In this state, the local memory activation signal LME #, the cache activation signal KEN # and the block completion signal BRDY # are set to "L" at the time of the data output.

The in Fig. 134 Cycle Ta shown represents a preparation cycle for the data input / output cycle, and an external address becomes Si with the rising edge of the master clock gnals sampled in the data hold cycle or the next data cycle.

When the ADS # address status signal is activated and the memory / IO signal M / IO # is "H", the CDRAM occurs in the data cycle Td. This leads in this data cycle Td CDRAM a data input / output from. When the CDRAM in the data cycle Td occurs, keeps the CDRAM maintains this state until the block complete signal BLAST # is activated. If the signal BLAST # is fed, in the next Cycle the LME # and BRDY signals to "H" and the KEN # signal to "L" set to invalid the CPU Display data.

The local memory activation signal LME # and the block ready signal BRDY # go into one state correspondingly high impedance after having once moved to "H" have been placed during they have been inactivated while the cache enable signal KEN # directly from the active state to one State changes according to high impedance. The reason for this is that the external Signal lines for the local memory activation signal LME # and the block ready signal BRDY # be dragged to "H" and because it is necessary as will be described later is the "H" level by driving a number of signal lines maintain high speed. The cache enable signal KEN # gets to a correspondingly high state at the "L" level Impedance offset. This will help determine a cache hit / miss executed at high speed. Cacheable / non-cacheable data is stored in the CPU with a delay of determined in one cycle.

Block mode means an operating mode in which successive addresses are addressed one after the other, and when an address is supplied on the memory cells with the subsequent address positions accessed one after the other.

[Read mode (block mode, non-cache-bar]

As in Fig. 135 is shown, is in this operating mode similar to the operation of the in Fig. 134 is shown, the read command in the clock signal cycle 1 created. However, because the value to be accessed by the external CPU does not exist in the cache, data is read that is transferred from the DRAM field. Therefore, in the cycle TDW, the cache enable signal KEN # rises to "H" to indicate a cache miss and to notify the external CPU that the value should not be cached. Because no valid data is being transmitted at this time, the block ready signal BRDY # also rises to "H". When the required data is all prepared, that is, from the clock cycle 3 data is provided in sequence as output. At this time, because the output data DOUT represents the value that is not in the cache area, the cache activation signal KEN # falls from the next cycle, that is, from the cycle 4 , to "L". The block ready signal BRDY # drops to "L" to indicate that valid data is output in block mode from the initial output value.

The cycle Tdw in the clock signal cycle 1 indicates a data wait cycle, which means that the controller must wait until all necessary data is available.

[Read mode (no block mode, cache-bar)]

As in Fig. 136 is shown, no data transmission (to the CPU) is carried out in block mode in this operating mode. Similar to the operating modes in the Fig. 134 and 135 are shown, an external address is adopted depending on the drop in the address status signal ADS #. In the next data cycle Td, the block completion signal BLAST # is set to "L". It is therefore shown that a data word has been addressed. The data input / output terminal DQ enters the data cycle Td in the next cycle from the address cycle Ta. In order to indicate at this point in time that the output value Dout represents a valid value, the local memory activation signal LME # and the block ready signal BRDY # both fall to "L" and because of a cache hit the cache activation signal KEN # also falls to " L ".

[Read mode (no block mode, cache-bar, data retention mode)]

As in Fig. 137 is shown, the read command is in the cycle in this operating mode 1 fed. Because the read command is applied, in the next clock signal cycle 2 valid data output (multiple hits). Because there is no block access, the BLAST # block signal falls in the cycle 2 to "L".

The data hold / sleep signal DH # / SP # is held at "L" for at least 30 T cycle periods. This defines the data hold mode, and that in the cycle 2 Output data DOUT are kept in this state. The output data is put into a state of correspondingly high impedance one clock signal cycle after the data hold / sleep signal DH # / SP # has reached the inactive state “H”.

[Read mode (no block mode, non-cache-bar)]

As in Fig. 138 is shown, the read command is in cycle in this operating mode 1 fed. At this time, because access to the non-cacheable area is being performed, memory cell data is output from the main memory, that is, the DRAM array. Therefore, it begins to cycle 2 in the data wait cycle Tdw, and the output value DQ is an invalid value. In the cycle 3 valid data DOUT are output. Because the access is in the non-block mode, the block completion signal BLAST # falls to "L" and reading of a data word is completed.

In the next cycle 4 the block completion signal BLAST # is raised to "H" and a new read command is supplied. Valid values DOUT in the cycle 6 output. Because the access is not executed in the block mode at this time, the block completion signal BLAST # is set to "L". When the respective value is accessed, the local memory activation signal LME # reaches the "L" level, and the block ready signal BRDY # is only at "L" in the cycle in which the valid data are output. Due to the non-cacheable data read process, the cache activation signal KEN # assumes the level "H" for both output values.

[Read mode (no block mode, non-cache-bar, hold mode)]

As in Fig. 139 is shown, a read command is supplied in this operating mode. In the cycle 2 the data wait cycle Tdw enters the data cycle Td, and it becomes valid data from the cycle 3 output. At this time, the block completion signal BLAST # is set to "L" and a data word is output. At the same time, by setting the data hold / sleep mode signal DH # / SP # to "L" for at least 30 T (T is a clock signal cycle), the valid data are continuously output as output values. The cache activation signal KEN # reaches the "H" level when the next clock signal cycle occurs after the valid data has been output.

[Missed reading mode (block mode, cache-bar)]

As in Fig. 140 is shown, a read command is first created. In the event of a cache miss, the valid data is not output in the next clock cycle. After a predetermined number of clock signal cycles have elapsed (which is determined by the latency and will be described later), the valid value DOUT is output. When the block termination signal BLAST # falls to "L", the output is put into the high impedance state after the output of the last output value. The cache enable signal KEN # is set to "L" to indicate that there is a cacheable value.

Miss miss reading mode (no Block mode, cache-bar)]

As in Fig. 131 is shown, valid values DOUT are output after a predetermined period of time has elapsed when a read command is issued and the access causes a cache miss. The block completion signal BLAST # assumes the address cycle Ta after a word has been output. Because a cache miss occurs again, the CDRAM enters the data wait cycle Tdw, and after a predetermined period of time, valid data is output.

Miss miss reading mode (no Block mode, cache-bar, hold mode)]

As in Fig. 142 is shown, a cacheable read command is first applied, and if a cache miss occurs, data transfer is performed. In this case, valid data is output after a predetermined period of time has passed. Because the value is cache-bar, the cache activation signal KEN # reaches the level "L" with the transition from the data wait cycle Tdw to the data cycle Td. The block ready signal BRDY # only reaches level "L" when valid data is output. If the signal DH # / SP # is held at "L" for a predetermined time period of a maximum of 30 T, the CDRAM enters the data hold mode, so that the valid data is held. If the signal DH # / SP # is raised to "H", the output value in the next clock signal cycle is brought into a state of correspondingly high output impedance.

[Write mode (block mode)]

as in Fig. 143 is shown, the address status signal ADS # is set to "L" in the address cycle Ta, and the signals M / IO #, T / C # and W / R # are set to "H", so that the data write mode is set. It is not important here whether the data write process is cache-bar or non-cache-bar. In both cases, the data is written into the SRAM field or the data transmission circuit, and therefore the valid data DIN is accepted at the same time and written successfully. The cache enable signal KEN # reaches the "L" level, which indicates that the cache data is successfully written in the CPU. If the block termination signal BLAST # reaches the "L" level, the high impedance state is set after the local memory activation signal LME # and the block ready signal BRDY # both rise to "H" with the rise of the next master clock signal CLK. The cache activation signal KEN # is set in a state corresponding to high impedance starting from the state "L". As shown in this figure, data. from the address ADD in the cycle 1 is fed, successively written to neighboring addresses.

[Write mode (no block mode)]

As in Fig. 144 is shown in the cycle 1 a write command is supplied. Because it is not a block mode, the block completion signal BLAST # drops to "L" when the valid data is accepted in the next clock cycle. As a result, the local memory activation signal LME # and the block ready signal BRDY # both rise to "H", and together with the cache activation signal KEN # they are brought into a state of correspondingly high impedance in the next clock signal cycle.

[Miss-write mode (Block mode)]

As in Fig. 145 is shown, a write command is first created. However, due to the cache miss, the data write process does not begin until the data of the memory cell of the requested address is cached.

After the end of this waiting period the data is written one after the other. In this case, the time the start of data writing is determined by the latency that later is described.

If the block complete signal BLAST # has reached level "L", the block write process has been completed.

[Miss-write mode (no block mode)]

As in Fig. 146 is shown, a write command is applied in cycle 1, that is to say in the address cycle Ta. In the event of a cache miss, after a predetermined period of time has elapsed (in the second clock signal cycle in Fig. 146 ) the required memory cell has been set to the selected state, which enables data writing. When the valid value is written, the external control signals LME #, KEN # and BRDY # reach the level "L".

[Initialization when switching on]

as in Fig. 147 is shown, the reset signal RST # reaches the level "L" when switched on. In Fig. 147 An operating sequence for setting the CDRAM into the operating state based on the sleep cycle Ts is shown as an example. The sleep cycle Ts represents an operation cycle in which the operation of each circuit except the internal memory cell refresh circuit of the internal voltage generating circuit is stopped. This allows the power consumption to be reduced. The internal master clock signal is not generated and the input signals are not accepted, that is, the input signals are not sampled.

Then there is an initialization cycle Ti executed. In this initialization cycle, the reset signal RST # is set to Active state "L" set, and the signal DH # / SP # is set to "H" set. By holding the signal DH # / SP # at the inactive level "H" for at least The initialization is carried out in the CDRAM for 15 T periods. In This initialization process becomes the values of the command registers described above initialized, the DRAM is initialized and those held in the bidirectional transmission circuit Data is also initialized. The first access is not allowed up to at least 100T periods from the beginning of the initialization cycle Ti have passed. This ensures that the internal Return circuits to the initial state.

[CPU reset (CDRAM will not reset)]

As in Fig. 148 is shown, the reset signal RST # is kept at the active state "L" at the time of the CPU reset if an initialization is carried out with a reset of the CPU and without a reset of the CDRAM. In this state, the signal DH # / SP # is kept at "L" in order to reliably avoid initialization. When the reset of the CPU is released, the reset signal RST # rises to "H". Then the signal DH # / SP # is raised to the inactive level "H".

At this point is in the initialization cycle Ti, that is, if the default CPU is released, switching of the signal DH # / SP # blocked, this means, it is impossible, set this signal to "H" once, and then this signal to decrease to "L" when the reset signal RST # increases to "H". This will initialize the CDRAM prevented. The operation when leaving sleep mode is for this identical.

[Setting the sleep mode]

As in Fig. 149 is shown, the reset signal RST # and the refresh signal REF # are both set to "H" and the data hold / sleep mode signal DH # / SP # to "L" to set the sleep mode. If the signal DH # / SP # is held at "L" for at least 32 T periods, the CDRAM enters the sleep mode. In this state, no internal operation is carried out and only the self-refresh operation is active.

[Return from sleep mode]

In order to exit the sleep mode, the reset signal RST # and the refresh signal REF # are both set to "L" and the signal DH # / SP # which is at "L" is raised to "H", as in FIG Fig. 150 is shown. Switching the signal DH # / SP # when rising is blocked. This prevents the CDRAM from being initialized. The first access is not allowed until at least 15 T periods have passed since the signals DH # / SP #, RST # and REF # were all set to "H" in order to safely set the internal circuits into an operating state.

[Command register read / write mode]

The operating mode for response of the command register an "instruction register index set" instruction OMIS, an "instruction register read" instruction CMRR for reading data from the command register and a "command register write" command CMR for writing data to the command register. The command index serves to identify the majority of the command registers formed. The reading / writing of the command register will be done later along with the structure and the operation of the command register are described in detail.

Whether the data or an index is accessed is determined by the in Fig. 151 shown address bit A0 fixed. The address status signal ADS # and the signal M / IO # are both set to "L". The signal W / R # determines whether data reading or data writing is to be carried out. If the register index is to be set, the signal W / R # can be "H" or "L".

In the next cycle, the instruction register enable signal CNE # set to "L". As a result, access to the command register executed. After the command register activation signal CME has been set to the active state "L", a Data write / read into and out of the command register.

Fig. 152 shows the state transition of the different cycles in a table. The cycle Tc1 represents an instruction cycle 1 there, which is set when the address status signal ADS # is activated and the signal M / IO is at "L". After this cycle Tc1, the command register activation signal CME # is monitored. As a result of this monitoring, the CDRAM enters the Tc2 cycle when the CME # signal is activated. If the signal CME # is inactive at this point in time, the CDRAM returns to the address cycle Ta.

The second command cycle Tc2 after the first command cycle Tc1 described above. In This cycle is a write or read in or out of Command register performed. At this time, the command to be addressed is from the command register index setting command fixed. To set the command register index used an address. The signal conditions for the respective state transitions are as follows.

• A: (transition from the address cycle Ta to data cycle Td): This transition is realized when the ADS # signal is in the active state Signal M / IO # is "H", the device is in the selected state, the reset signal RST # is inactive and the block ready signal BRDY # is in the active state.
• B: This state shows a transition from the address cycle Ta for data waiting cycle Tdw. It is executed when the ADS # signal in is active state, the signal M / IO # is "H", the device in the selected State is, the reset signal RST # is inactive and the signal BRDY # is inactive Condition is.
• C: This state transition shows the transition from Data wait cycle Tdw for data cycle Td. It runs when the signal DH # in the inactive state, the reset signal RST # in the inactive State and the BRDY # signal is in the active state.
• D: This state transition repeats the data cycle Td. This state is realized when the data hold signal DH # in the inactive state, the block completion signal BLAST # in the inactive state, the reset signal RST # in the inactive State and the block ready signal BRDY # is in the active state.
• E: The transition from data cycle Td to data wait cycle Tdw is executed if the signal DH # in the inactive state, the block termination signal BLAST # in the inactive state, the reset signal RST # is in the inactive state and the signal BRDY # is in the inactive state.
• Q: The continuation of the data waiting cycle Tdw is realized when the signals DH #, RST # and BRDY # are all in the inactive state are located.
• G: The return from the data cycle Td to the address cycle Ta is executed if the signals DH # and RST # are both inactive and the block complete signal BLAST # reached the active state.
• H: The transition from data cycle Tdw to data hold cycle Tdh is executed if the data hold signal DH # is activated and the reset signal RST # is inactive.
• I: The transition from data hold cycle Tdh to data cycle Td is executed if the signals DH #, BLAST # and RST # are all inactive and the block ready signal BRDY # is in the active state.
• J: The transition from the data hold cycle Tdh to the data hold cycle Tdw is executed when the signals DH #, BLAST #, RST # and BRDY # all in the inactive state are.
• K: The transition from data hold cycle Tdh to address cycle Ta is executed if the signals DH #, RST # are both inactive and the block completion signal BLAST # is activated.
• L: The transition from the address cycle Ta becomes the first command cycle Tcl by adjusting the address status signal ADS # to the active state, setting the memory / IO signal M / IO # to "L" and by setting the reset signal RST # to performed inactive state.
• M: The transition from the first command cycle Tcl to the second command cycle Tc2 is made by setting the Command register activation signal CME # to the active state and realized by setting the reset signal RST # to the inactive state.
• N: The transition from the first command cycle Tcl to the address cycle Ta by deactivation of the signals CME #, RST # executed.
• O: The transition from the second command cycle Tc2 to the address cycle Ta is executed if the reset signal RST # is put into the inactive state.
• P: The address cycle Ta is maintained when the address status signal ADS # and that Reset signal RST # both are put in the inactive state.
• Q: The transition from different cycles to the initialization cycle Ti is through Setting the reset signal RST # implemented on the active state.
• R: The transition from the initialization cycle Ti to the address cycle Ta is by setting of the reset signal RST # implemented in the inactive state.
• S: The transition from the address cycle Ta for the sleep cycle Ts is realized when the sleep mode signal SP # activated and the reset signal RST # is deactivated. At this point, the signal SP # must be for at least 32 T clock signal periods are kept in the active state.
• T: The sleep cycle Ts is maintained when the sleep mode signal SP # is in the active state. The sleep mode signal SP # becomes asynchronous sampled to the clock signal.
• U: The return from sleep cycle Ts to address cycle Ta is realized when the sleep mode signal SP # is deactivated. When exiting sleep mode to allow access, are at least 15 T periods from the time when the sleep mode signal SP # is disabled, required.

[Command Register]

The Fig. 153A and 153B show truth values of control signals for performing reading / writing of data of the command register and the operations of the respective cycles in a table.

As in Fig. 153A is shown, the command register access cycle is implemented using the signals M / IO #, D / C #, w / R # and CME # and the address signal bit A0. This is shown in detail by the states of the respective control signals in the signal diagram Fig. 151 , When the command register is addressed, the signal D / C # is set to "1" and the signal M / IO # is set to "L". If the command register activation signal CME # is set to "L", the signal which was applied in the previous clock signal cycle is accepted and the specified process is carried out. If the address signal bit A0 is 0, the command register index setting cycle CMIS is set. If the address signal bit A0 is 1 and the write / read signal W / R # is at 0, the command register read cycle CMRR is set. If the address signal A0 is 1 and the write / read signal W / R # is "1", the command register write cycle CMRW is set.

Is the command register activation signal CME # equal to "1" the command register does not work at all.

As in 153B an instruction register index setting cycle CMIS and the instruction register write cycle CMRW are sequentially executed when data is to be written into the instruction register, that is, when a predetermined mode is to be set. A command register is selected by the command register index setting cycle CMIS from the command register indices 00H to 1CH according to the value at the input / output terminals DQ0 to DQ7. The indices 00H to 1CH that follow the command register are given in hexadecimal notation.

In the command register write cycle CMRW becomes a value supplied to the data input / output terminals DQ0 to DQ7 to the selected register index written. By repeating the above process, you can a data writing for any required command registers are executed.

If stored in the command register Data to be read is the command register index setting cycle CMIS and the instruction register read cycle CMRR executed. consequently are the saved. Data of the selected command register index read. When all the required contents of the command register are read the process described above is repeated.

[Command register index 00H]

As in Fig. 154 is shown, the command register with index 00H has a width of 8 bits. Bit 7 is used to set the input terminal or the output terminal of the self-refresh control terminal REF #, which will be described later. If the bit 7 set to 0, the REF # connector works as a signal input connector. is bit 7 is 1, the REF # connector is used as the signal output connector. Is this bit 7 equal to "1", the state of the REF # connector is controlled by a built-in refresh timer. That is, when the REF # terminal acts as an output terminal, a refresh request signal is generated by the internal refresh timer.

bit 6 is used to set the cache operation on a write hit. This is because the bit sets whether or not to write back on a write hit.

bit 5 is used to specify the cache operation in the event of a write miss, namely whether an assignment should be carried out or not.

The bits 3 and 4 are used to adjust the Refresh interval used. The refresh interval is set to an appropriate value according to the frequency of the master clock signal and the operating mode (sleep mode, etc.).

bit 2 is used to set the bus size. The bus size is used to set a shadow RAM address, which will be described later. A 32-bit bus and 64-bit bus are prepared for the bus size.

The bits 0 and 1 are used to set the number of memory banks. The addressing architecture changes according to the number of memory banks.

[Index 01H]

Fig. 155 shows the structure of the command register with the Indes 01H. In the following description, it is assumed that each instruction register is 8 bits wide. The bits 5 to 7 are used to set the frequency of the master clock signal. 33 MHz, 40 MHz, 50 MHz and 66 MHz are available as frequencies.

The bits 2 to 4 are used to set the number of waiting cycles. You set the waiting time until valid data is output in the access cycle. If there is an operation without a waiting cycle, data is output in the next cycle, in the access cycle. The bits 2 . 3 and 4 set the wait state for the block cycle, the write cycle or the read cycle. The bits 0 and 1 set the block length and block type. 4 is prepared as standard for the block length. The block type includes an interleave type, in which various data are alternately created, and a sequential type, in which the same processing device accesses. The gear type is used when an image processing device and the CPU in the image processing system access alternately. That will be described later.

[Indices 02 to 03H]

The structure of the command registers with the indices 02 to 03H is in Fig. 156 shown. The command registers with the indices 02H and 03H are used to set the non-cacheable area. The non-cacheable area means a DRAM field area for which the data of the DRAM field are not stored as a cache in the SRAM field, but for which the CPU directly addresses the DRAM field.

bit 7 The command register with index 02H is used to determine whether the CPU address range (000000 to 0C7FFh) should be cacheable or non-cacheable. The bits 4 to 6 of the command register with index 02H are used to determine the size of the non-cacheable memory block. 64 kbit, 128 kbit, 256 kbit and 512 kbit are available as block sizes.

The bits 0 to 3 of the command register with index 02H and the data bits 0 to 7 of the command register with index 03H are used to determine the start address of the non-cacheable memory block. Here is according to the bus size, which is determined by bit 2 of the index 002 to Fig. 154 is set, the CDRAM address architecture changed. The start address of the non-cacheable memory block, which is set by the command register with the indices 02 and 03H, corresponds to the command register address with respect to bits 2 of the command register has been written with index 00H.

[Indices 04H to 05H]

The structure of the command registers with the indices 04H to 05H is in Fig. 157 shown. The command registers of indices 04H and 05H are used to set the non-cacheable area. In the instruction registers with the indexes 02H and 03H, the non-cacheable area is defined by the address signal bits A21 to A14 (or A20 to A13). This area can be set as desired in the CPU address area 0C000 to 0C7FFFh. The command registers with the indices 04H and 05H which are in Fig. 157 are shown can set the non-cacheable area in any area. The bits 4 to 6 of the command register with index 04H are used to determine the size of the non-cacheable memory block. The bits 0 to 3 of the command register with index 04H and the bits 0 to 7 of index 05H are used to determine the start address of the non-cacheable memory block. In this case the non-cacheable area defined by the indices 04H and 05H is determined by the address signal bits A14 to A21 (or A13 to A20).

[Indices 06H to 07H]

The structure of the indices 06H to 07H is in Fig. 158 shown. As in Fig. 158 is shown, the command registers with the indices 06H and 07H are used to determine the test mode. The supported test mode has a refresh counter test and a test mode in which all address areas are configured as a non-cacheable area. The refresh counter test is a test mode in which it is determined whether or not the counter for generating the refresh address for the refresh operation of the DRAM array operates normally. The address area is made entirely non-cacheable in order to check whether the memory cells of the DRAM field are defective or not. The command register with index 07H is reserved for future functional expansions.

[Indices 10H to 1CH]

The command registers with the indices 10H to 1CH are used to control the read / write of the shadow RAM area, as in FIGS Fig. 159 and 160 is shown. The CPU address area 0DC0h to 0FFFFh is prepared as a shadow RAM area. The CPU address area is assigned to the respective index. The activation / deactivation of reading / writing of the respective CPU address area is set by the values of bits W and R in the command register index.

[Read / write latency]

The number of clock cycles required to read or write a valid value after access, that is, into the latency is in Fig. 161 shown. The frequency command is through the bits 5 to 7 of the register with index 01H set above with reference to Fig. 155 has been described. The length of the latency is set according to the respective clock frequency. In read mode, data is output in the clock signal cycle after the access if there is a hit, and then data is output in succession in each clock signal cycle. In the event of a cache miss, a predetermined number of clock cycles are required before valid data is output.

"Not overwritten" and "overwritten" indicates the deleted or set state of the write indicator bit. This is because it indicates whether the data stored in the SRAM cache is different from the data of the corresponding memory cell of the DRAM field. If the write indicator bit is set and thereby indicates the overwritten state, the content of the SRAM field must be written back to the DRAM field. In parallel to the external access, data transmission between the SRAM field and the DRAM field is carried out in the CDRAM (see page mode transmission and write-back mode, which have been described above). The number of clock cycles that are necessary for this data transmission are in Fig. 161 in brackets (). If misses continue to occur, it is necessary to wait for the previous miss access to complete.

The latency is in write mode always the same, independently whether access to a cache hit or cache miss leads, because the data goes directly to the data transmission gate to be written.

[Setting / holding time]

In CDRAM, data input / output is synchronized to the master clock signal CLK executed. Therefore the setting time and the hold time of the input signal with respect to the rising edge of the master clock signal CLK designed.

Fig. 162 shows the response time and the hold time of the input signals. Fig. 163 shows the stabilized states of the output signal. The output signal becomes valid after a lapse of a predetermined period from the rise of the master clock signal CLK, and becomes invalid after a predetermined period of time from the rise of the master clock signal CLK.

[Output circuit]

As in Fig. 164 a plurality of CDRAMs are generally used to form a memory system. As in Fig. 164 is shown, CDRAMs CR00 to CR33 are arranged in 4 rows * 4 columns that form 4 banks. Bank # 0 is formed by CDRAMs CR00 to CR03, bank # 1 by CDRAMs CR10 to CR13, bank # 2 by CDRAMs CR20 to CR23 and bank # 3 by CDRAMs CR30 to CR33. Each of the CDRAMs has an 8-bit bus 7501 (7501 generally denotes the reference numerals 7501a to 7501b ).

The 8 bit data buses 7501a to 7501d are connected to 32-bit 7501e data bus. The CDRAMs are each with a control bus 7500 connected (7500 generally denotes the reference numerals 7500a to 7500e ). The control buses 7500a to 7500D are with a main control bus 7500e connected.

As described above the CDRAM itself generates control signals. That means it creates the block ready signal BRDY #, the cache activation signal KEN #, the local memory activation signal LME # and the refresh determination signal REF # if this is configured as an output signal. The sections to output these signals are structured so that they are appropriate OR logic connected to the signal lines. The block ready signal BRDY # is used as an example. This signal becomes active on "L", if the CPU above it is informed that a valid Value is output so that the CPU and the applied signal processed and the applied data in a cache section in the CPU according to the active state ("L" level) of the cache enable signal KEN # stores.

If a CMOS inverter is used in the output section, a transistor switches through in such a case, so that a current constantly flows through the signal line. This increases the power consumption of the CDRAM. If a 3-state buffer with a clocked inverter is used for the signal output section, clock signal control becomes necessary. This leads to a complicated circuit structure and an enlargement of the device. Therefore, a structure with an open drain, like the one in Fig. 165A is shown as an output section for generating control signals ver applies. The signal line is raised to the supply potential Vcc by a pull-up resistor R. As in Fig. 165A is shown, output transistors OTA and OTB are parallel to each other with a signal line 9010 connected. The output transistors OTA and OTB switch depending on the output determination signals? 1 and? 2 in the CDRAMs CRA and CRB, respectively, around the signal line 9010 to unload. On the signal line 9010 a pull-up resistor R is formed. It is assumed that the CDRAMs CRA and CRB do not output signals at the same time. The transistors OTA and OTB do not switch through simultaneously. These stores belong to different banks of the structure that are in Fig. 164 is shown. Referring to the signal diagram in Fig. 165B the operation of the in Fig. 165A described circuit described.

It is assumed that a read request is supplied to the CDRAM CRA and valid data is output. In this case, signal? 1 first rises to "H". This makes the output transistor OTA conductive. As a result, the potential becomes SigA of the signal line 9010 , which was raised to the supply potential Vcc by the pull-up resistor R, quickly discharged via the output transistor OTA. When the data output is completed, the signal? 1 drops to "L". Consequently, the signal line 9010 raised by the pull-up resistor R to the level of the supply potential Vcc. The value of the resistor R is relatively high and its power consumption is therefore low.

Then the CDRAM CRB is accessed and the signal? rises to "H". As a result, the output transistor OTB turns on to the signal line 9010 to discharge to the ground potential level. After the completion of the predetermined processing, the signal ϕ2 falls to "L" and the signal line 9010 is raised again to the level of the supply potential Vcc.

By using the output section described above can the necessary signals, for example the signal BRDY #, by a simple circuit structure can be transferred to the CPU.

Although the signal line 9010 is charged by the pull-up resistor R, there is a stray capacitance C on the signal line 9010 , Therefore, a time period determined by the RC time constant is necessary until the signal SigA on the signal line 9010 increases from "L" to "H".

The CPU determines whether the next access is possible and whether valid data corresponds to the state of the SigA signal on the signal line 9010 issue. If the rise of the signal SigA on the signal line 9010 is moderate and if it is determined with the rising edge of the master clock signal CLK that it is at "L", data can possibly be accepted incorrectly. In this case, because the CPU determines whether the next access is possible according to the state of the signal SigA, it becomes impossible to address the memory in another bank by switching the banks. This prevents quick operation. If the value of the pull-up resistor R is made smaller, the signal line can 9010 be loaded at high speed. In this case, however, a large current flows through the signal line 9010 , This increases the power consumption of the storage system.

Fig. 166 shows a CDRAM structure with an improved output section according to the present invention. As in Fig. 166 is shown, the output section of the CDRAM has an output transistor 9011 for discharging the signal line 9010 and a transistor 9012 for charging the signal line 9010 for a predetermined period of time. The output section of the CDRAM CRA has an output transistor 9011a , which is made conductive in accordance with a signal ϕ1D, and a p-channel MOS transistor 9012A which is made conductive depending on a signal? 1L. The signal ϕ1L is held at "L" for a predetermined period of time and only in response to the fall of the signal ϕ1B. The CDRAM CRB similarly has an output transistor 9011b , which is made conductive depending on a signal? 2D, for discharging the signal line 9010 and a p-channel MOS transistor 9012b for charging the signal line 9010 for a predetermined period of time and only in response to a signal ϕ2L. The master clock signal CLK is sent to the CDRAMs CRA and CRB via a signal line 9009 fed. Referring to the signal diagram in Fig. 167 is the operation of the output section after Fig. 166 described.

First, it is assumed that the CDRAM CRA is put into the operating state and executes predetermined processing. At this time, predetermined processing (indicated in the figure as?) Is executed from the rising edge of the master clock signal CLK, the signal? 1D rises to "H" after the lapse of a predetermined period of time around the signal line 9010 to discharge to the ground potential level. After a predetermined period of time has elapsed (the length of this period of time changes depending on the data holding time, the block length and similar sizes), the signal? 1D then falls to "L", using the rising edge of the master clock signal CLK as a trigger. The drop in the signal? 1D is used as a trigger and the signal? 1L drops to "L" and is held for a predetermined period of time. As a result, the transistor turns off 9011a and the transistor 9012A switches through. So that the signal line 9010 about the transistor 9012A loaded at high speed. After a predetermined period of time has elapsed, the transistor turns on 9012A blocked.

At this point, the end changes not for a predetermined period of time from the rising edge of the master clock signal CLK, as in Fig. 162 is shown. More specifically, the step-down transistor switches 9011 from the locked state to the on state after a predetermined period of time has passed since the rising edge of the master clock signal CLK. The transistor therefore switches during this time 9011b not through even if the transistor 9012A is switched through. Therefore, there is no signal collision, no current flows from the transistor 9012A to the transistor 9011b and the signal line 9010 is loaded at high speed. Because the? 1L signal is generated using the? 1D signal as a trigger, the transistors switch 9011a and 9012A not through at the same time. Therefore, no forward current flows in the CDRAM CRA. because the transistor 9012A after a predetermined period of time has passed to the locked state, its power consumption is quite low.

According to the state of the signal Sig on the signal line 9010 the CDRAM CRB is then addressed by the external CPU, the transistor 9011b switches through in a similar manner and discharges the signal line 9010 , Then the transistor 9011b blocked. Then the signal? 2L is generated, the transistor 9012b switches through and discharges the signal line 9012 for a predetermined period of time at high speed.

Each CDRAM operates using the rising edge of the master clock signal as a trigger. Parameters of various signals are set with the rising edge of the master clock signal CLK as a reference. Therefore, the period of time when the pull-up transistors 9012A and 9012b kept in the conductive state, can be set exactly.

Fig. 168 shows a circuit structure for generating control signals ϕD and ϕL. As in Fig. 168 the control signal generating system has a processing circuit 9020 to generate a set signal after the lapse of a predetermined period of time in accordance with an applied command, a set / reset flip-flop 9021 which is dependent on the set signal from the processing circuit 9020 is set and reset with the rising edge of the clock signal CLK, an inverter circuit 9022 to which the output signal of the flip-flop 9021 inverted and a single pulse generation circuit 9023 by the output signal from the inverter circuit 9022 is dependent on generating a single pulse with a predetermined pulse width. The control signal ϕD is generated by the set / reset flip-flop 9021. And this signal switches the transistor 9011 to unload the output line. The single pulse? L from the single pulse generation circuit 9023 switches the transistor 9012 to load the output signal line.

At the in Fig. 168 shown, the signal? D is reset with the rising edge of the master clock signal CLK. Depending on the transition of the signal ϕD to the reset state, a single pulse? L is generated for a predetermined period of time. The processing circuit 9020 changes its operation according to the signal from the Fig. 166 output section shown is delivered. The set / reset flip-flop 9021 is reset with every rising edge of the master clock signal CLK. However, a circuit structure can also be used in which a reset signal is generated by another processing circuit after completion of processing depending on the rising edge of the master clock signal CLK. The adjustability of the adjust / reset flip-flop 9021 is greater than the resilience.

Fig. 169 shows another structure for the control signal generation system. As in Fig. 169 is shown, the control signal generation system has a flipfop 9025 on that at its setting input a signal from the inverter circuit 9022 , in the Fig. 168 is shown, and receives the master clock signal CLK at its reset input. The flip-flop 9025 is reset depending on the drop in the master clock signal CLK. The control signal? L is generated at its complementary output / Q. Referring to the signal diagram in Fig. 170 will the operation of the in Fig. 169 described circuit described.

If the signal? D is at "H", the output signal of the inverter circuit is located 9022 to "L". In this state, the signal ϕL is held in the reset state. In other words, it is kept at a "H" level. If the signal? D falls to "L", the output signal of the inverter circuit rises 9022 on and the flip-flop 9025 is set. Depending on this, the signal? L is set and reaches the level "L". When the master clock signal CLK drops, the flip-flop 9025 then reset and the signal? L rises to "H". As a flip-flop 9025 an edge-triggered flip-flop can be used, which is set as a function of the rise in the setting input signal and is reset as a function of the fall of the master clock signal. The resilience of the flip-flop 9025 can be greater than the adjustability. If so, the flip-flop 9025 as a function of the drop in the master clock signal CLK even if the signal supplied to its setting input S is in the active state "H".

If the output signal of the circuit, which is in the form of an OR logic with the signal line 9010 is connected, as described above, represents a signal which is output in synchronism with the master clock signal CLK, the signal line can be charged in accordance with the clock signal for synchronization. Therefore, the signal line can be raised to the pull-up potential with high speed and low power consumption the.

With the structure described above, the signal line 9010 raised to the level of the supply potential Vcc. The signal line 9010 can be pulled down to the ground potential level. In this case, the structure is such that a signal line connected in the form of an OR logic is charged to the supply potential by the driver transistor of the output stage, and the signal line is discharged to the ground potential level via the driver transistor in the output stage. The polarity of the transistors in the example described above are namely changed.

[Procedure for setting of test modes]

As in Fig. 158 a test can be performed using the command registers with the indices 06h and 07h by setting the test mode. For example, the refresh counter can be checked and the DRAM field can be addressed directly. In this case, there are several test modes that the user does not need. For example, a reference voltage (Vcc / 2) is generally applied to a cell plate, which is an electrode of a storage capacitor of a dynamic memory cell, and it is necessary to ensure the breakdown voltage of the storage capacitor by measuring its breakdown property by varying the cell plate voltage. In this case, an acceleration test is carried out with the cell plate voltage raised above the generally applied reference voltage (Vcc / 2). It is desirable that the device not enter such a test mode even if a user operates the memory at a wrong timing. A structure for such an operation is described.

Fig. 171 shows a method for setting a test mode in the CDRAM according to the present invention. As in Fig. 171 is shown, the test mode is set when the command register setting cycle (Tcl or Tc2) is repeated twice in succession. At this time, the command register activation signal CME # is set to the inactive state "H" in the second cycle. In this case, the command register is not accessed. The address applied at this time, that is, the address bit supplied at the time of setting the test mode, is used as a signal for setting the test mode. This makes it possible to set a desired test mode among a plurality of test modes and it becomes possible to activate only a specific test mode.

To exit the test mode, the same command register setting command created again. In this case too, the first command cycle Tcl or the second command cycle Tc2 executed. The CME # signal goes up "H" held.

As described above the test mode is only used according to the signal timing, and a special test mode is set according to the address key (one Combination of the predetermined address signal bits) called. Therefore can be compared to a method of entering a test mode by applying a signal that is above the supply voltage Vcc is raised, the test mode easier and with higher reliability be called. Furthermore, the test mode can be done in a simple manner be used after the device has been formed on a chip is.

Because the test mode corresponds to that Command Register setting can be taken other desired Commands than that for the command register setting process during the test operation be so that the CDRAM a desired one Circuit operation.

In a semiconductor memory device with an instruction register, the method for entering the test mode can use the instruction register setting cycle. For example, in CDRAM, which is the truth table of signals as in 94 is shown, the command register can be set using the signals RAS #, CAS # and DTD #. In this case, the command for setting the command register is applied with the rising edge of the external clock signal K, as in Fig. 172 is shown. In other words, the external control signals ext.CS #, ext.RAS #, ext.CAS # and ext.DTD # are also set to "L". This command is applied sequentially for two clock signal cycles. The test mode is taken by the command register setting cycle of the second clock signal, and the test mode executed at this time is set by the external address signal ext.Ad. Instead of a structure in which a test mode is selected from a plurality of test modes, a structure can be used in which only a specific test mode is activated in accordance with a predetermined address key. A structure can be used in which the remaining test modes are executed in accordance with the test mode set in the command register.

According to the specification of the Product is generally entering other commands for one to one locked three cycles when a command register setting command is supplied. Because the test mode was taken at such an operating time who is locked according to the specification can be a incorrect call of the test, which indicates incorrect operation of the CDRAMs are caused to be prevented.

Fig. 173 shows an example of the structure of a test mode setting circuit. As in Fig. 173 is shown, the test mode setting circuit has a command detection circuit 9030 receiving an external control signal for detecting the input of a command register setting command, a counter 9032 for counting the detection signals from the loading fail detection circuit 9030 , an address key detection circuit 9035 by a double counter signal from the counter 9032 is dependent, for comparing the address signal supplied at that time with a predetermined key to detect a match / mismatch, and a test circuit 9034 which is dependent on a match detection signal from the address key detection circuit 9035 is activated to set a desired test mode. The test circuit 9034 is dependent on a triple counter signal from the counter 9034 disabled. The command register 9033 becomes dependent on a command detection signal from the command detection circuit 9030 activated. Access to the command register 9033 is permitted in this structure according to the third embodiment only when the command activation signal CME # is activated.

If the command detection signal is applied twice in successive clock cycles, the counter generates 9032 an increment signal and passes it to the address key detection circuit 9035 to. After counting up, it deactivates the test circuit 9034 depending on the next command detection signal applied. The test circuit 9034 enables a predetermined test operation depending on the key detection signal from the address key detection circuit 9035 , For example, when a cell plate test is to be performed, a reference voltage source connected to the cell plate, that is, a node connected to the reference potential generation circuit that generates the potential Vcc / 2, is connected to an external supply terminal. This enables the cell plate voltage to be raised in a simple manner. A structure can be used in which the connection of the node for the test is switched to an internal voltage generation circuit and the internal voltage generation circuit under the control of the test circuit 9034 generates a predetermined voltage for the test. The test circuit 9034 may include such an internal voltage generation circuit for the test.

Fig. 174 shows another structure for the test mode setting circuit. As in Fig. 174 a counter is shown 9042 the command register setting command from a command detection circuit 9040 and count their number. A test mode setting circuit 9044 is dependent on a two-time increment signal from the counter 9042 activates and sets a predetermined test mode according to the address supplied at that time. More specifically, the test mode setting circuit has 9044 a function for decoding the address signal and setting a predetermined test mode. The circuit structure of the test circuit 9042 is designed so that the test mode setting circuit 9044 specified test mode is implemented. The test circuit 9044 is similar to that in Fig. 173 shown test circuit 9034 ,

In the in the Fig. 173 and 174 The structure shown can use a structure in which a test mode determination signal of a predetermined instruction register 9033 corresponding to twice the count-up signals from the counter 9032 read and fed to the test circuit. In this case, the command register 9033 a predetermined test mode is set.

Fig. 175 shows an example of the structure of the in the Fig. 173 and 174 shown counter. As in Fig. 175 is shown, the counter points 9032 (9042) a single pulse generation circuit 9050 that from the command detection signal? is dependent on the command detection circuit for generating a pulse with a predetermined pulse width ( 2 Clock signal cycles), a counter circuit 9054 for counting the command detection signal ϕ, a set / reset flip-flop 9056, which has at its setting input S twice the count-up signal C2 from the counter circuit 9054 and at its reset input R three times the count-up signal C3 from the counter circuit 9054 receives, and a gate circuit 9052 that have an output signal from the flip-flop 9056 and an output signal from the single pulse generation circuit 9050 receives on.

For example, the gate circuit 9052 an OR gate. Is the output signal from the gate circuit 9052 the counter circuit becomes "H" 9054 put in the operating state. Referring to the signal diagram of Fig. 176, the operation of the in Fig. 175 counter circuit shown.

If a command register setting command is supplied with the rise of the master clock signal CLK, the command detection signal ϕ rises. The single pulse generating circuit generates depending on the command detection signal ϕ 9050 a single pulse and the output signal of the gate 9052 rises to "H". Consequently, the counter circuit 9054 activates and counts the command detection signal? The count value thus reaches the value 1.

The output signal of the single pulse generation circuit 9052 has a pulse width of 2 clock signal periods (that is in Fig. 176 indicated by the dashed line). Does a command detection signal subsequently occur during this period? supplied, generates the counter circuit 9054 twice the count-up signal C2. This will make the flip-flop 9056 set and its output signal Q rises to "H". Depending on the rise of the output signal Q of the flip-flop 9056 becomes the pulse generation of the single pulse generation circuit 9050 blocked. The output signal of the single pulse generation circuit 9050 namely drops to "L". The gate 9052 continuously outputs a signal with level "H" corresponding to the output signal Q of the flip-flop 9056 out. So that the counter circuit 9054 kept in the active state.

Will the third command detection signal? applied, generates the single pulse generation circuit 9050 no impulse. Depending on the third command detection signal? raises the counter circuit 9054 the double count-up signal C3 to "H".

As a result, the output signal Q of the flip-flop falls 9056 to "L" and the counter circuit 9054 is reset. Depending on the drop in the Q output signal of the flip-flop 9056 becomes the single pulse generation circuit 9050 reactivated.

Will the command detection signal? not applied twice in succession, the output signal of the single pulse generation circuit falls 9050 depending on the second clock signal from the first application of the command detection signal? as indicated by the dashed line in Fig. 176 is shown. In response to this, the count value of the counter circuit 9054 reset. With this, a successive double supply of the command detection signal, that is, the successive double application of the command register setting command can be reliably detected.

[Refresh controller]

As in Fig. 154 is shown, the seventh bit of the command register with index OOh can set the REF # connection as an input connection or an output connection. The input / output structure of the REF # connector will now be described.

It is assumed that the CDRAM is arranged in n banks, as in Fig. 177 is shown. As in Fig. 177 shown bank 0 to bank n each a 4-byte word structure with byte 0 to byte 3 on, and in each bank the REF # terminals of the CDRAMs are interconnected. In each bank, the REF # terminal of a CDRAM is configured as an output terminal and the REF # terminals of the remaining CDRAMs are set as input terminals. As a result, the refresh can be carried out under the control of a CDRAM in each bank.

Fig. 178 Figure 12 shows a structure for the CDRAM refresh section. For easier understanding of the refreshing process, in Fig. 178 described an example in which memory access is determined by the row address strobe signal ext.RAS #, which is a commonly used external control signal in a standard DRAM. The CDRAM according to the third embodiment has a controller and performs the sampling of external control signals in accordance with an address status signal ADS #. The internal RAS signal is generated as required according to the result of the scan. The structure will be briefly described later. The following simply shows a state in the RAS buffer 6030 generates an internal RAS signal? RAS # corresponding to the external row address strobe signal ext.RAS # as a memory access signal (this applies to the first to third embodiments). When the internal row address strobe signal (internal RAS signal) φRAS # is at the active level "L", the DRAM field is active.

As in Fig. 178 is shown, the refresh control system has a master circuit 8010 to generate a refresh request, a master / slave switch 8040 for transmitting the refresh request from the master circuit 8010 to a refresh port 8000 corresponding to a master / slave setting indicator M / S # from the command register, and a slave circuit 8020 by the refresh request to the port 8000 is dependent on performing the refresh operation on.

The master circuit 8010 has a self-refresh timer 8012 for generating the refresh request? REFs # at predetermined time intervals and a first arbitration means 8014 to arbitrate the refresh request? REFs # from the self-refresh timer 8012 and the internal RAS signal ϕRAS # from the RAS buffer 8030 on. When the internal RAS signal? RAS # is active and a refresh request? REFs # is asserted, the first arbitrator gives 8014 a refresh request? REF # if the internal RAS signal? RAS is deactivated. At this time, as will be described in detail later, the first arbitration means 8014 a refresh request ϕREFs # in synchronism with the master clock signal CLK.

The master / slave switch 8040 transmits the refresh request from the first arbitrator 8014 to the refresh port 8000 when the master / slave indicator M / S # indicates the master status. If the slave state is set, the changeover switch 8040 placed in a state of high output impedance. This blocks the transmission of the output signal from the first arbitration means 8014 ,

The slave circuit 8020 has a second arbitration means 8022 to arbitrate the refresh request from the port 8000 is supplied (from outside or from the same chip), and a precharge completion signal ϕPR and a self-refresh control circuit 8024 by the refresh request ϕREFa # from the arbitration means 8022 is dependent on performing the necessary control for the refresh. The self-refresh control circuit 8024 has an address counter for specifying the line to be refreshed. When the refresh request ϕREFa # is created, it performs the row selection process of the DRAM and a read amplifier activation using the refresh address from the refresh address counter as the row address. The self-refresh tax circuit 8024 generates the internal RAS ϕRASa #, which has a predetermined width (the width includes at least the time required to complete the row selection and the detection process in the DRAM field), depending on the refresh request signal ϕREFa #. The RAS buffer 8030 performs a logic operation with the external row address strobe signal ext.RAS # and the internal RAS signal? RASa # and generates the internal RAS signal ϕRAS #.

The second arbitration tool 8022 transmits the refresh request internally or from the off chip through the port 8000 to the self-refresh control circuit when the precharge completion signal ϕPR of the RAS buffer 8030 is activated, indicating that the precharging of the DRAM field has been completed. The second arbitration tool 8022 delivers a mask signal ϕMask # to the RAS buffer 8030 simultaneously with the transmission of the refresh request? REFa # to the self-refresh control circuit 8024 ,

In accordance with that of the second arbitration means 8022 generated mask signal ϕMask # masks the RAS buffer 8030 the external row address scanning signal ext.RAS # and blocks external access. Referring to the signal diagrams of Fig. 179 and 180 now becomes the operation of the master circuit 8010 and the slave circuit 8020 , in the Fig. 178 are described.

With reference to Fig. 179 will first operate the master circuit 8010 described. If the internal RAS signal ϕRAS # is in the active state "L", the DRAM field is accessed from the outside and the DRAM field is active. Used by the self-refresh timer 8012 If a refresh request ϕREFs # is created, the first arbitration means is transmitted 8014 the refresh request ϕREFs # in synchronism with the master clock signal CLK when the signal? RAS # is at the inactive level "H". The switch 8040 has been put into the operating state in accordance with the indicator M / S #, so that it is that of the first arbitration means 8014 supplied refresh request for connection 8000 and to the slave circuit 8020 transfers. This removes the refresh request for the other CDRAM from the connector 8000 issued.

At this point, the first arbitration tool delivers 8014 an external refresh request depending on the (synchronous to) increase in the external master clock signal ext.CLK. With the rise of the master clock signal CLK, which is used as a trigger, the external refresh request REF # returns to the inactive state and the first arbitration means 8014 disables the internal refresh request? REFs #. This will become the self-refresh timer 8012 reset again and starts a new counting process. With this structure, the refresh request can always be generated synchronously with the external master clock signal CLK. In the master chip (the chip, in the indicator M / S # the connection 8000 as the output connection) leads the second arbitration means 8022 arbitration of the refresh request from the switch 8040 out. The second arbitration tool 8020 generates a mask signal? Mask # depending on the refresh request from the switch 8040 is created. The first arbitration means 8014 generates the refresh request in synchronization with the master clock signal CLK after the internal RAS signal? RAS # is deactivated. The mask signal? Mask # therefore has the function of masking a newly created access request.

When a refresh request is submitted, the second arbitrator generates 8022 a refresh request ϕREFa # when the precharge completion signal ϕPR from the RAS buffer 8030 deactivated and precharging completed. The self-refresh control circuit 8024 executes the refresh operation according to the refresh request ϕREFa #. More specifically, the count from the address counter is selected by a multiplexer and applied to the DRAM row decoder so that the DRAM row decoder is activated and the sense amplifier is driven. The internal RAS signal? RAS that is generated at this time has a predetermined width. Namely, the self-refresh control circuit generates a single pulse signal having a predetermined width as an internal RAS signal ϕRASa # depending on the refresh request ϕREFa #.

Is a predetermined period of time elapsed, the refreshing process is complete and that Mask signal? Mask # is deactivated. That allows the assumption an external access.

In the slave chip (a chip in which the connector 8000 is set as the input port by the indicator M / S #), the refresh operation is carried out in accordance with the refresh request which is external to the port 8000 is created. Therefore, the refresh operation from the slave chip can be performed synchronously and in accordance with the refresh request from the master chip. At this time, because the refresh request is supplied in synchronism with the master clock signal, a plurality of CDRAMs are subjected to the refresh operation at the same time without being affected by timing fluctuations.

Because first and second arbitration circuits 80 14 and 8022, the refresh operation can be performed with an arbitrary activation of the DRAM field. The self-refresh can thus be carried out even in the normal operating mode. The structure of various sections is described below.

Fig. 181 shows a circuit structure for generating the precharge completion signal? PR #. This Circuit is in the RAS buffer 8030 included the in Fig. 178 is shown. As in Fig. 181 is shown, the precharge completion signal generation system has a delay circuit 9060 which delays the rise of the internal RAS signal? RAS # by a predetermined period of time. At the in Fig. 181 As shown in the structure shown, the precharge completion signal? PR rises to "H" after a predetermined period of time from the rise of the internal. RAS signal ϕRAS # to the inactive level "H". This indicates the completion of the subpoena, as in Fig. 182 is shown. The precharge completion signal ϕPR is set to the inactive level "L" at approximately the same time that the internal RAS signal ϕRAS # changes to the active state "L".

Fig. 183 Fig. 10 shows another structure of the precharge completion signal generation system. As in Fig. 183 is shown is a counter 9064 activated depending on the rise of the internal RAS signal ϕRAS #, the master clock signal CLK counts for a predetermined period of time and raises the precharge completion signal? PR to the active state "H", which indicates the completion of the precharge. In this case, the precharge completion signal can be generated in the form of a single pulse. A signal obtained by AND operation of the internal RAS signal “RAS # and the precharge completion signal“ PR can be generated as the precharge completion determination signal. When this AND operation is to be used, the precharge completion signal? PR is kept inactive "L" when the internal RAS signal "RAS # is at the active level" L ", that is, when the DRAM array is in the active state.

That of the rise delay circuit 9060 and the counter 9064 Delay time delivered can be as long as the RAS precharge time.

Fig. 184 shows an example of the structure of the first arbitration means of FIG Fig. 178 , As in Fig. 184 is shown, the first arbitration means 8014 an inverter circuit 8068 for inverting the refresh request (ext.REF #) from the changeover switch 8040, a setting / resetting flip-flop 8062 which has the output signal from the inverter circuit at its setting input S. 8061 and at its reset input RD the output signal of the inverter circuit 8068 receives a 2-input AND circuit 8063 which outputs Q from the flip-flop 8062 and receives the internal RAS signal ϕRAS #, a latch circuit 8064 which is the output signal from the AND circuit 8063 depending on the rise of the master clock signal CLK takes over and locked, and a flip-flop 8066 , the output signal Q of the latch circuit at its setting input S. 8064 receives on. The external refresh request ext.REF # is from the flip-flop 8066 generated (it is via the switch 8040 to the refresh port 8000 ) Is applied.

The flip-flop 8066 is from an output signal of the gate circuit 8067 , the master clock signal CLK at its true input and the output signal / Q of the flip-flop at its false input 8066 receives, reset. More specifically, the flip-flop 8066 resets with the rise of the next clock signal CLK after the external refresh request ext.REF # is generated (when it reaches the "L" level), and the external refresh request ext.REF # is reset. The operation will now be briefly described.

If the refresh request? REFs # from the self-refresh timer 8012 (please refer 178 ) is created, the flip-flop 8062 set (at this time, the external refresh request ext.REF # is still at the inactive level "H"). If the internal RAS signal ϕRAS # reaches the inactive state "H", the gate circuit leaves 8063 the output signal Q of the flip-flop 8062 by. The latch circuit 8064 accepts the output signal from the gate circuit 8063 synchronized with the rise of the master clock signal CLK and locks it. Therefore, the refresh request is taken over by the latch circuit 8064 locked in synchronism with the rise of the next clock signal CLK when the internal RAS signal? RAS # is deactivated. The output signal Q of the latch circuit thus rises 8064 to "H", the flip-flop 8066 is set and its output signal / Q reaches the level "L". This creates the refresh request. If the refresh request ext.REF # assumes the active state "L", the gate circuit sets 8067 the flip-flop 8066 depending on the rise of the next master clock signal CLK. So that the output signal / Q of the flip-flop 8066 reset from "L" to "H".

With the structure described above, the external refresh request is only generated when the internal RAS signal? RAS # is inactive. If the external refresh request ext.REF # reaches the active state, the flip-flop 8062 through the inverter circuit 8068 reset, and the output signal Q of the flip-flop 8062 drops to "L". Then the output signal Q reaches the latch circuit 8064 the level "L". The flip-flop 8066 is not set at all and held in the reset state.

The refresh request? REFs # issued by the self-refresh timer 8012 is a single pulse with a predetermined width. A reset is not necessary.

Fig. 185 shows an example of the structure of the second arbitration means shown in Fig. 178 is shown. As in Fig. 185 is shown, the second arbitration means 8022 a latch circuit 8070 which takes over and latches the external refresh request ext.REF # in synchronism with the rise of the master clock signal CLK, and a flip-flop 8072 , depending on the complementary output signal / Q of the latch circuit 8070 is set to. The mask signal φMask # is from the complementary output / Q of the flip-flop 8072 issued.

The second arbitration tool 8022 also has a gate circuit 8074 which receives the mask signal? Mask # and the precharge completion signal ϕPR, and a counter 8076 which is dependent on the refresh request signal? REFa # from the gate circuit 8074 is activated to count up a predetermined number of the master clock signal CLK. After a predetermined number of master clock signals CLK have been counted, the counter sets 8076 the flip-flop 8072 back. The counter 8076 sets the time period of the refresh process. The operation will now be briefly described.

If the external refresh request ext.REF # drops to the active state "L", the latch circuit takes over 8070 the external refresh request ext.REF # synchronized with the rise of the clock signal CLK and locks it. As a result, the complementary output signal / Q of the latch circuit rises 8070 to "H". This will make the flip-flop 8072 set. The masking signal ϕMask # thus changes from the complementary output signal / q of the flip-flop 8072 to the active state "L".

After the mask signal? Mask # has reached the active state "L", the gate circuit generates 8074 a refresh request ϕREFa # when the precharge completion signal ϕPR has reached the active state "H". The counter 8076 counts a predetermined number of clock signals CLK depending on the refresh request REFa #. After counting the predetermined number, he sets the flip-flop 8072 back. As a result, the mask signal ϕMask # is reset to "H", the output signal of the gate circuit 8074 also reaches level "H" and the refresh request? REFa # assumes the inactive state.

At the in Fig. 185 As shown in the structure shown, the refresh request? REFa # generated by the first arbitration means is at the active level "L" during the refresh operation. A structure can be used in which it is generated in the form of a single pulse. More specifically, a structure can be used in which a single pulse generation circuit in the output portion of the gate circuit 8074 is formed, and the counter 8076 is activated depending on the output signal of the single pulse generation circuit. Although this is not shown, the count of the counter 8076 reset to the initial value when a predetermined count has been reached.

Fig. 186 shows an example of the special structure of the RAS buffer and the refresh control circuit. As in Fig. 186 is shown, the RAS buffer 8030 a gate circuit 8080 , which receives the external RAS signal ext.RAS # and the mask signal ϕMask #, and a NOR circuit 8082 , the output signal of the gate circuit at the first input 8080 receives on. The NOR circuit 8082 receives at its second input the internal RAS signal? RASa # from the refresh control circuit 8024 is produced.

The refresh control circuit 8024 has a refresh detection circuit 8090 for detecting a refresh in response to the refresh request signal ϕREFa #, a pulse generation circuit 8094 from the refresh detection signal? REFa # from the refresh detection circuit 8090 is dependent, for generating a pulse signal? RASa # with a predetermined width (refresh operating time), an address counter 8092 that from the rise (deactivation) of the internal RAS signal φRASa # from the pulse generating circuit 8094 is dependent on increasing the count by 1, and a multiplexer 8096 to select either the count value of the address counter 8092 or an external address in accordance with the internal RAS signal φRASa # from the pulse generating circuit 8094 on.

The output signal of the multiplexer 8096 is fed to the DRAM row decoder. At this point, the output of the multiplexer 8096 to the DRAM row decoder via an address buffer. That from the gate circuit 8082 External RAS signal generated is sent to a DRAM RAS driver circuit 8096 created. The DRAM-RAS driver circuit 8096 performs an activation of the DRAM row decoder, a selection of the word lines, an activation of the sense amplifiers, etc.

At the in Fig. 186 shown structure, it is not necessary to use the refresh detection circuit and the pulse generation circuit 8094 to be formed when the refresh request signal ϕREFa # is kept active during the refresh operation time, as in Fig. 185 is shown. The refresh detection circuit 8090 and the pulse generation circuit 8094 are necessary if the refresh request signal? REFa # is generated in the form of a single pulse.

The address counter 8092 may be structured such that the count value is put into an output activation state by the refresh detection circuit 8090 in response to the refresh detection signal RA.

In the Fig. 186 The circuit structure shown is formed in the DRAM control and cache / refresh control section 7026 in the CDRAM according to the third embodiment, which is shown in FIG Fig. 131 is shown. The tax section 7026 does not receive the external RAS signal ext.RAS # directly. In this case, a structure can be used in which a circuit for detecting the return to the address cycle Ta in the control section 7026 and the arbitration is dependent on the detection of the return to the address cycle Ta instead of the external RAS # signal is performed.

The in Fig. 131 shown control section 7026 shows the structure of in Fig. 111 external control device shown 3100 on. Therefore, because access to the DRAM array is being performed, an access control signal from the controller 3108 (please refer Fig. 111 ) to the DRAM field. Therefore, the structure is such that that of this control section 7026 applied internal RAS signal instead of the external control signal of the gate circuit 8080 of Fig. 186 is fed.

In the structures after the first and second embodiment, where different operations according to the combination of the states of external signals when rising of the clock signal become an active command detection signal instead of the external address scanning signal ext.RAS # fed. Differentiate the external control signals used at this time yourself in dependence from the control signals used in the respective embodiments to be used.

In the third embodiment a structure can be used in which the address status signal ADS # that is masked at the time of the refresh request is used instead of the RAS # signal.

Fig. 187 Fig. 4 shows another structure of the refresh control section. As has already been described, the CDRAM enters sleep mode when the signal SP # is held in the active state "L" for a predetermined period or longer. The internal circuit does not work in sleep mode. The CPU therefore does not access it. In this state, self-refresh is carried out. The structure for this process is described below.

As in Fig. 187 is shown, the refresh control section has inverter circuits 8702 and 8704 that invert the sleep determination signal Sleep, an AND circuit 8700 which the output signal from the inverter circuit 8702 and receives the master-slave indicator M / S #, a gate circuit 8708 which the output signal from the inverter circuit 8704 and one from either the refresh port 8000 or the selector switch 8040 received refresh request signal receives a gate circuit 8706 that the refresh request? REF # from the first arbitrator 8014 and receives the sleep mode determination signal Sleep, and a gate circuit 8710 which are the output signals of the gate circuits 8706 and 8708 receives on. From the gate circuit 8710 a refresh request signal becomes the second arbitration means 8020 transfer.

The gate circuit 8706 outputs an active signal when the refresh request? REF # is in the active state "L" and the sleep mode determination signal Sleep is at the active level "H". The gate circuit 8708 provides a signal at "H" when the external refresh request signal ext.REF # is in the active state and that from the inverter circuit 8704 supplied signal reaches the inactive level "H". The gate circuit 8710 outputs a signal at "L" when one of the output signals from the gate circuits 8706 and 8708 reached level "H". The gate circuit 8700 controls the output state of the switch 8040 , The operation is briefly described below.

In the normal operating mode, the sleep mode determination signal Sleep is inactive and the gate circuit 8700 passes the indicator M / S #. Hence the switch 8040 corresponding to the M / S # indicator into a state of high output impedance or a state in which the refresh request? REF # is passed. Because the sleep mode determination signal Sleep is at the inactive level "L", the output signal is the gate circuit 8706 fixed to "L". The gate circuit 8708 receives the signal with level "H" at its positive input via the inverter circuit 8704 and works as a buffer. In this case, therefore, the gate circuit 8710 according to the refresh request ext.REF # from the port 8000 or the switch 8410 a refresh request is generated and the second arbitration means 8020 carries out the arbitration necessary for the refresh. Therefore, a refresh is carried out in both master and slave mode.

When the sleep mode is set, the sleep mode determination signal Sleep rises to "H", the output signal of the gate circuit 8700 reaches level "L" and the switch 8040 regardless of whether the chip is a master or slave, it is placed in the high output impedance state. Because the gate circuit 8708 at its positive input a signal with level "L" via the inverter circuit 8704 receives, its output is fixed to "L". The gate circuit 8706 operates as a buffer in response to the sleep mode determination signal Sleep, which is "H", and generates the refresh request in accordance with the refresh request? REF # from the first arbitration means 8014 is produced. The logic of the gate circuit 8706 Refresh request is generated by the gate circuit 8710 inverted and as a refresh request with negative logic to the second arbitration means 8020 created.

Therefore, in sleep mode operation, the refresh is carried out in accordance with the refresh request generated by the self-refresh timer in the chip. There is no external access to a CDRAM in sleep mode. It is therefore not necessary to carry out the internal processes synchronously. At this point the connection 8000 placed in a state of high output impedance. It is not necessary to transfer another external refresh request ext.REF #, charging / discharging of this signal line can be avoided, and therefore the power consumption in the sleep mode can be reduced.

Fig. 188 shows another example of the storage system structure. In the example of the storage system described above (see Fig. 177 ), the refresh operation is carried out bank-wise. In the structure shown in Fig. 188, all refresh ports are connected to each other regardless of the banks. In this case, all of the CDRAMs CR00 to CRN4 of the memory system carry out the refresh operation synchronously. In this example as well, the same effect as in the embodiment described above can be achieved. The CDRAM has been described above. However, a structure for realizing refresh using the master / slave structure can be applied to any synchronous semiconductor memory device in which external signals are adopted in synchronism with the clock signal. The structure is not limited to the CDRAM.

[Data transmission method]

In the truth table of the control signals of the DRAM, which in 94 is shown, contain the commands for data transfer from the write data transfer gate DTBW to the DRAM field, a command DWT1 for performing a data transfer between the master register and the intermediate register of the data transfer circuit DWTB and a command DWT2 for the data transfer between the master register and locks the intermediate register. A new transfer command is created here.

Command DRT1: The command should be a data transfer between the master register and the intermediate register (hereinafter as slave register) in the write data transfer circuit simultaneously with the data transfer process from the DRAM field to the read data transfer circuit Execute DTBR.

Command DRT2: The command should be the data transfer lock between the master register and the slave register of the write data transfer circuit and a data transfer Execute from DRAM field to read data transfer circuit DTBR.

By forming those described above two DRAM read transfer commands can the quick write back and data transfer be made compatible in page mode. It will be the data transfer process using these commands.

The commands mentioned below have the same meaning as those in 94 commands shown are used.

As in Fig. 189 is shown, an active command ACT is first applied to the DRAM and a line corresponding to the CPU address is selected in the DRAM. The DRAM is then given a DRAM read transfer command 1 fed. At the same time, a buffer write transfer command BWT is applied to the SRAM. A row selection operation is performed in the DRAM field in accordance with the ACT active command, and then in accordance with the DRAM read transfer command 1 DRT1 the data block B1 of the selected row is transferred to the read data transmission circuit DTBR. The command DRTl specifies the data transfer from the slave register of the write data transfer circuit DTBW to the master register. Therefore, the SRAM data block A1, which has been transferred from the SRAM field to the slave register STW in accordance with the BWT command, is then transferred to the master register MTW. It should be noted that the data transfer between the SRAM array and the data transfer circuits DTBW and DTBR is performed by the SRAM driver section, while the data transfer between the DRAM array and the data transfer circuits DTBW and DTBR is controlled by the DRAM driver section.

To simplify the description Fig. 189 shows a state in which data from the DRAM field to the slave register STR of the read data transfer circuit DTBR are transmitted according to the command DRT1. Whether the data transfer according to this command is executed immediately depends on the frequency of the used Clock signal from (latency).

As in Fig. 190 is shown, the DRAM-NOP command DNOP (no operation) is applied and a buffer write transfer command BWT1 is supplied to the SRAM. In this cycle, the DRAM continuously executes the previous command and the DRAM data block B1 is latched to the read data transfer circuit DTBR.

Another line is selected in the SRAM, and the corresponding data block A2 becomes the slave register STW Write data transfer circuit DTBW transmitted and locked there.

As in Fig. 191 is shown, the DRAM-NOP instruction DNOP is again supplied to the DRAM and a buffer read transfer instruction BRTR is applied to the SRAM. The previous operating state is retained in the DRAM. In the SRAM, the data block B1, which is stored in the master register MTR of the read data transfer circuit DTBR, is stored in the selected line of the SRAM field. At this time, the line in which the data block A1 was previously stored is selected in the SRAM field. Data block B1 is therefore stored instead of data block A1. The necessary data, that is to say the data requested by the CPU, are output in parallel with this storage process.

Due to the sequence of operations described above, in the event of a cache miss, the data required by the CPU can be run at high speed speed to the SRAM field and read immediately, so that the access delay in the event of a cache miss can be significantly reduced. This process is used as a fast write-back mode, as described above. By selecting two data blocks A1 and A2, the block size of the cache can be doubled. This allows the cache size to be increased.

As in Fig. 192 is shown, a DRAM read transfer command in the DRAM 2 DRT2 fed and a command * applied to the SRAM. The command * can be any command except the BWT buffer write transfer command and the BRTW buffer write transfer / write command. In the DRAM, a data block B2 which exists in the same line as the data block B1 but belongs to a different data block is selected and transmitted to the read data transfer circuit DTBR. A desired operation is performed for the DRAM. However, the content of the write data transfer circuit DTBW is not changed by the command *.

As in Fig. 193 is shown, the DRAM-NOP command DNOP is supplied to the DRAM and the command * is applied to the SRAM. Therefore, the DRAM data block B2 is stored in the master register MTR in the read data transfer circuit DTBR.

As in Fig. 194 is shown, the DNOP instruction is applied to the DRAM and the buffer read transfer instruction BRT is applied to the SRAM. At this time, the line in which the data block A2 has been stored is set to the selected state in the SRAM. Corresponding to the BRT, the data block B2 which has been stored in the master register MTR of the read data transfer circuit DTBR is transferred to the SRAM field. Consequently, data blocks A1 and A2 are replaced by DRAM data blocks B1 and B2 in the SRAM field. The block size of the cache can namely be two lines (32 bits) of the SRAM.

As in Fig. 195 a precharge command PCG is supplied to the DRAM. The command * is applied to the SRAM. With the precharge command PCG, the DRAM field returns to the precharge state. As in Fig. 196 is shown, the active command ACT is then applied to the DRAM and the command * to the SRAM. The row in which the SRAM data blocks A1 and A2 are to be stored is selected in the DRAM field in accordance with the tag address. The command * is supplied to the SRAM, and data is not rewritten into the write data transfer circuit DTBW.

As in Fig. 197 is shown, the DRAM is the DRAM write transfer command 2 DWT2 fed. The command * is applied to the SRAM. The DBT2 command carries out a data transfer between the slave register STW and the master register MTW in the write data transfer circuit DTBW. As in Fig. 197 is shown, no data transfer from the master register MTW to the DRAM column is carried out in this cycle in which the command DWT2 is applied, and therefore the transfer process is shown by a dashed line.

As in Fig. 198 is shown, the DNOP command is applied to the DRAM and the * command is applied to the SRAM. Consequently, the data block A1, which has been stored in the master register MTW of the write data transfer circuit DTW, is stored in the corresponding column of the DRAM.

As in Fig. 199 is shown, then the DRAM write transfer command 1 DWT1 applied to the DRAM, and the command * fed to the SRAM. The command DTW1 represents an operating mode for transferring the data of the slave register STW of the write data transfer circuit DTBW to the DRAM field via the master register MTW. Therefore, in this example, the data block A2 is transferred to the selected line of the DRAM field. At this time, the DRAM field contains the same line as the line selected by the previous DWT2 command in the selected state, and therefore data block A2 is stored at a different location on this line in which data block A1 has been stored.

As in Fig. 200 is shown, the DRAM-NOP command DNOP is supplied in the DRAM. As a result, writing of data block A2 for the selected row and column of the DRAM is completed. At this point, the command for the SRAM can be any command (unimportant). Therefore, the precharge command PCG is supplied to the DRAM. With this precharge command, the DRAM returns to the precharge state.

Through the sequence described above of operations can the data blocks A1 and A2 of the SRAM field written back according to the page mode become. The fast write-back mode and the page mode can namely both are used.

A structure can be used at which the line corresponding to the address requested by the CPU is, in the DRAM, corresponding to a page hit / miss after the preloading is completed selected becomes.

It becomes a special operational sequence described in the event of a cache miss.

Fig. 201 Figure 12 shows a signal diagram of the operation in the event of a cache miss when the write indicator bit is set. Fig. 201 shows an operating sequence for a clock signal with 66MHz. The T1 cycle involves the occurrence of a cache miss where the address sampled as the address status signal ADS # falls does not match the tag address. Because the write indicator bit is set, the contents of the cache differ from the contents of the main memory. If a cache miss occurs, the contents of the cache must therefore be written back to main memory.

The following process is for a read Operation performed with page hits. If there is an access request and it turns out that there is a cache miss and page hit, the commands DRT1 and BWT are generated in the cycle. As a result, data transfer from the SRAM array to the write data transfer circuit is performed. Because the command DRT1 is applied, data transfer from the slave register to the master register is carried out in the write data transfer circuit. According to the command DRT1, data is transferred from the DRAM field to the read data transfer circuit.

In the cycle 5 the DRT2 and BRTR commands are executed. The data previously stored in the read data transfer circuit in accordance with the command DRT1 are transferred to the SRAM field and the data requested by the CPU are read. At this time, data is transferred from the DRAM field to the read data transfer circuit in accordance with the DRT2 command. There is no data transfer between the slave register and the master register of the write data transfer circuit. In the cycles 6 to 8th a command SR is supplied to the SRAM and data are read in succession. In the cycle 7 a precharge command is applied to the DRAM so that the DRAM field returns to the precharge state.

In the cycle 9 the BWT instruction is supplied and data is transferred from the SRAM field to the slave register of the write data transfer circuit. As a result, two data blocks are stored in the write data transfer circuit.

In the cycle 10 commands ACT and BRT are created, a row selection process is carried out in the DRAM field, while in accordance with the BRT command the cycle command corresponding to the DRT2 command 5 data block stored in the read data transfer circuit is stored in the corresponding line of the SRAM field.

In the cycle 13 the DWT2 command is executed and the data which have been stored in the master register of the write data transfer circuit are stored at the corresponding position in the selected line of the DRAM field. In the cycle 15 the DWT1 command is created, and the data stored in the slave register of the write data transfer circuit are stored at the corresponding location in the DRAM field. This completes the write back process. The DRAM field can start from cycle 16 be addressed, and in the cycle 17 a command for the DRAM field is generated.

When reading with page miss, the following operation is performed.

In response to a cache miss, the PCG and BWT instructions are issued. As a result, the DRAM array returns to the precharge state. Data is transferred from the SRAM field to the slave register of the write data transfer circuit. Then in cycle 6 the ACT command is created and a line is selected in the DRAM. In the cycle 8th the DRT1 command is created and the data of the corresponding position of the selected line of the DRAM are stored in the slave register of the read data transfer circuit via the master register. The data transfer between the registers is carried out in the write data transfer circuit.

In the cycle 10 the commands DRT2 and BRTR are created. In accordance with the BRTR command, the data which have been transmitted in accordance with the DRT command are stored in the corresponding position in the SRAM field. According to the command DRT2, data is transferred to the read data transfer circuit. At this time, no data transfer is carried out between the master register and the slave register of the write data transfer circuit. Then the command SR is supplied and data are read in succession. In the cycle 12 the precharge command PCG is created. As a result, the DRAM array returns to the precharge state.

In the cycle 14 the BWT command is created and in the cycle 15 the commands ACT and BRT are supplied. With this, lines of the DRAM field and the SRAM field are selected, and the SRAM cell data are stored in the write data transfer circuit (slave register). In accordance with the BRT command, the data corresponding to the DRT2 command of the cycle 10 have been stored in the read data transfer circuit, transferred to the position of the line which, according to the command DWT (cycle 14 ) has been selected. A line is selected in the DRAM, and in cycle 18 and the following commands DWT2 and DWTl are executed. The data that has been stored in the write data transfer circuit is successively stored.

The following operation is performed on a page miss write. First, the commands PCG and BW are supplied, and data is written in the write data transfer circuit. The DRAM field returns to the precharge state. In the cycle 6 an ACT command is created and a line is selected in the DRAM. Then in the cycle 9 command DWT1 is supplied, and the data that has been written into the write data transfer circuit is transferred to the corresponding location of the selected row of the DRAM array.

When writing with page hits the commands BW and DWT1 created. The created at this time Data is transferred to the master and slave registers of the write data transfer circuit.

Fig. 202 shows a signal diagram of the operating sequence when a clock signal with 50MHz is present. In Fig. 202 is also the operational sequence for a failure hit write and a miss read under the same conditions as in the example Fig. 201 , that is, when the write indicator bit is set. At the in Fig. 202 operating sequence shown, the DRAM-NOP period (no operation) is shorter than in the example after Fig. 201 , The order in which the commands DRT1 and DRT2 are generated differs from the signal diagram Fig. 201 , Once the BWT buffer write transfer command is asserted, the DRAM read transfer command is asserted twice. Therefore, a similar process can be realized regardless of which of the commands DRT1 and DRT2 is generated earlier. More specifically, the data transfer from the DRAM field to the read data transfer circuit is carried out together with the data transfer from the SRAM field to the write data transfer circuit when the commands DRT2 and BRT are applied.

If the commands DRT1 and BRTR are supplied, the data which have been stored in the read data transfer circuit are written to the corresponding position in the SRAM field, and the new DRAM cell data are then transmitted to the read data transfer circuit. At this time, data transfer from the slave register to the master register is carried out in the write data transfer circuit. When the BWT command is created (cycle 8th ) data is then stored in the slave register of the write data transfer circuit. Therefore, the SRAM data is stored in the write data transfer circuit, which corresponds to the BWT command in the cycles 3 and 8th be transmitted. Therefore, an operation similar to that in Fig. 201 shown can be realized.

Fig. 203 shows an operational sequence when the master clock signal has a frequency of 40MHz. The signal diagram after Fig. 203 is similar to that of Fig. 201 , Similar operation is realized except that the DRAM-NOP period (no operation) differs due to the difference in clock frequency. Fig. 204 shows an operational sequence when the master clock signal CLK has a frequency of 33MHz. In the Fig. 204 Operating sequence shown is similar to the operating sequence according to Fig. 202 , and the only difference concerns the DRAM-NOP period (no operation). The difference results from the different frequency of the master clock signal.

As described above differs the DRAM-NOP time period (no operation) depends on the frequency of the master clock signal, because the internal data transfer time determined by the latency. The length of the latency can be adjusted accordingly the frequency of the clock signal can be set.

Fig. 205 shows a truth table of the control signals for setting the DRAM read transfer command. As in Fig. 205 is shown, the signals RAS #, CAS # and DTD # are all set to "H" for the DRAM-NOP command (no operation). The signal CMd # is at "H". For the DRAM read transfer command 1 DWT1, the signals RAS # and DTD # are set to "H" and the signal CAS # to "L". For the DRAM read transfer command 2 DRT2, the signals RAS # and CAS # are set to "H" and the signal DTD # to "L". The method of generating these commands is only an example and other combinations of signal states can be used.

The write data transfer circuit DTBW and the read data transfer circuit DTBR each have similar structures to those in FIGS Fig. 125 and 127 shown on.

The control signal generation system has a structure similar to that in FIG Fig. 129 shown is similar. At the in Fig. 125 Write data transfer circuit shown is the signal DWTE for controlling the data transfer from the intermediate register 4002 , that is the slave register, to the master register 4004 activated / deactivated according to the commands DRTl and DRT2.

In the third embodiment of the CDRAM with a controller, the controller generates 7026 a signal in accordance with the external control signal, the cache hit signal and the page hit signal. This can be realized when the signals supplied to the internal DRAM driver section and the SRAM driver section are generated to satisfy signal logic similar to that shown for the first and second embodiments.

Fig. 206 shows another structure of the data transmission circuit. As in Fig. 206 is shown, the write data transfer circuit DTBW has N stages on registers # 1 to #N. In this example, registers # 1 to #N have a shift register structure and perform locking and moving for the data created. With this structure, the block size of the cache can be increased to N times. The reason is because N data blocks can be successively transferred between the DRAM field and the SRAM field according to the page mode. Data transfer in the write data transfer circuit DTBW is performed by expanding the structure of the two stages of registers described above.

At the in Fig. 206 Write data transfer circuit DTBW shown, a similar effect is achieved not only by the shift register structure, but by a register with a FIFO structure (first in / first out).

[Image Processing System]

Fig. 207 Figure 10 shows an example of the image processing system using the CDRAM according to the present invention. As in Fig. 207 is shown, the image processing system has a CPU 9500 as an external processing unit for Processing data, a CDRAM 9530 , an image display unit 9520 for displaying data on a monitor and a high-speed video interface 9510 to control access to the CDRAM for image display and access between the CPU and the CDRAM. The CPU 9500 is over a data bus 9505 with the high-speed video interface 9510 connected.

The DRAM 9530 has an SRAM area 9540 for storing video data (data of one scan line) and a DRAM area 9550 on.

The DRAM area 9550 has a video area 9560 to save video data. The data transfer is between the SRAM 9540 and the video area 9560 executed. The CPU 9500 works with an operating frequency of 33MHz. The high-speed video interface 9510 works with 66MHz and regulates the access to the CDRAM 9530 the CPU and the image display unit 9520 , By data transfer (according to the commands DRT and BRT) from the DRAM area 9550 to the SRAM area 9540 become video data from the DRAM field 9550 to the SRAM field 9540 transfer. Under the control of the high-speed video interface 9510 attacks the CPU 9500 directly to the data transmission circuit in accordance with the buffer read command BR and the buffer write command BW to the data transmission circuit which is in the CDRAM 9530 is formed. The image display unit 9520 accesses the SRAM area 9540 to. The high-speed video interface 9510 is carried out in an interleaved manner.

Fig. 208 shows schematically the working principle of the in Fig. 207 shown image processing system. In the return time of the video data (horizontal and vertical return time) there is a transfer of video data from the DRAM area 9550 to the SRAM area 9540 carried out. During this period the CPU 9500 the CDRAM 9530 do not respond. Outside of the ramp-down time, a so-called "image refresh" can be carried out on the video data from the CPU that is on the CDRAM 9530 accesses, be changed. The CDRAM 9530 Namely, it can implement an operation similar to a video RAM that includes an optional access port and a serial access port.

It becomes the control process of the high speed video interface 9510 describe.

Fig. 209 Figure 12 shows a signal diagram of the operation of the video data processing system when the CDRAM is operating in the "transparent output mode". In Fig. 209 CK33 sets the operating speed of the CPU and CK66 sets the operating speed of the high-speed video interface 9510 that the CDRAM 9530 responds to the image display unit 9520 video data is transmitted at a speed of 15.5MHz. Access to the video data is performed using the SR command. In Fig. 209 cycle T1 denotes a live access cycle and T2 denotes a CPU access cycle.

As in Fig. 209 is shown, is shown in the first cycle, a video address VIDEO0 is created in the first cycle by the command SR, and in accordance with this address, video data is output on the CDRAM bus with the rise of the next clock signal CK66. This data is transmitted through the high speed video interface 9510 to the image display unit 9520 transfer.

An access is then carried out by the CPU. At this time, the DWT and BW commands are supplied, the DRAM write transfer operation and the buffer write operation are executed, the data from the CPU is written to the data transfer circuit, and the written data is transferred to the DRAM field. Then the video access is carried out and video data VIDEO1 is removed from the SRAM field by the command SR 9540 read. In the CDRAM 9530 data transfer is carried out in accordance with the command from the CPU. In the next cycle, the DRT command is applied, data is transferred from the DRAM to the data transfer circuit, and the block read operation is carried out. The valid data are output by this block read mode. The valid data of this block read mode are output after three clock cycles have elapsed. It should be noted that access to the CDRAM 9530 is executed in accordance with the clock signal CK66 while the CPU issues an access request in accordance with the clock signal CK33. Then, video data and the CPU data are sequentially output in accordance with the BR and SR instructions.

Because the CPU and the image display unit alternately access the CDRAM of this interlocking arrangement, the CPU can perform the DRAM without interrupting access (except for the transmission period of the video data from the DRAM area 9550 to the SRAM area 9540 ). This enables data processing at high speed.

Fig. 210 Fig. 12 shows a signal diagram of the operation of the image processing system when the CDRAM outputs data in the register output mode. In the register output mode, data is output with a delay of one clock cycle, as has already been described with reference to FIG. 66. In the transparent output mode, outputs are made in the cycle that follows the access cycle. Therefore, when the register output mode is used, the next address can be created while the previous data is output as in Fig. 210 is shown. Therefore, the CPU and the image display unit can access the CDRAM alternately at the same speed. That is, the CPU data and the video data can be input / output at the same speed become.

In the transparent output mode, valid data with the rise of the next Clock signal output when an address is created. If the CPU data and video data take turns at the same speed are addressed, there is therefore a data collision. The Video data VIDEO0 and the CPU data 486-0 are now used as an example in FIG. 210. If the CDRAM works in transparent output mode and creates an address VIDEO1 will be in the next Clock cycle video data VIDEO1 output. At this time Write data 486-0 created by the CPU. Therefore, the CPU data collide with the video data. In the register output mode, the data with a delay of output a clock cycle, and therefore the data can even then be written safely and without data collision when the CPU Writes data to the CDRAM. So an image processing system, the higher one Speed works, be formed.

Fig. 211 shows a comparison of the operating speed of a standard DRAM and the CDRAM. It is assumed that data is to be written which is arranged in 16 rows * 16 columns, as in Fig. 211 (a) is shown. As in Fig. 211 (b) is shown, it is necessary with the standard DRAM to write the data one after the other by switching the signal CAS after the activation of the signal RAS. When a row of data is written, the DRAM field is precharged and the data must be rewritten according to the RAS and CAS signals.

As in Fig. 211 (c) is shown, data are written in succession in the CDRAM to the data transfer circuit in accordance with the buffer write command BW, the DRAM active command ACT is applied to the DRAM, the written data are transferred collectively to the line of the DRAM field in accordance with the command DWT, and data is written to the remaining lines executed. If the next line is to be accessed, the line selection process of the DRAM can be carried out at the same time as the data writing to the data transfer circuit in accordance with the BW command. Therefore, the RAS precharge time is not required externally at all. Thus data can be written at high speed.

In the description regarding Fig. 211 8 bits are treated as a cache block, that is, as a transfer size.

Fig. 212 shows a comparison of the data write operation when there is a page boundary in a rectangular area. The lines of the DRAM field differ at the page boundary. As in Fig. 212 (a) is shown, in this case there is a page boundary at the interface between the data DI area and the data DI area, and the data DI and data DI are stored in different DRAM word lines. As in Fig. 212 (b) is shown, in this case the data D1 are first written in the standard DRAM using the signals RAS and CAS until the page limit is reached. Then the DRAM is precharged and the remaining data D2 and D3 of the first line must be written in accordance with the signals RAS and CAS. A similar procedure must be carried out in the area of the second line. Therefore, the DRAM field must be preloaded both at the page boundary and when the rows are changed in the arrangement with 16 rows * 16 columns. Therefore, the RAS precharge time prevents high speed data processing.

As in Fig. 212 (c) is shown, after the data has been written in accordance with the buffer write command BW, data is written in the CDRAM in accordance with the commands DWT and BWTW, and in parallel the precharge command PCG of the DRAM field is applied and the data can be written in succession in accordance with the buffer write command BW. In parallel to writing data to the data transfer circuit in accordance with the buffer write command BW, a DRAM line can be selected into which the data D2 and D3 are to be written. By transferring the commands DWT and BWTW at the end of this line section, data can be written to the desired DRAM line. Therefore, when switching the rows with the arrangement with 16 rows * 16 columns, a precharge must be carried out, which requires a waiting time, but with the arrangement with 16 rows * 16 columns no RAS precharge time is necessary at the page boundary, so data can be written at high speed.

Fig. 213 Fig. 12 shows a signal diagram of the operation when data arranged in 16 rows * 16 columns is to be read from the DRAM field. It is assumed that the data groups D1 and D2, which are as in Fig. 213 (a) are arranged to be read. The data D1 and D2 are blocks that each form a transmission unit.

Fig. 213 (b) Fig. 12 shows a data reading sequence when a synchronous semiconductor memory device (SDRAM) is used. The synchronous semiconductor memory device SDRAM can read data in synchronism with the clock signal at high speed. The synchronous semiconductor memory device has a serial register in the data input / output section and enables data input / output to and from the serial register in synchronism with the clock signal. When data is read, the internally selected memory cell data is stored collectively in the serial register, and then the data is read out successively from the serial register in synchronism with the clock signal. If the number of serial registers is 8, it is necessary to store new data in the serial register every time 8 Da be read tenbits. Therefore, the signal CAS for loading data into the serial register is generated. If data are to be read from the serial register one after the other after data has been loaded into the serial register, another line can be preloaded in the DRAM field and in the selected state be transferred. Therefore, when a synchronous semiconductor memory device SDRAM is used, data can be read more or less continuously.

As in Fig. 213 (c) In CDRAM, the necessary data is transferred to the data transfer circuit according to the ACT and DRT commands, and the data is transferred from the data transfer circuit to the SRAM field according to the BRTR command, and then data can be read safely according to the SR command. In this case too, precharging and activation can be carried out in the DRAM field when data is read from the SRAM field. Therefore, data reading can be performed at the same speed as in a synchronous semiconductor memory device SDRAM.

Fig. 214 shows a signal diagram of the operation of the SDRAM and CDRAM when reading data when a page boundary exists. As in Fig. 214 (a) is shown, it is assumed that the WRAP length (data length that can be read continuously) in the synchronous semiconductor memory device (hereinafter simply referred to as SDRAM) is 8. As in Fig. 214 (b) is shown, the RAS precharge state is assumed at the page limit in the SDRAM, and the DRAM field is then reactivated. With this, data is stored in the read register (serial register formed in the data output area), then data is read one by one, and then it is necessary to read data one by one by transferring new data by switching the signal CAS. Therefore, in this case there is a significant RAS preload time and the RAS-CAS delay time at each page boundary.

As in Fig. 214 (c) In the CDRAM, even with a page boundary in the middle of the arrangement, it is possible to read data one after the other by transmitting the data to the data transfer circuit and to preload and activate the DRAM field in parallel. There is no precharge influence from the DRAM field, so the. Data can be read at a higher speed than in SDRAM.

Fig. 215 shows a signal diagram of the operation for the read-modify-write operation. As in Fig. 215 (a) is shown, it is assumed that the data are arranged in 16 rows * 16 columns and all are overwritten according to the read-modify-write mode. As in Fig. 215 (b) is shown, the read command and the write command are output in the SDRAM depending on the drop of the signal CAS. Therefore, two clock signals are required for the read command and the write command. If the read-modify-write process is to be carried out for the data of a line, there is therefore a waiting time between the write process and the execution of the read process. This prevents the data from being changed quickly.

In contrast, the data in CDRAM Writing data from the DRAM field to the SRAM field via the transfer circuit and by alternating execution reading data from the SRAM field and writing data to the transfer circuit changed become. The required data all become the write data transfer circuit written after the data is transferred to the read data transfer circuit according to the DRT command have been. Then the data in the write data transfer circuit have been written, transferred to the DRAM field in accordance with the BWT command. Therefore can the data in the DRAM field is rewritten at high speed if there is no page boundary in a line.

Fig. 216 shows a waveform diagram of the operation when data occupying a triangular area is to be written. It is assumed that the video data containing the data D1 and D2 and arranged in a triangular shape in the range of 16 rows * 16 columns should be written as in Fig. 216 (a) is shown. As in Fig. 216 (b) shown, data must be written in the SDRAM and in the DRAM at this time by switching the signals RAS and CAS according to the respective line. Therefore, there is a RAS precharge time and a RAS-CAS delay time in each line.

On the other hand, in the CDRAM, the RAS-CAS delay time can be reduced compared to the SDRAM and DRAM, because the data can be written to the data transfer circuit according to the command BW and the row selection process of the DRAM field can be carried out in parallel, as in Fig. 216 (c) is shown. However, the precharge time of the DRAM field remains. Therefore, data writing can be performed at a higher speed.

By using the CDRAM after the present invention, an image processing system as described above be implemented, the processing of data at high speed performs.

Because the present invention is structured so that the operational control of the DRAM section and the SRAM section is carried out independently of each other, and a bidirectional transfer circuit for transferring data between the SRAM array and the DRAM array can be directly accessed from the outside , as described above, a semiconductor memory device can be implemented that can be used as a cache memory in a memory system or as a video memory for graphics applications and with high performance and high operating speed works.

The essential properties Effects brought about by the present invention are as follows.

• (1) When the DRAM field is active, various DRAM column blocks in succession be formed. Therefore, it is possible to continuously create a Row of data (a page of data) through the sense amplifier in the To lock a DRAM field, a data transfer between the DRAM section and independent of that driven SRAM section using the page mode of the DRAM perform, causing a data transfer is done at high speed, and therefore the access time reduce significantly in the event of a cache miss.
• (2) A data transmission circuit for the data transfer between the SRAM field and the DRAM field is used by a latch circuit to temporarily Storage of data formed. Therefore, it becomes possible to use direct data Input / output access to the data transfer circuit from outside. Thus, the data input / output of the DRAM field can be carried out without affecting the data stored in the SRAM. Therefore a semiconductor memory device can be formed that not only as a cache system, but also for Graphics applications useful is.
• (3) The data transfer circuit has a write buffer circuit to transfer of data to the DRAM and a read data transfer buffer for receiving data from the DRAM field, which is formed separately. Each of them will formed by a latch circuit. Therefore, the data transfer between the DRAM field and the SRAM field are executed in parallel. This allows a data transfer at high speed.
• (4) The bidirectional data transfer circuit has a write transfer circuit with a plurality of latches for transferring data to the DRAM field and it is a masking circuit for masking the data transmission for each Latch of the write transfer circuit formed. Therefore only necessary memory data of the DRAM field changed so that the in the DRAM field stored data easily overwritten at high speed can be.
• (5) The bidirectional data transfer circuit has an intermediate register means for temporary storage of data, a buffer circuit for receiving the data created by the intermediate register and for transmission the data to the DRAM field, an intermediate masking register for storage of masking data, which is an independent masking of data transmission to the DRAM field for each data bit enables and a master masking register that holds the masking data from the Intermediate masking register synchronous with the data transfer from the intermediate data register to the buffer register Mask the data transfer from the buffer register to the DRAM field. Because the masking data of the intermediate masking register depending on whether the data from the outside or created by the SRAM field, can be set selectively could, only the data that is to be transferred to the DRAM field is included passed at high speed.
• (6) The masking data of the intermediate masking register become all reset when data is transferred from the SRAM field be while only the masking data corresponding to the intermediate masking register, which are subject to the data writing of the externally created data, are reset in the intermediate masking register so that only the transfer the required data safely and easily to the DRAM field become.
• (7) Because the data transfer accomplished when the intermediate data register and the intermediate mask register are separated from the buffer register or master masking register, can repeats the same data into the memory cell blocks of the DRAM can be written. Thus, a process like "filling" with running at high speed become. Therefore, a semiconductor memory device can be obtained the for Graphics processing is effective.
• (8) Because a DRAM field, an SRAM field and a bidirectional Data transmission circuit for the data transfer are formed between the SRAM field and the DRAM field and the operation regarding the DRAM field independently from the operation of the SRAM field and concerns data input / output, independently of one another by a separate control circuit executed can be a data input / output that has a high speed mode, such as connecting the page mode of the DRAM. Furthermore, successive data writing, such as the Block write mode, can be performed at high speed.
• (9) Because a signal indicating the selection / non-selection of the semiconductor memory device controls, and a signal to lock the data input / output separately are formed, a semiconductor memory device can be formed with a memory expansion capability and fast bank switching can be implemented.
• (10) Because two control signals are formed for data input / output and the activation / deactivation of the input / output circuit is controlled according to the result of AND formation of these two input / output control signals, bank switching at high speed can be easily implemented , If the semiconductor memory device has both the DRAM section and the SRAM section, the cache size formed by the SRAM can be easily Way to be changed.
• (11) The bidirectional data transmission circuit has a read data transfer buffer with a latch circuit for temporary Storing and locking data from the DRAM field and a write data transfer buffer, the data directly from the SRAM field or receiving the data input / output port. This will make one Semiconductor memory device implemented in the before storage of read data from the DRAM field in the read data transfer buffer entered / output at high speed and a write-through cache can run at high speed.
• (12) In the DRAM field, you can use the data latch function the DRAM sense amplifier write data without writing to the DRAM field in write-through mode accomplished become, that is, write data without assignment in the event of a cache miss. This enables data writing according to the block write mode executed at high speed become. Furthermore, a hit process can take place immediately after the data has been written for one other address executed be so that a Semiconductor memory device with a cache that runs at high speed works, can be achieved.
• (13) In a semiconductor memory device with a cache memory which is in the Copy mode works, is a high-speed access possible by using the latch data of the DRAM sense amplifiers. Therefore one can use a semiconductor memory device with a short waiting time received even in the event of a cache miss.
• (14) In the semiconductor memory device with write-back method it is not necessary to write data to the SRAM field in the event of a cache miss, because those locked in the DRAM sense amplifiers Data can be used. This makes data writing at high speed and one Data writing possible in block write mode.
• (15) Cached with write-back mode can the locked data of the DRAM sense amplifiers are used. Thereby receives to a semiconductor memory device with a cache that at cache miss has a short wait.
• (16) Because the transfer / non-transfer of clock signals to the control circuit that the DRAM section drives and to a second control circuit for controlling the SRAM section and the input / output of data are carried out independently of one another, can the clock signal transmission to the DRAM section are stopped while the SRAM section is operating. This can significantly reduce the power consumption in the DRAM section become. Thus, a semiconductor memory device can be made smaller Achieve power consumption.
• (17) As command data for the command register, the data for specifying the input / output port arrangement the semiconductor memory device, the operation mode and the like Gössen stores predetermined bits of the column selection address of the DRAM are used. Therefore can Command data without increment the number of control connections can be entered. Command data for setting the data writing mode from the data transfer circuit to the DRAM field can occur simultaneously in the operating mode determination cycle are fed. Therefore, a desired one Operating mode set in a simple manner and at high speed be without load for increase external devices.
• (18) Because the address bits to choose in the DRAM field all are taken over as command data and a part the command data for specifying the setting / resetting of the test mode and to set the type of data transfer mode command data can be used for the DRAM field in test mode operation easily set using a memory tester become. This allows a semiconductor memory device for which a test can be carried out easily and with high reliability can without the burden of To increase memory tester be implemented.
• (19) Because the self-refresh of the DRAM field at the same time executed with the command register setting mode can be used to determine of the mode necessary time can be reduced, and a semiconductor memory device, which enables high-speed access to be implemented.
• (20) In the command data setting mode, only the operation becomes Store command data in the command register the operation of the DRAM field at all unaffected. This allows the command data can be changed easily, even if that DRAM works.
• (21) Because the masking data to mask the data transfer are set to the DRAM field after switching on, a setting is made the masking values ensured.
• (22) Because the peripheral circuit by applying a predetermined one Number of master clock signals initialized after switching on will, can the conditions of the internal circuits safely to a predetermined initial state can be set.
• (23) There is a first control section for controlling the operation of the DRAM array and data transfer between the DRAM array and the bidirectional data transfer circuit, and a second control section for controlling the operation of the SRAM array and data transfer between the SRAM array and the bidirectional data transmission circuit or external access to the SRAM field formed separately. The first and second control sections work independently of each other. As a result, a multi-function semiconductor memory device that operates at high speed can be formed.
• (24) Because a second transistor element is driven around the first node to a predetermined potential only for a predetermined one Period of time to drive when the first transistor element that the signal line drives, is inactive, the external signal line can even then at a high speed to a predetermined potential level be driven if a structure is used in which the first Transistor element is connected in the manner of an OR logic. Thereby becomes a high-speed access with a simple circuit structure allows.
• (25) Because a special test mode is used when a predetermined state of an external signal twice or more can be applied in succession in synchronism with the external clock signal the test operation can be realized by the timing condition, so that the Test mode is set in a simple and safe way.
• (26) Because a special test mode is used when external Signals of a predetermined combination of states continuously for a predetermined one Period of time can be applied synchronously to the external clock signal, and the test mode is exited when the external signals of this predetermined State combination supplied the test mode can be taken in a simple and safe way become. While this period can be a desired one Command can be supplied to the memory device, and the test can be executed while the Semiconductor memory device operates in a desired operating mode. Because leaving the test mode is carried out synchronously with the clock signal can, the exit can be set by the timing conditions be so that the Test mode reset safely can be.
• (27) Because the refresh control terminal by the mode setting means as input connection or set as an output port under the control of a storage device, a plurality of Semiconductor memory devices are refreshed so that the self-refresh mode while of normal operation can be.
• (28) Because the refresh according to an included self-refresh timer dependent on from a sleep mode determination signal, it is not necessary a refresh request to other semiconductor memory devices to send, so that Power consumption for the charging / discharging of signal lines can be reduced.
• (29) When transferring data from the DRAM field to the first data transmission device can in the second transmission device for transferring Data from the SRAM field to the DRAM field selectively transfer the data between Latches in the second transmission device accomplished be so that under A quick write-back can be performed using the page mode can. This allows the enlargement of the Block size of the cache, the page mode and the fast write-back mode can executed simultaneously and high-speed access can be realized while the waiting time in the event of a cache miss is reduced.
• (30) Because in the transfer circuit for transferring data from the SRAM field a plurality of latches are formed for the DRAM field and the transmission process selectively between the latches in the second transmission device accomplished when data is transferred from the DRAM field to the first transfer device the cache block size can be increased and the cache hit rate will be improved. Furthermore, the data transmission between the SRAM field and the DRAM field according to the page mode accomplished become. The fast write back process A cache miss can also be done in accordance with the page mode accomplished become. This allows a data transfer at high speed.
• (31) Because the second transmission device in the write data transfer circuit N stages of FIFO storage means the block size of the cache be enlarged.
• (32) Because the CDRAM operates in register output mode and the Access by the CPU and the image processing unit for access access to the CDRAM, the access works by the CPU and access for the video display is not against each other, the CDRAM can run at high speed can be addressed, and therefore an image processing system be realized, the fast processing of the image data allows.

Claims (28)

A semiconductor memory device comprising: a DRAM array ( 102 ; 7001 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns, a first control means ( 128 . 110 . 112 ; 1452 ; 6008 . 6009 ) with a line selection means ( 110 ), which depends on a first address, for selecting a row in the DRAM field and a column block selection means ( 112 ) which is dependent on a second address for selecting a column block with a plurality of columns of the DRAM, the control means being dependent on an external control signal for driving the DRAM field and the column block selection means being able to repeatedly select different column blocks while the row selection means is in an active state and in response to a one-time activation selects a line from a data transfer specification; an SRAM field ( 104 ) with a plurality of static memory cells, which are arranged in a matrix of rows and columns; a second control means ( 132 . 118 . 120 ; 6000 . 6006 . 6002 . 6004 ) with a memory cell selection means ( 118 . 120 ), which is dependent on a third address which is applied independently of the first and second address, for selecting a plurality of memory cell blocks in the SRAM field in response to the one-time activation of the data transfer specification, the control means being driven by an externally supplied second control signal the SRAM field is dependent and independent of the first control means; and a data transmission means ( 106 ), which is dependent on the one-time activation of the data transfer specification, for performing block-by-block data transfer between the selected column block of the DRAM array and the selected memory cell block of the SRAM array. A semiconductor memory device comprising: a DRAM array ( 102 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns, an SRAM field ( 104 ) with a plurality of static memory cells, which are arranged in a matrix of rows and columns, a first selection means ( 110 . 112 ) for the simultaneous selection of a plurality of memory cells in the DRAM field, a second selection means ( 118 . 120 ) for the simultaneous selection of a plurality of memory cells in the SRAM field, a data transmission means ( 106 ) with a plurality of latch means ( 140 . 142 . 144 ) for temporarily storing applied data for simultaneous data transfer between the selected plurality of memory cells of the DRAM array and the plurality of selected memory cells of the SRAM array, and an access means ( 134 . 136 . 138 . 120 ; 1434 . 1438 . 1514 . 1516 . 1518 ) to access the latch means in the data transmission means ( 106 ) corresponding to an applied address to input / output data, the data transmission means ( 106 ) a reading transfer medium ( 140 ; 1510 ; 1610 ; 5000 . 5002 ) for receiving data transmitted from the DRAM field and a write transfer means ( 142 . 144 . 146 ; 3520 . 3539 ) for transferring data to the DRAM field, and the read transfer means and the write transfer means each have a plurality of latch means ( 402 . 4004 . 4006 . 4008 . 5000 . 5002 ) for the temporary storage of created data. Semiconductor memory device according to Claim 2, characterized in that the data transmission means ( 106 ) a masking agent ( 146 ), which is formed corresponding to each latch means of the write transfer means, for masking the data transfer to the DRAM field by the respective latch means. Semiconductor memory device according to Claim 2, characterized in that the data transmission means ( 106 ) a buffering agent ( 4004 ) which receives data from the latch means of the write transfer means for transferring the data to the DRAM field, an intermediate masking means ( 4006 ), which is formed in accordance with each of the plurality of latch means of the write transfer means, for storing masking data which indicate whether the transfer of the data stored in the corresponding latch means to the DRAM field is to be masked, ( 4008 ) which receives the masking data from the intermediate masking means in synchronization with the data transfer from the latch means to the buffer means, for masking the data transfer from the buffer means to the DRAM field, and a control means ( 6006 . 6009 ), which is dependent on an operating mode specification, which indicates whether the latch means has received data from the SRAM field or externally supplied write data, for setting masking data of the intermediate masking means. Semiconductor memory device according to Claim 4, characterized in that the control means ( 6006 . 6009 ) a means ( 6009 ) resetting all masking data of the intermediate masking means when the operating mode setting indicates a data transfer from the SRAM field to the write transfer means, and means ( 6006 ) for resetting only the masking data corresponding to the latch means that receives the external write data when the mode setting indicates that external write data is supplied to the data transfer means. Semiconductor memory device according to Claim 4 or 5, characterized in that the control means ( 6006 . 6009 ) also a means ( 6009 ), which is dependent on an operating mode specification which indicates that the same value is to be transmitted repeatedly to the DRAM field, for separating the latch means ( 4002 ) from the buffering agent ( 4004 ) and to separate the intermediate masking agent ( 4008 ) from the master masking agent ( 4006 ). Semiconductor memory device according to Claim 2, characterized in that the write transfer means ( 106 ) a slave latch agent ( 4002 ) for temporary storage a master latch means (data stored by the SRAM field or external write data supplied by the access means ( 4004 ) a temporary masking means for temporarily storing data which are created by the slave latch means ( 4006 ) for storing masking data indicating that the data stored in the slave latch means should or should not be masked for transmission to the DRAM field, a master masking means for temporarily storing masking data from the slave masking means, and a driver means ( 3540 . 3550 ) for transferring data from the master latch to the DRAM field corresponding to the masking data from the master masking means. Semiconductor memory device according to Claim 7, characterized by a first control means ( 6000 . 6006 ) to control the data transmission from the SRAM field to the slave latch means ( 4002 ), and a second control means ( 6008 . 6009 ), which is formed independently of the first control means, for controlling the data transmission from the slave latch means ( 4002 ) to master latch agent ( 4004 ) and the slave masking agent ( 4006 ) to the master masking agent ( 4008 ). Semiconductor memory device according to Claim 8, characterized in that the first control means ( 6000 . 6006 ) a means ( 6000 . 6004 ) for activating the data writing to the slave latch means by the access means. Semiconductor memory device according to Claim 2, characterized in that the read transfer means ( 106 ) a slave latch agent ( 5000 ) for the temporary storage of data from selected memory cells of the DRAM field ( 102 ), and a master latch agent ( 5002 ) for temporarily storing data from the slave latch means for the transfer to selected memory cells in the SRAM field or for access means. Semiconductor memory device with a DRAM array ( 102 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns, an SRAM field ( 104 ) with a plurality of static memory cells, which are arranged in a matrix of rows and columns, a data transmission means ( 106 ) with a plurality of reading transfer means ( 140 ; 1510 ) for receiving data transmitted from the DRAM field and for temporarily storing the data in order to transmit data between the DRAM field and the SRAM field, a first control means ( 128 . 108 . 112 ) for controlling an activity related to the selection of a memory cell in the DRAM field for transferring the data of the selected memory cell to the read transfer means, a second control means ( 6000 . 6002 . 6004 ) which operates in parallel with and independently of the first control means, for controlling an activity relating to the selection of a static memory cell in the SRAM field for inputting and outputting data to or from the selected static memory cell, and a third control means ( 6000 . 6006 ), which operates independently of the first control means, for controlling an activity related to the transfer of data from the read transfer means to the SRAM field. Semiconductor memory device with a DRAM array ( 102 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns, an SRAM field ( 104 ) with a plurality of static memory cells, which are arranged in a matrix of rows and columns, a data transmission means ( 106 ) to perform a bitwise transfer between the DRAM field and the SRAM field, a data input / output means ( 134 . 136 . 138 ) for transmitting data between the SRAM field or the data transmission means and an external data input / output node (DQ; D, Q), a first control means ( 1424 . 1464 . 1450 . 1452 ), which is dependent on a first control signal, for setting at least the DRAM field, the SRAM field, the data transmission means and the data input / output means to an unselected standby state, and a second control means ( 1490 . 1494 ), which is dependent on a second control signal, for controlling the activation and deactivation of only the data input / output means. Semiconductor memory device according to Claim 12, characterized in that the second control signal (DQC) has a control signal (DQCO) of a first type and a control signal (DQC1) of a second type, and the second control means ( 1490 . 1494 ) means for generating a control signal for controlling only the data input / output means ( 1100 ) by a logical AND formation of the control signal of the first type and the control signal of the second type. Method for driving a semiconductor memory device with a DRAM array ( 102 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns, a sense amplifier means ( 114 ) that the Da th of the memory cells connected to a selected row of the DRAM field is detected, amplified and locked, an SRAM field ( 104 ) with a plurality of static memory cells, which are arranged in a matrix of rows and columns, a read transfer means ( 1510 ) with means ( 5000 . 5002 ) for locking applied data from the DRAM field, and a write transfer means with latch means ( 4002 . 4004 ) for the temporary storage of data which are supplied from a selected memory cell in the SRAM field or of externally applied data, characterized by the steps (a) selecting a line in the DRAM field and reading, amplifying and locking the data of the memory cells, connected to the selected row by the sense amplifier means and in data read mode: (b) determining whether or not the data requested from an external device is stored in the SRAM array, (c) selecting a corresponding memory cell of the SRAM array corresponding to one applied address and reading the data of the selected memory cell if the result of the determination in step (b) indicates that the requested data are in the SRAM field, (d) determining whether the applied address specifies the selected line of the DRAM field or not, if the result of the determination in step (b) indicates that the requested data is not available in the SRAM field, (e) select a plurality of columns in the DRAM field, transferring the data of the selected plurality of columns to the read transfer means, selecting the corresponding memory cell in the SRAM field according to the address applied, transferring the data from the read transfer means to the selected cells in the SRAM field and further selecting one Memory cell in the SRAM field specified by the applied address to read data from the selected memory cell when the result of the determination in step (d) indicates that the applied address determines the selected row of the DRAM field, (f if the result of the determination indicates that the created address determines a line which is different from the selected line of the DRAM field: (g) initializing the DRAM field and the sense amplifier means and then selecting a corresponding line in the DRAM field accordingly the created address, (h) selecting a plurality of columns in the DRAM field corresponding to the a applied address and transferring the data of the selected plurality of columns to the read transfer means after the corresponding row in the DRAM field has been selected, (i) selecting memory cells in the SRAM field corresponding to the applied address simultaneously with or in parallel with the data transfer to the read transfer means, Transferring data from the read transfer means to the selected memory cells and further selecting a memory cell in the SRAM field and reading the data of the selected memory cell in parallel. Method for driving a semiconductor memory device with a DRAM array ( 102 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns, a sense amplifier means ( 114 ), which captures, amplifies and latches the data of the memory cells connected to a selected row of the DRAM field, an SRAM field ( 104 ) with a plurality of static memory cells, which are arranged in a matrix of rows and columns, a read transfer means ( 1510 ) with means ( 5000 . 5002 ) for locking applied data from the DRAM field and a write transfer device ( 1520 ) with latch means ( 4002 . 4004 ) for temporary storage of data; which are supplied from a selected memory cell in the SRAM field or from externally applied data, characterized by the steps of selecting a line in the DRAM field and reading, amplifying and locking the data of the memory cells which are connected to the selected line by the Sense amplifier means and in data write mode: (i) if there is a memory cell in the SRAM field with the address to which access is required by an external device, (a) writing data into the corresponding memory cell of the SRAM field in accordance with the address applied and Writing the data to the write transfer means, (b) selecting a column in the DRAM field and transferring the data between the selected column and the write transfer means when the created address specifies the selected row of the DRAM field, (c) initializing the DRAM field and the sense amplifier means, selecting a row and a column in the DRAM field corresponding to the set address, and then transferring data between the selected column of the DRAM field and the write transfer means if the applied address determines a row different from the selected row of the DRAM array, (ii) if there is no memory cell in the SRAM array with the address to which access is required by the external device, (d) writing data into the write transfer means corresponding to the address applied, (e) selecting a column in the DRAM field corresponding to the address applied and transferring data from the write transfer means to the selected line if the created address specifies the selected line in the DRAM field, and (f) initializing the DRAM field and the sense amplifier means and then selecting a row and a column in the DRAM field according to the address applied, and transferring the data from the write transfer means to the selected column if the address applied is not the selected line in the DRAM field sets. A method according to claim 15, characterized in that the determination in steps (e) and (f) whether the created address is the selected line in the DRAM field, postpones until a next access is requested. Method for driving a semiconductor memory device with a DRAM array ( 102 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns, a sense amplifier means ( 114 ), which captures, amplifies and latches the data of the memory cells connected to a selected row of the DRAM field, an SRAM field ( 104 ) with a plurality of static memory cells, which are arranged in a matrix of rows and columns, a write transfer means ( 1520 ) with a plurality of latch means ( 4002 . 4004 ) for transferring data to a block of a plurality of columns in the DRAM field, and a read transfer means ( 1510 ) with a plurality of latch means ( 5000 . 5002 ) for receiving data from the block of the plurality of columns selected in the DRAM field, characterized by the steps (a) selecting a row in the DRAM field and reading, amplifying and locking the data of the memory cells associated with the selected row by the sense amplifier means and (A) in data read mode (i) if there is no data in the SRAM field to be accessed by an external device, (ii) determining whether a write indicator bit is set which indicates that the data stored in the SRAM field and the data stored in the DRAM field differ, which are defined by the same address, (iia) selecting a plurality of memory cells of the SRAM field according to an applied address, transferring and storing the data of the selected memory cells to and in the write transfer means, (iib) if the created address indicates the selected line in the DRAM field: (iib1) selecting a block of a meh number of columns corresponding to the applied address from the selected row of the DRAM field and transferring the data of the block of the selected plurality of columns to the read transfer means, (iib2) selecting a plurality of memory cells in the SRAM field corresponding to the applied address for further transfer of the data transferred to the read transfer means to the selected memory cells, (iib3) selecting and reading corresponding data among the data transferred to the read transfer means according to the address applied, (iic) when the address applied indicates a line which is from the one selected in the DRAM field: (iic1) initializing the DRAM field and the sense amplifier means and then selecting a row and a block of a plurality of columns in the DRAM field according to the address applied, and transferring the data of the selected column block to the read transfer means , (iic2) Select one A plurality of memory cells in the SRAM field corresponding to the address applied, transferring data from the read transfer means to the selected memory cells, and selecting and reading data transferred to the read transfer means corresponding to the address applied, (iii) when the write indicator bit is cleared: (iiia) when the applied address specifies the selected row in the DRAM field, selecting a block of columns from the selected row and transferring the data of the block to the memory cells of the SRAM field selected by the applied address and further reading from Data to be stored in a memory cell in the SRAM field corresponding to the address applied, selecting one row and a plurality of columns in the DRAM field corresponding to the address applied, and transferring the data from the plurality of columns to memory cells derived from the created address are set in the SRAM field, and reading data are to be stored in a memory cell in the SRAM field, which is determined by the created address, and (B) in data write mode (Ba) accessing the SRAM field according to the created address and writing data into the corresponding static memory cell, if in SRAM field there is a memory cell that is set by the applied address, (Bb) setting the write indicator bit, (Bc) if the SRAM field does not exist the memory cell that is set by the address that is applied by the external device: (Bc1) writing data to the write transfer means according to the created address, (Bc2) selecting columns from the selected row according to the created address and transferring data from the write transfer means to the selected column when the created address specifies the selected row in the DRAM field, (Bc3) initialize the DRAM array and the sense amplifier means and select a row and gap s in the DRAM field according to the created Address if the created address specifies a line that is different from the line selected in the DRAM field, (Bc4) transfer from the write transfer means to the selected column. Semiconductor memory device which accepts an externally applied control signal in synchronism with an externally applied clock signal in a pulse train for generating an internal control signal, comprising: a DRAM field ( 102 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns, a first control means ( 128 ), which is dependent on the clock signal, for taking over a first external control signal for generating a control signal for driving the DRAM field, an SRAM field ( 104 ) with a plurality of static memory cells which are arranged in a matrix of rows and columns, an input / output means ( 134 . 138 ) for inputting and outputting data from and to outside the storage device, a data transmission means ( 106 ) for exchanging data with the input / output means and for transferring data between a selected memory cell in the DRAM field and a selected memory cell in the SRAM field, a second control means ( 132 ) for taking over an externally applied second control signal as a function of the clock signal for generating a control signal for driving at least the SRAM field or the data transmission means, a first clock signal gate ( 126 ), which is dependent on a first clock signal masking signal, for blocking the transmission of the clock signal to the first control means and a second clock signal gate ( 130 ), which is dependent on a second clock signal masking signal, for blocking the transmission of the clock signal to the second control means. A semiconductor memory device that accepts an externally applied signal in synchronism with a clock signal that is applied in the form of pulses, comprising: a DRAM array ( 102 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns, an SRAM field ( 104 ) with a plurality of static memory cells, which are arranged in a matrix of rows and columns, a data transmission means ( 106 ) for executing at least one data transfer between a selected memory cell of the DRAM field and a selected memory cell of the SRAM field, an instruction register means ( 9033 ) for storing command data for specifying at least one specific operating mode of the semiconductor memory device and a means ( 400 ), which is dependent on a combination of the states of external control signals which are applied in synchronism with the clock signal, and any signal which is currently fed to an address input node for selecting a row and a column of the DRAM field is taken over as the command value Part of it is used as data for specifying the type of data transfer mode to the DRAM array in the data transfer means and as data for specifying a test mode of the semiconductor memory device to store the value in the command register means. Semiconductor memory device according to Claim 19, characterized by a means ( 404 . 406 ) to self-refresh the DRAM field when the test mode is set. Semiconductor memory device according to Claim 19 or 20, characterized by a means ( 9030 ), which depends on a combination of the states of external control signals, for setting only the command data in the command register means. Semiconductor memory device with a DRAM array ( 102 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns, an SRAM field ( 104 ) with a plurality of static memory cells, which are arranged in a matrix of rows and columns, a write transfer means ( 142 . 144 ; 1520 ) for temporarily storing applied data and for transferring the stored data to a selected memory cell of the DRAM field, a masking data register means ( 4006 . 4008 ) for storing masking data for masking the data transfer from the write transfer means to the selected memory cell of the DRAM field, and a control means ( 400 . 402 ), which depends on the switching on of the write transfer means, for setting all masking data of the masking data register means to a state which masks the data transfer. Semiconductor memory device according to Claim 22, characterized by a means ( 400 ), which is dependent on turning on the write transfer means, for repeatedly executing the resetting operation of a peripheral circuit according to a predetermined number and for activating the control means. A semiconductor memory device comprising: a DRAM array ( 102 ) with a plurality of dynamic memory cells, which are arranged in a matrix of rows and columns, an SRAM field ( 104 ) with a plurality of sta table memory cells, which are arranged in a matrix of rows and columns, a data transmission means ( 106 ) for transferring data between a selected memory cell of the DRAM field and a selected memory cell of the SRAM field, a first control means ( 128 ), which is dependent on a first address and a first control signal, for controlling the operation of the DRAM array and the data transfer process between the DRAM array and the data transfer means and a second control means (132) which is formed independently of the first control means and independently operates from the first control means, is dependent on a second control signal and a second address, which is applied independently of the first address, for controlling an activity relating to the driving of the SRAM field, one relating to external access to the SRAM field related activity, the data transfer operation between the SRAM array and the data transfer means, and the data input / output operation between the data transfer means and the environment of the device. A semiconductor memory device comprising: a DRAM array ( 102 ) with a plurality of dynamic memory cells, an SRAM field ( 104 ) with a plurality of static memory cells, a first transmission means (DTBR) with at least two stages of serially connected latch means (STW, MTW) for transmitting data from the DRAM field to the SRAM field, a second transmission means (DTBW) with at least two Stages of serially connected latch means (STR, MTR) for transferring data from the SRAM field to the DRAM field, a first control means ( 6008 . 6009 ), which is dependent on a first transfer determination (DRT1), for carrying out the data transfer from the DRAM field to the first transfer means and for performing the data transfer between the latch means of the second transfer means and a second control means ( 6008 . 6009 ), which is dependent on a second transfer determination (DRT2), for carrying out the data transfer from the DRAM field to the first transfer means and for blocking the data transfer between the latch means of the second transfer means. A semiconductor memory device comprising: a DRAM array ( 102 ) with a plurality of dynamic memory cells, an SRAM field ( 104 ) with a plurality of static memory cells, a first transfer means (DTBR) with at least two stages of serially connected latch means (STR, MTR) for transferring data from the DRAM field to the SRAM field, a second transfer means (DTBW) with at least two Stages of serially connected latch means (STW, MTW) for transferring data from the SRAM field to the DRAM field, a first transfer control means ( 6000 . 6006 ), which is dependent on a first transfer determination, for carrying out the data transfer from the SRAM field to only one latch means of the second transfer means and a second transfer control means ( 6000 . 6006 ), which is dependent on a second transmission determination, for carrying out the data transmission from the SRAM field to a plurality of latching means of the second transmission means. A semiconductor memory device according to claim 25 or 26, characterized characterized that the second transmission means N levels of FIFO storage means (# 1 - # N), where N is one integer is not less than 2. A semiconductor memory device according to claim 2, wherein at least one of the read transfer means ( 140 ; 1510 ; 1610 ; 5000 ; 5002 ) and from the write transfer means ( 142 . 144 . 146 ; 1520 ; 3520 . 3530 ) a slave latch agent ( 5000 ; 4002 ) to receive data from one of the SRAM field ( 104 ) or the DRAM field ( 102 ) and a master latch agent ( 4004 ; 5002 ) for receiving data from the slave latch means ( 5000 ; 4002 ) for transmission to the other from the SRAM field ( 104 ) or the DRAM field ( 102 ) having.