DE4391003B4 - High speed current mode computer bus system - has transmission lines for coupling master current mode bus drivers to slave bus receivers having sampling and amplifying circuit stages - Google Patents

Abstract

The system consists of a bus which is configured to have all master devices clustered at an unterminated end of the bus. The slaves are located along the remaining length of the bus and the opposite end of the transmission line of the bus is terminated. The termination resistor at the end of the bus where the master devices are located is eliminated to reduce the drive current needed to produce a given output swing. The bus input receiver comprises a two stage buffered sampler and amplifier which receives a small swing signal from the bus and samples and amplifies the low swing signal to a full swing signal within a clock cycle using CMOS circuits.

Description

BACKGROUND THE INVENTION

FIELD OF THE INVENTION

The The present invention relates to the field of high speed computer buses. In particular, the present invention is in the field of power-driven High-speed computer buses addressed.

computer buses provide the funds to several computer devices in such a way that the equipment can communicate with each other. The buses usually connect Master devices, for example Microprocessors or peripheral controllers, and slave devices, for example Memory components or bus transceivers. Usually the master and slave devices located at a position along the bus, and the bus is at both ends of the transmission line completed the bus. In a double ended bus are both ends of the bus signal lines with terminating resistors of one of the impedance of Signal lines corresponding impedance completed. When a Signal along the transmission line of the bus to the terminator guided In this way, the resistor absorbs the signal and excludes signal reflections that can occur on the bus and lead to faulty signals.

When the bus is double terminated, each driver of a device on a bus must effectively drive two buses in parallel, one running from the location of the device to the left and one to the right. These signals propagate down the bus and the bus is steady when both signals reach the termination resistors. In the worst case, the settling time for the bus configuration is equal to the propagation delay t _f on the bus; and this case occurs when a driver on one end of the bus sends to a receiver on the opposite end of the bus. The problem with this type of configuration is that the power consumed by the device driving the bus is relatively high because the impedance of the bus is relatively low.

Usually Buses are driven by voltage level signals. However it is has become advantageous to provide buses by one Power to be driven. An advantage of a current mode bus is a reduction in the peak turn-on current. In a voltage mode device, the output transistor must the driver to drive the maximum specified current worst-case operating conditions be dimensioned. Under rated conditions less than the maximum Load, the inrush current when the output is turned on, but before he reaches the maximum, be very high. The current mode driver on the other hand draws a known current regardless of the load and the operating conditions. additionally Impedance discontinuities occur when the driver device in the transmission state is characterized by a low output impedance. These discontinuities to lead to reflections that inevitably additional Cause bus settling time. Power mode drivers, on the other hand, are through a high output impedance, so that a propagating on the bus Signal no significant discontinuity of line impedance due encountered in the sending state driver. reflections are avoided in this way and the required bus settling time is reduced. An example of a current mode bus is disclosed in U.S. Patent 4,481,625 issued November 6, 1984 entitled "High Speed Data Bus System". One Current mode bus is also described in PCT International Application PCT / US91 / 02590, filed on 16 April 1991, published on 31 October 1991 titled Integrated Circuit I / O Using a High Performance Bus Interface described by the same assignee as this invention was registered.

constructive Requirements can the use of MOS circuits prescribe. When the bus driver integrated CMOS circuits The signal voltage controls of external signals are usually Maximum-to-maximum levels, where the voltage of the high Level usually 3.3 to 5 volts and the voltage of the low level is zero. Such high voltage controls are in high-speed transmission line buses due to the high level of induced noise and power dissipation undesirable. Other systems have tried to solve the problem by using different ones reduced voltage drops, for example, by GTL (running transistor logic), signal level (0.8 to 1.4 volts). GTL levels have been optimized for voltage mode drivers in the past and are too low in voltage to make them effective current mode drivers to construct. An example of such a system is in the U.S. Patent 5,023,488 entitled "Drivers and Receivers for Interfacing VLSI CMOS Circuits to Transmission Lines "discussed.

US 4,247,817 relates to a transmission system wherein signals are transmitted to a receiver via a transmission line. In particular, it relates to the synchronization of events, wherein the synchronization should be such that the Position of the signal source and the receiver along the transmission line is unimportant. For this purpose, a sawtooth generator or ramp generator 12, 16 is provided at least at one end of the transmission line. This generator generates a particular ramped waveform which propagates along the signal line 10 and is reflected back to the transmitter at the ends of the signal line. After the reflected wave reaches the transmitter, the resulting voltage level is the same across all receivers along the line.

US 4,806,198 relates to a microprocessor system which is suitable for connecting a memory or an input / output unit with an N / 2-bit data bus to a microprocessor with an N-data bus. For this purpose, the microprocessor system has a unit which divides a word transfer instruction into two 112 word transfer instructions.

SUMMARY PRESENTATION THE INVENTION

It It is therefore an object of the present invention to provide a high speed current mode computer bus to disposal to set, which minimizes the settling time for the bus.

It It is also an object of the present invention to provide a high speed current mode computer bus to disposal to provide interfaces with CMOS circuits.

It It is a further object of the present invention to provide a bus receiver for disposal to provide CMOS VLSI circuits with high-speed current mode buses to pair.

The The object of the invention is achieved by an input receiver for Sampling a first signal having a first voltage level according to the claim 1, an input receiver according to the claim 13, a system with a master device, a slave device and a signal line between the master device and the Slave device according to claim 20 and a method of receiving a plurality of data according to claim 23 solved.

BRIEF DESCRIPTION OF THE DRAWINGS

The Objects, features and advantages of the present invention illustrated by the following detailed description, in which:

1 shows the bus configuration used in the preferred embodiment of the present invention.

2a and 2 B show the NMOS device operating as a current source in the preferred embodiment of the high speed bus of the present invention.

3 FIG. 12 is a block diagram of the bus receiver used in the high-speed bus of the present invention. FIG.

4a FIG. 12 is a block diagram of the clocked buffered amplifier used in the bus receiver of the present invention; and FIG 4b Fig. 12 shows a more detailed circuit diagram of the clocked buffer amplifier of the receiver device of the high-speed bus according to the present invention.

DETAILED DESCRIPTION

The bus configuration used in the low impedance current driven high speed bus of the present invention is shown in the block diagram of FIG 1 shown. Master devices connected to the bus 10 . 20 are with an end 25 the transmission line 5 coupled to the bus. Slaves 30 . 35 . 40 . 45 are along the transmission line 5 arranged. The opposite end 50 the transmission line 5 is with a terminator 55 completed. As already mentioned above, the problem with known bus configurations is that the power consumed by the device driving the bus is relatively high because the impedance of the bus is relatively low.

In the configuration of the present invention, the amount of power required is reduced by the bus configuration used since the omission of the terminating resistor at the En de 25 of the bus reduces the required drive current needed to produce a given output drive. Because the master devices are located at the end of the bus, the current driven by the master device output driver generates a fully-triggered signal that propagates along the bus to a slave device. One at a point along the bus between the two endpoints 25 . 50 arranged slave device generates a drive current, which is divided at the output to a 1/2 controlled signal in the direction of the first end 25 and a 1/2 controlled signal toward the second end 50 to create. By putting the master device on the end 25 is disposed of the bus and a termination resistor is omitted, the master device receives a fully controlled signal, the Is the sum of the 1/2 output signal and a 1/2 output signal which is the reflection of the 1/2 output signal. In this way, the master devices located in the area where the 1/2 output signal is duplicated receive a fully modulated signal due to the sum of the signal and the reflected signal. Preferably, the master devices are located at the point where the signal reflection occurs. However, the extent of the range is determined by the signal width and signal propagation time along the bus.

Although removing the terminating resistor at one end causes the bus to settle slower, this additional delay does not matter because the bus transactions at the master end of the bus 25 begin or end. The removal of the termination resistor from the one end of the bus leaves the worst case delay at t _f , the worst case worst case delay found in known bus configurations.

This delay t _f will be explained later using the example. In the case of a master device sending to a slave device 10 the master sees only a single transmission line of impedance Z, since it is connected to the open end of the bus. When the power source of the driving device has a magnitude I, a signal voltage of I * Z goes down the bus. The signal arrives at the terminator and stops at the terminator 55 such that the bus settles after a propagation delay t _f . When a signal is transmitted from a slave device to a master device, the device sees two transmission lines, one in each direction, and sends a signal voltage of I · Z / 2 in both directions. The signal, which runs in the direction of the closed end, reaches the resistance 55 and stops. The signal going towards the unfinished end 25 runs, reaches the end 25 and is reflected back in the opposite direction, with the amplitude doubling to provide the needed modulation. However, because the master devices 10 . 20 at the end 25 of the bus are located, see the devices 10 . 20 the final value after only one t _f , even if the bus has not yet settled completely.

It should be noted that the reflected signal traveling back along the bus results in intersymbol interference for the other slave devices on the bus; however, this is not important as the slaves only send data to the master and not to other slaves. However, it is important that the reflected wave not cause any further disturbances which would lead to secondary reflections back to the master, which may possibly lead to interference at the master. One possible source of such interference is the original slave transmitter on the bus. In the more common type of bus using a voltage source, the low impedance driver would cause a secondary reflection, which in turn would be reflected off the unfinished end of the bus and continue to run until the energy of the wave is consumed by line losses. Such a situation could lead to very long settling times. In the high speed bus of the present invention, current mode sources representing a high impedance to the reflected wave are used. In this way, the wave continues to propagate towards the closed end of the bus where it exits from the termination resistor 55 is absorbed.

A MOS transistor provides a good power source when operated under the right conditions. The graph according to 2a shows the drain current plotted versus the drain-source voltage for a typical NMOS device, and 2 B shows an exemplary power driver. As with the graph of 2a As can be seen, the output current is constant and substantially independent of V _DS as the drain-source voltage is above a minimum level 75 is held. Therefore, a simple NMOS device works well enough as a current source as long as the bus voltage levels V _OH and V _{OL are selected} high enough. However, the higher the values of V _OH and V _OL , the higher the consumed energy of the switched-on device. Therefore, the current mode performance and power loss must be adjusted. An area 75 . 80 , as in 2a V _{DS is kept} above a minimum level to keep the current independent of V _DS while V _{DS is} minimized to minimize V _OH and V _OL and thus the power consumed to operate the device. Preferably, voltage levels of V _OH (2.5 volts) and V _OL (2.0 volts) are used which allow a reasonable trade-off between current mode operation and power consumption. These levels also allow substantially the same driver circuit to be used in 5.0 volt operation as well as at lower voltages of 3.0-3.3 volts in CMOS technology.

An additional advantage of using a current mode driver operation is the reduction in peak on-current compared to a voltage mode driver. In a voltage mode device, the output transistor must be sized to drive the maximum specified current under worst case operating conditions. Under rated conditions, with less than the maximum load, the current transition when the off gear is switched before it reaches the maximum, be very high. The current mode driver draws a known current regardless of load and operating conditions.

It will open 3 Referenced. A novel receiver used in the current mode high-speed bus of the present invention will be described. In the preferred embodiment of the present invention, the output of the current driver is a current of the order of 25 milliamperes. A bus voltage rating of 500 millivolts results when the bus line has an impedance of 20 ohms. Therefore, the bus input receiver must be able to receive the low gated signal and amplify the signal into a highly controlled minimum-to-maximum signal compatible with the CMOS circuit within a relatively short receive time period, preferably one bus cycle. However, using currently available CMOS processes, it is difficult to sample low-level signals and amplify heavily-driven minimum-to-maximum signals within a single clock cycle. To overcome this barrier, the input circuit preferably has two input samplers operating in a ping-pong manner, the samplers sampling the received signal on alternate clock edges. Alternatively, an increased sampling frequency may be provided by other techniques, such as quadrature sampling. To simplify the design and reduce the common mode noise sensitivity of the input receiver, the bus is provided with an additional signal V _REF nominally in the middle between the high and the low bus voltage. This signal is used as a reference for the comparison, which determines whether the bus data signal is high or low.

The following will be on 3 Referenced. The input signal of the bus is the input signal of the samplers 150 . 160 , The first scanner 150 outputs a fully modulated signal while the second input sampler 160 processed the currently received, low-level signal. The output signal of the scanner 150 . 160 is the input signal of the serial / parallel converter 170 which pushes the fully controlled signal parallel to the device. Preferably, the input / sense circuit has a narrow sampling window with respect to the duration of a clock cycle in order to be able to increase the speed of the bus while taking into account clock distortion and bus settling time. In addition, the receiver is preferably capable of amplifying the bus signals in less than two bus cycles (eg, 4 nsec). Preferably, the noise that is fed back into the bus must be very low, as there may be many such sampling circuits of receivers coupled to each bus that add to the noise and therefore increase the likelihood of errors on the bus. To achieve this performance, the input sample circuit is preferably as a clocked, buffered amplifier, as in FIG 4a shown is implemented. In known receiver circuits described, for example, in PCT Application PCT / US91 / 02590 of April 16, 1991, published October 31, 1991 entitled Integrated Circuit I / O Using a High Performance Bus Interface, noise is applied to the Introduced bus data lines due to the parasitic capacitance present at the sense gate electrodes. Once a signal has been sampled, the gate electrode is turned off. When the gate is subsequently turned on to sample the next signal, the parasitic capacitor discharges voltage back to the bus signal lines. This is called feedback on the bus. Although the introduced noise may be nominal as the number of receivers coupled to the bus increases, the amount of noise increases significantly due to the summation of feedback noise from the receivers. In addition, when low voltage levels are imposed on the bus signal lines, the signals received from the sampling circuit are amplified to be compatible with the CMOS circuit. Therefore, the amount of charge injected due to the parasitic capacitance is proportional to the larger, amplified minimum-to-maximum voltage.

There is therefore provided a novel sampling circuit which accommodates the required narrow sampling window and minimizes the adverse effect of back-fed noise on the bus. It will open 4a Referenced. The receiver circuit of the present invention may be described as a two-stage sampler / amplifier. The input voltage (DATA) from the bus 200 and the reference voltage (V _REF ) 205 be from the samplers 210 . 215 sampled on a first edge of the clock (-CLK) and the buffer amplifier 220 entered with low gain. The buffer amplifier 220 serves the samplers 210 . 215 and the bus input signals 200 . 205 to separate. On the next edge of the clock (CLK), the DATA and V _REF output signals are removed from the buffer amplifier 220 from the samplers 225 respectively. 230 sampled and to the sense amplifier 235 which amplifies the difference signal to a full minimum-to-maximum signal. Although a parasitic capacitance on the scanner 210 . 215 is present, which discharges its capacitive charge back on the bus lines, the amount of voltage is minimized, since only the low-level voltage is applied to the samplers and the amplifier and the high Minimum-to-maximum output thereof is isolated from the samplers.

On This is done by sampling the input signals in one first stage of the circuit, by transmitting the sampled input signals to a second stage of the circuit isolated from the first stage and by amplifying the input signals at this second stage a CMOS compatible receiver created, which fed the amount of the Noise on the bus minimized.

A preferred embodiment of the two-stage sampler / amplifier is in 4b shown. The sampling stage comprises the transistors M1 to M9 and the transmission gates T1, T2. In the first clock, which is when the clock (Clk) is low, the isolation transistors M5 and M6 are turned off and T1, T2 and M7 are turned on. M7 balances the drainage nodes of M3 and M4 and ensures that the drain-to-gate coupling for M3 and M4 is in common mode. The gate nodes of transistors M3 and M4 track the voltage on the bus DATA and the V _REF input signals. In the next clock, that is, when the clock signal goes high, the transmission gates T1, T2 are turned off and the transistor M1 and the transistors M5 and M6 are turned on. I1, an asymmetric delay element (ie it rises slowly from low to high and falls rapidly from high to low) is used to delay the turn-on of M5 and M6 until the nodes 100 and 105 balanced. This also ensures that each drain-to-gate coupling of M3 and M4 is in common mode. When M1 is turned on, power is provided to activate the differential amplifier consisting of the current sources M1, M2, the current control transistors M3, M4 and the load transistors M8, M9. The output signals of the differential amplifier are approximately equal to the input signals, DATA and V _REF with a low gain. The gain of the amplifier is deliberately kept low, preferably 1, to reduce the noise that is fed back to the input signals DATA and V _REF . When the isolation transistors M5 and M6 are turned on, the outputs of the differential amplifier of M3 and M4 become the nodes 100 . 105 transfer.

An object of the first stage of the circuit is to transmit the input differential voltage to the second stage, the cross-coupled sense amplifier consisting of transistors M10 to M16. Since the second stage is disconnected from the first stage when the isolation transistors are turned off, high drive voltage levels are not fed back to the DATA and V _REF input signals. While the clock signal is high, M16 is on. This serves to rebalance the sense amplifier after the previous clock signal, but also to short-circuit the differential voltage generated by the differential amplification stage of the circuit. However, the load transistors M8 and M9 are powerful enough that the bias level of the differential signal is kept above the threshold voltage of the transistor M16. In this way, M16 is somewhat resistive and the differential voltage can be recovered. When the clock signal transitions low, the cross-coupled sense amplifier is activated and the initial voltage differential is amplified to a fully-balanced output signal.

The resulting circuit provides a CMOS compatible receiver available which works on a high-speed current mode bus.

Claims (27)

Input receiver for sampling a first signal having a first voltage modulation with a first sampling circuit ( 210 . 215 ) with an input terminal coupled to receive the first signal from an external signal line, the first sampling circuit ( 210 . 215 ) for electrically coupling the external signal line to the input terminal in response to a first transition of a clock signal (Clk) and for electrically isolating the input terminal from the external signal line in response to a second transition of the clock signal (Clk), a first amplifier circuit ( 235 ), which is designed to amplify the first voltage modulation of the first signal into a second voltage modulation in response to a third transition of the clock signal (Clk), and a first separation circuit ( 220 ) connected between the first sampling circuit ( 210 . 215 ) and the first amplifier circuit ( 235 ) and for electrically disconnecting the first sampling circuit ( 210 . 215 ) from the first amplifier circuit ( 235 ) in response to the first transition of the clock signal (Clk) is configured. input receiver according to claim 1, wherein the first voltage level is less than is a volt, and wherein the second voltage drive is a CMOS voltage drive represents. An input receiver according to claim 1, wherein the first separation circuit ( 220 ) for providing the first signal for the first amplifier circuit ( 235 ) in response to the second transition of the clock signal (Clk) is configured. An input receiver according to claim 1, wherein the first sampling circuit ( 210 . 215 ) further comprising a differential amplifier having a first transistor (M3) coupled to the input terminal, a second transistor (M4) configured to receive a reference voltage (V _REF ) and a first terminal, the sources of the first and second transistors (M3, M4) are coupled to the first terminal. input receiver according to claim 4, wherein the differential amplifier in response to the second transition of the clock signal is activated. input receiver according to claim 5, wherein the differential amplifier further comprises a third and a fourth transistor (M2, M1) connected in series between the first connection and arranged a reference terminal are, wherein the third transistor (M2) a bias voltage and the fourth transistor (M3) receive the clock signal (Clk). input receiver according to claim 4, wherein an equalizing transistor (M7) is provided, between a drain of the first transistor (M3) and a drain electrode of the second transistor (M4) is arranged, wherein the tuning transistor (M7) for reducing the potential difference between the drains of the first and second transistors (M3, M4) depending from the first transition of the clock signal (Clk) is configured. Input receiver according to claim 1, wherein the first amplifier circuit ( 235 , M10-M16) has an equalizing transistor (M16) and an input terminal pair, the equalizing transistor (M16) being connected to the input terminal pair for reducing a potential difference between the input terminal pair of the first amplifier circuit (16). 235 ) in response to the second transition of the clock signal (Clk). Input receiver according to claim 1, wherein the first amplifier circuit ( 235 ) is activated in response to the third transition of the clock signal (Clk). An input receiver according to claim 1, wherein the first separation circuit ( 220 ) has a first and a second transistor (M5, M6), wherein in each case their gate electrode with the clock signal (Clk), respectively whose drain electrode with the first amplifier circuit ( 235 ) and respectively their source electrode with the first sampling circuit ( 210 . 215 ) are coupled. An input receiver according to claim 1, further comprising a second sampling circuit ( 210 . 215 ) having an input terminal coupled to receive the external signal line for receiving a second signal from the external signal line, for electrically coupling the external signal line to the input terminal of the second sampling circuit ( 210 . 215 ) in response to the second transition of the external clock signal and for electrically isolating the input terminal of the second sampling circuit ( 210 . 215 ) is formed by the external signal line in response to the third transition of the clock signal (Clk), a second amplifier circuit ( 235 ), and a second isolation circuit ( 220 ) connected between the second sampling circuit ( 210 . 215 ) and the second amplifier circuit ( 235 ) is arranged. input receiver according to claim 1, wherein both the second transition of the clock signal as also the third transition of the clock signal (Clk) during a first clock cycle of the clock signal (Clk) occur. Input receiver, with a first sampling circuit ( 160 . 210 . 215 ) for sampling first data from an external signal line in response to a first transition of a clock signal (Clk), a second sampling circuit ( 150 . 210 . 215 ) for sampling second data from the external signal line in response to a second transition of the clock signal (Clk), wherein both the first and the second transition of the clock signal occur during a first clock cycle of the clock signal (Clk), a first latch circuit (Clk). 160 . 220 ) connected to the first sampling circuit ( 160 . 210 . 215 ) is coupled to the latching of the first data in response to the second transition of the clock signal (Clk), and a second latch circuit ( 150 . 220 ) connected to the second sampling circuit ( 150 . 210 . 215 ) is coupled to the latching of the second data in response to a third transition of the clock signal (Clk). An input receiver according to claim 13, further comprising a first isolation transistor (M5) connected between said first sampling circuit (M5). 160 . 210 . 215 ) and the first latch circuit ( 160 . 220 ), wherein the first isolation transistor (M5) is configured to separate the first data from the input of the first latch stage in response to the second transition of the clock signal (Clk), and a second isolation transistor (M5) connected between the second sampling circuit (M5). 150 . 210 . 215 ) and the second latch circuit ( 150 . 220 ), wherein the second isolation transistor (M5) is configured to separate the second data from the input of the second latch in response to the third transition of the clock signal (Clk). An input receiver according to claim 13, wherein the first sampling circuit ( 160 . 210 . 215 ) a first differential amplifier having first and second inputs, the first input being for receiving the external signal line and the second input being coupled to a reference voltage (V _REF ) and having a second differential amplifier having a first and a second input, wherein the first input is for receiving the external signal line and the second input is coupled to the reference voltage (V _REF ). An input receiver according to claim 13, wherein the first sampling circuit ( 160 . 210 . 215 ) in response to the first transition of the clock signal and the second sampling circuit ( 150 . 210 . 215 ) are activated in response to the second transition of the clock signal. An input receiver according to claim 13, further comprising a first equalization transistor (M7) connected to an output terminal pair of said first sampling circuit (M7). 160 . 210 . 215 ) is connected for reducing a potential difference at the output terminal pair of the first sampling circuit ( 160 . 210 . 250 ) in response to the second transition of the clock signal (Clk), and a second equalization transistor (M7) connected to an output terminal pair of the second sampling circuit (Clk). 150 . 210 . 215 ) is connected for reducing a potential difference at the output terminal pair of the second sampling circuit ( 150 . 210 . 215 ) in response to the third transition of the clock signal (Clk). An input receiver according to claim 13, further comprising a first equalization transistor (M16) connected to an input terminal pair of the first latch circuit (M16). 160 . 220 ) is connected for reducing a potential difference at the input terminal pair of the first latch circuit ( 160 . 220 ) in response to the first transition of the clock signal (Clk) and a second equalization transistor (M16) connected to an input terminal pair of the second latch circuit (Clk). 150 . 220 ) is connected for reducing a potential difference at the input terminal pair of the second latch circuit ( 150 . 220 ) in response to the second transition of the clock signal (Clk). An input receiver according to claim 18, wherein the first latch circuit ( 160 . 220 ) in response to the second transition of the clock signal and the second latch circuit ( 150 . 220 ) is activated in response to the third transition of the clock signal (Clk). System with a master device ( 10 ), a slave device ( 30 . 35 . 40 . 45 ) and one between the master device ( 10 ) and the slave device ( 30 . 35 . 40 . 45 ) arranged signal line ( 5 ), whereby the master device ( 10 ) for receiving a resulting signal from the slave device ( 30 . 35 . 40 . 45 ) via the signal line ( 5 ), the resulting signal having an amplitude due to a sum of the amplitudes of a signal transmitted by the slave device ( 30 . 35 . 40 . 45 ) received an incoming signal and one by a reflection of the incoming signal at a first end ( 25 ) of the signal line ( 5 ) has generated reflected signal. A system according to claim 20, wherein a closure element ( 55 ) provided with a second end ( 50 ) of the signal line ( 5 ), the master device ( 10 ) near the first end ( 25 ) of the signal line ( 5 ) is arranged. A system according to claim 20, wherein the slave device ( 30 . 35 . 40 . 45 ) transmits the incoming signal by sending a predetermined amount of current from the signal line ( 5 ) consumed. Method for receiving a plurality of data with a first input sampler ( 210 . 215 ) and a second input sampler ( 210 . 215 ) for receiving an external data line, comprising the steps of sampling first data in a first sampling circuit ( 160 . 210 . 215 ) in response to a first transition of a clock signal (Clk), sampling of second data in a second sampling circuit ( 150 . 210 . 215 ) in response to a second transition of a clock signal (Clk), latching the first data in a first latch circuit ( 160 . 220 ) in response to the second transition of the clock signal (Clk), and latching of the second data in a second latch circuit (FIG. 150 . 220 ) in response to a third transition of the clock signal (Clk), the second and third transitions of the clock signal (Clk) occurring within a first clock cycle of the clock signal (Clk). The method of claim 23, further comprising the steps of electrically disconnecting the first sensing circuit (16). 160 . 210 . 215 ) from the external signal line in response to the first transition of the clock signal (Clk), and electrically disconnecting the second sampling circuit (FIG. 150 . 210 . 215 ) from the external signal line in response to the second transition of the clock signal (Clk). The method of claim 23, further comprising the steps of electrically disconnecting the first latch circuit (16). 160 . 220 ) from the first sampling circuit ( 160 . 210 . 215 ) in response to the second transition of the clock signals (Clk), and electrically disconnecting the second latch circuit ( 150 . 220 ) from the second sampling circuit ( 150 . 210 . 215 ) in response to the third transition of the clock signal (Clk). The method of claim 23, further comprising the steps Reinforce the first data in dependence from the second transition of the clock signal and strengthen the second data in dependence from the third transition of the clock signal (Clk). The method of claim 23, further comprising the steps of reducing a potential difference of an input terminal pair of said first latch circuit (16). 160 . 220 ) in response to the first transition of the clock signal (Clk), and reducing a potential difference of an input terminal pair of the second latch circuit (FIG. 150 . 220 ) in response to the second transition of the clock signal (Clk).