DE4430811C1 - Ion-sensitive FET prodn., useful for mfg. integrated liq. sensor circuit - Google Patents

Abstract

ISFET prodn. involves (a) structuring source, drain and ion-sensitive gate regions; (b) depositing a silicon oxide-silicon nitride double layer (12a, 12b) as gate insulator (12); (c) forming contact openings in the double layer above the source and drain regions; (d) depositing and structuring conductor lines (24, 28) which directly contact the source and drain regions; (e) depositing an insulating surface planarising layer (26, 26', 30); (f) etching a trench extending down to the double layer above the source and drain regions respectively adjacent the ion-sensitive region; (g) depositing a silicon carbide layer (38); and (h) etching a cavity (40) which is enclosed by the trench and which extends down to the double layer (12a, 12b) above the ion-sensitive region.

Description

The present invention relates to a method for producing provide an ion-sensitive field effect transistor.

In particular, the present invention relates to a manufacture method for an integrated liquid sensor scarf Field effect transistor based detection of ions in the sample liquid to be examined. typically, become such integrated liquid sensor circuits with ion-sensitive field effect transistors (ISFET) reali siert, those for signal evaluation, an evaluation circuit which MISFETs (Metal Insulator Semiconduc Gate Field Effect Transistor).

Typically, in such integrated liquid keitssensorschaltungen the sample liquid via a sepa rate reference electrode to a defined potential ge sets, whereby the ions contained in it, the example can be H⁺ ions, at the sensor surface a Form charge. This effects as well as the gate potential in a MOS transistor within the ISFET an elektri nice field, which causes the field effect. In a Be The ISFET can measure its gate-source voltage which use a calibration characteristic for each ISFET has an assignment of the ion concentration in the Liquid allows, for example, in the case of H⁺ ions is the pH. For detection of other ions can Ionophores or other layers on the surface of the ISFET be used.  

Is the active gate area of the ISFET with a biological or biochemical membrane, the ISFET can be used as a Biosensor for the detection of biological and / or biochemical Substances are used in the liquid. These substances bring with the help of biological components, such as For example, microbes, or with the help of biochemical acting components, such as enzymes, antibodies perceptors, etc., physical effects that in turn, directly or indirectly via further Zwischenreak Within the sensors an electrical output nal as the gate-source voltage of the ISFET.

The German patent application DE 41 15 397 A1 shows a Method of manufacturing a CMOS integrated circuit with an ISFET and with an evaluation MISFET in Polysi liziumtechnologie.

This known method is structured in a silicon subculture strat a drain region, a source region and a ion-sensitive gate region. On the substrate, a Si silicon dioxide / silicon nitride double layer as a gate insulator deposited, and after forming Kontaktierungsöff tions in the silicon dioxide layer / silicon nitride double layer above the drain or source region Tracks are deposited and structured.

In this known method is used to define the Flüs generates a mask, which is the structure tion of a photopolymer layer, with which the entire Surface of the integrated circuit is covered. With help the mask formed by the photopolymer layer 18 becomes the active sensor area is opened from the one during the Semiconductor process required TEOS protective layer 11 by Etching is removed. The photoresist or the photopolymer However, layer remain on the surface of the integrated th circuit as an additional passivation layer.  

The disadvantage of this known method is that the passivation layers used are not satisfactory Dense edge coverage, an unsatisfactory chemical Re resistance and low mechanical stability. Furthermore, these passivation layers show no so-called Biocompatibility, and thus enable no sensor use in biotechnology or medical technology.

From the technical literature L. Bousse, et al., "A Process for the Combined Fabrication of Ion Sensors and CMOS-Cir cuits ", IEEE Electron Device Letters, Volume 9, Number 1, Yes nann 1988, pages 44 to 46 is already a procedure for Create a CMOS integrated circuit with an ISFET and with an evaluation MISFET in polysilicon gate techno known. In this procedure, Isola tion areas to delineate the individual components under generated each other, then having a gate oxide layer the gate insulator is formed, whereupon a polysilicon gate created and structured. Subsequently, Source and realized drain of the field effect transistors. Now the active gate region of the ISFET is exposed, whereupon a passivation layer is applied. In the well-known th integrated circuit consists of the gate insulator finally made of silicon dioxide. Both in the ISFET as also in the MISFET of the integrated circuit is the poly silicon region above the gate oxide layer. The MISFET has insulation above the polysilicon gate layer of a low-temperature oxide, which is on Sei the ISFET in the area of the polysilicon gate a Ausneh having mung. The integrated circuit shows as off closing passivation layer a silicon nitride layer in the area of the MISFET above the Niedertempera turoxids lies in the area of the ISFET up to its Polysilicon gate extends. This results in under different electrical properties of the MISFET and the ISFET of the integrated circuit, so that at this inte grated circuit is not possible, a largely of Disturbance free measurement signal to get.  

The following references are also mentioned for the technological background of the invention:
D. Harame, et al., "An Implantable Ion Sensor Transducer" Proceeding "IEDM", 1981;
J. Kimura, et al., "An Integrated SOS / FET Multi-Biosensor" Sensors and Actuators, 9 (1986), pages 373-387; and
K. Tsukada, et al., "A Multiple-ChemFET Integrated with CMOS Interface Circuits" Proceeding "Transducers'87", 1987.

Based on the above-appreciated prior art the present invention based on the object, a Ver drive to produce an ion-sensitive field effect to create a sistor in which the passivation of the field Effect transistor used a good Kantenbe Coverage, high chemical resistance and high mecha nische stability, and also a Biocompatibili to use the sensor in biotechnology or medicine zintechnik has.

This object is achieved by a method with the in patent solved claim 1 features.

The present invention provides a method for manufacturing ment of an ion-sensitive field-effect transistor, the fol having the following process steps:

• - Structure of a drain region, a source region and an ion-sensitive gate region;
• - depositing a silicon dioxide-silicon nitride double layer as a gate insulator;
• - Forming contact holes in the Siliziumdi oxide silicon nitride bilayer above the drain  area and the source area;
• Depositing and structuring of printed conductors, the Contact drain region and source region directly;
• - depositing an insulating surface leveling layer;
• - Etching a trench that extends to the silicon di oxide silicon nitride bilayer above the drain and the source region adjacent to the ion extends sensitive area;
• - depositing a silicon carbide layer;
• - etching a recess enclosed by the trench, the up to the silicon dioxide-silicon nitride double layer above the ion-sensitive region he stretches.

Preferred embodiments of the present invention are defined in the subclaims.

The advantage of the present invention is that by using the silicon carbide as a passivation material in the above process the properties good edge coverage, high chemical resistance tenz, a high mechanical stability and a biocom compatibility and thus also the sensor application in biotechnology and medical technology.

Another advantage of using the silicon carbide as Passivation in the above method is that the silicon carbide passivation starting at the flanks of the sensitive ISFET region emanating from the gate insulator the protection against the ingress of liquids away sets and thus all chip areas including the Includes aluminum conductors.  

Another advantage of the present invention is there rin that the use of the trench etching technique in the above mentioned method in the "superstructure" of the sensor a Verkapse With a silicon carbide passivation layer made possible light, creating an unrestricted short-circuit protection of the electronic component when operating in liquids is guaranteed.

Yet another advantage of using the silicon karbidsals passivation in the above-mentioned method be is that by the thus enabled encapsulation technology, which on the flanks of the sensitive ISFET Be reichs begins, the associated source / drain areas unmit contact the active sensor surface with aluminum can be. As a result, the electrical Characteristics of the device improved, since the influence of Rail resistors along the source / drain regions themselves mi and the long feed diffusion paths to the source and drain area with the compared to aluminum minium by a factor of 1000 to 5000 higher specific wi derstand can be omitted. As a result, the design becomes compact ter and the integration density increases.

Yet another advantage of the present invention is that through the passivation technology means Silicon carbide in the above method additional Degrees of freedom opened in the housing of the device because all electronic areas are liquid are tightly covered. Consequently, after the separation of the Chips only the exposed chip edges and the An include closing contact surfaces by a housing. Therefore can the housing application-related (for example, by Connectors for system solutions) as well as inexpensive, automatic procedures.

Compared to those mentioned in the introduction Writings of L. Bousse, D. Harame, J. Kimura and K. Tsukada  the present invention has the following Advantages.

The process order and design according to the invention According to the method allows simultaneous production of ISFET structures and conventional devices in CMOS Technology, such as field effect transistors.

Furthermore, integration of the ISFETs in both n-channel as well as in p-channel design equally possible.

There is no expensive use of an SOS structure (Sili con on sapphire) necessary.

The simultaneous integration of ISFET and CMOS components to operational amplifiers and signal processing On-chip circuits, for example, allow for users microsystem technology solutions.

By the realization of the double-layer gate insulator so probably with the ISFETs as well as with the MISFETs (ie the her conventional transistors), which are made of a pH-sensitive Si₃N₄ layer on a leveling layer SiO₂ consists, agree the electrical properties of both components with respect to their threshold voltage and gate insulator charge reason of the identical interfaces. Consequently are the ISFET and the MISFET are integrated in the same way.

A self-adjustment of the channel area facing sour ce and drain edges are used for channel length adjustment polysilicon gate technology in the MISFET and the ISFET, wherein the polysilicon gate in the course of the process is removed and thus a flat sensor surface rea is lisiert.

All layers covering the active sensor surface become exclusive for reasons of greater selectivity by a wet-chemical etching and thus by a  Gate insulator "gentle" etching process locally removed.

To protect the gate insulator remains after etching the Polysilicon gates a CVD oxide layer to the end of the process consist, for example, the contact with photoresist or etching plasma and solutions is avoided and consequently Damage to the gate insulator is prevented.

The inventive method used in the ISFET Her a two-layer metallization with aluminum.

To achieve miniaturization of the transducer, the large-volume glass reference electrode by a in replaced solution contact made of gold, on the Chip front side in the immediate vicinity of the ISFET structured becomes.

A preferred embodiment of the present invention The following is made with reference to the appended Drawings explained in more detail. Show it:

Fig. 1a-1c is a flow chart of the procedural inventive method;

FIGS. 2a-12b-sectional illustrations of exemplary inte ter circuits according to the invention in each case after execution of individual process stages of the procedure according to the invention, with the figures labeled A to an n-channel circuit and the figures indicated by b refer to a p-channel device ,

The abbreviations used in the following description Gen are now described with reference to Tables 1 and 2.  

Table 1

Table 1 gives the for the different method masks used, their designations and their respective task.

No. process module 1 Tub technology and component definition 2 Channel stopper technology and field oxidation 3 Gate insulator and polysilicon gate technology 4 Source / drain technology 5 Definition of active sensor areas 6 Contact technology and first metallization level 7 Connection technology and second metallization level 8th Definition of the solution contacts 9 Passivierungstechnologie 10 Exposing the active sensor areas

Table 2 defines the individual process modules which is referred to in the description.

In the following description of the embodiment of this method according to the invention reference is made at the same time to the flowchart of Fig. 1 and the Querschnittsdar positions of the semiconductor structure of the invention in tegrierten CMOS circuit according to FIGS . 2a to 12b.

The inventive method uses as Ausgangsma Material of a silicon wafer with a crystal orientation of ⟨100⟩ doped with phosphorus.

Fig. 2a, 2b show the component classification for the MISFET, the ISFET and in the case of Fig. 2b an inte gr th solution contact.

The process module 1 , which comprises the process steps 1 to 12, will be described below with reference to FIGS . 3a, 3b.

In method step 1, the silicon wafer 2 is thereafter oxidized for the well technology and for the definition of the components. The photomask PW (see Table 1) defines the p-well regions 4 ( FIG. 3 b) in method step 2 as the base material for n-channel transistors and sensors. After carried out in step 3 Ionenim plantation with boron and the removal of the photoresist in Ver procedural step 4 is followed in step 5, the tub collection to before the tub oxide in procedural step 6 is wet etched.

The LOCOS technology is used to define the components. Following a thermal prenitride oxidation 6 , which is carried out in method step 7, the deposition of a polysilicon layer 8 and an LPCVD silicon nitride layer 10 follows immediately thereafter in method steps 8 and 9. With the OD mask, the active regions are defined in method step 10, and the silicon nitride layer 10 is patterned in method step 11 by a dry etching process.

Now, for the description of the process module 2 (see Table 2), which comprises the method steps 13 to 28, reference is made to FIGS. 4a, 4b.

With renewed use of the PW mask 13 so-called "n-channel stopper" 5 are realized in the process step. In method step 14, in order to increase the field threshold voltage, boron is implanted in the well regions, wherein the parameter setting only allows the ions to be introduced into the silicon nitride-free regions.

After the photoresist has been removed in step 15, the process step is repeated in the regions inverse to the n-wells. For this purpose, the PWI mask (process step 16) serves as a mask for the process step 17 by guided ion implantation with phosphorus. This ion implantation serves to increase the field threshold voltage in the silicon nitride-free substrate region ("p-channel stopper" 7 ). In method step 18, the photoresist is removed.

In a conducted in process step 19 Feuchtoxi dation grows locally a field oxide, wherein a thin polysilicon layer is aufoxidiert. The resulting from the Feuchtoxi dation oxynitride is removed in step 20 by a wet chemical etching, so that in the process step 21 and 22, the silicon nitride and poly silicon layer 8 , 10 (see FIG. 3) can be dry etched. The resulting in the local oxidation at the top of the "Bird's beak" thin nitride layer, which can lead to early breakthrough in the gate oxide is converted in the process step 23 by an SAC oxidation (SAC = Sacrificial Oxide) in an oxide.

In method step 24, in turn, the PWI mask is used to cover the p-well regions 4 ( FIG. 3b) with photoresist. Successively implanted in the Substratge area Phospor and boron. This increase in the dopant concentration by means of phosphorous in the near-surface region of a transistor, the expansion of the source and drain space charge zones is reduced and thus an unwanted wished contact these zones avoided ("punch-through effect"). This is carried out in method step 25. By means of the Borim plantation carried out in step 26, the threshold voltage of the p-channel transistors with respect to the n-channel transistors is set symmetrically to the zero point. After the photoresist in the process step 27 is removed, the above-described sacrificial layer ("sacrificial oxides") is wet etched in step 28.

In Fig. 4a, 4b, the structures at the end of the process module 2 are shown.

The process module 3 , which summarizes the method steps 29 to 36, will be described below with reference to FIGS. 5a, 5b.

According to the present invention, the gate insulator 12 is realized as a double layer consisting of silicon dioxide 12 a and silicon nitride 12 b. In contrast to oxide, nitride as the uppermost layer of the gate insulator is hydrophobic and prevents absorption of H + ions, which - built into the gate insulator - would distort the sensor measurement result. However, since the adhesion of silicon nitride (Si₃N₄) is limited to silicon by mechanical stresses, silicon dioxide (SiO₂) is used as an intermediate layer. In addition, this reduces the impurity density at the interface between silicon and silicon dioxide. Following a gate oxidation carried out in method step 29, a gate oxide layer 12 a with a typical gate oxide thickness of 25 to 30 nm is formed, and then a typically 70 nm thick silicon nitride layer 12 b is deposited by means of the LPCVD technique in method step 30. This is followed by a polysilicon layer 14 is deposited in the LPCVD reactor in step 31, and in the process step 32 doped by an occupancy and diffusion process in a POCl₃ furnace with Phospor.

To produce the polysilicon interconnects and the gate electrodes are after the process step 33 applied phototechnology PS polysilicon layer 14 in the procedural step 34 procedurally structured and subsequently sequent step 35, the photoresist is removed. By using this polysilicon gate technology, the source / drain regions of the transistors and the sensors in the n-channel and p-channel embodiments can be doped by means of ion implantation in a self-aligned technique. Here, the structured Polysili ziumschicht 14 serves as a mask and their structural edges are transmitted to the source and drain regions. Instead of the otherwise usually carried out dry etching of the poly silicon structure 14 , whereby steeper etching edges achieved who can, in favor of a selective Ätzstops on the gate nitride layer 12 b, a corresponding wet chemical etching process must be used. However, in order simultaneously to minimize undersaturation of the source / drain regions in the channel region and to protect the gate electrodes 14 from penetrating into the implanted ion, the polysilicon layer 14 is oxidized in method step 36. Due to the IN ANY nitride surface 12 b, the oxide 16 grows only on the polysilicon 14 on.

The structures at the end of the process module 3 are shown in FIGS. 5a, 5b.

In the following, the process module 4 will be described with reference to FIGS. 6a, 6b, which includes the method steps 37 to 48.

Using the SN mask, the areas of the p-channel transistors are covered in method step 37 and the LDD source / drain islands (LDD = lightly doped drain) of the n-channel transistors and sensors are implanted in method step 38 , After removal of the photoresist in the process step 39, a CVD oxide layer 18 is deposited over the entire surface in the process step 40 and then in Ver procedural step 41 etched so anisotropically that the edges of the polysilicon gate 14 are covered with the oxide 18 ("spacer" = spacing) , Subsequently, in the process step 42, the SN phototechnology, in step 43, the ion implantation (in this case with arsenic) to generate the source / drain regions and in step 44 Entfer the voltage of the photoresist repeated. The spacer width and thus the thickness of the CVD oxide layer 18 are adapted to the parameters of the ion implantation such that an overlap of the source / drain regions with the LDD regions is ensured by Unterdiffu sion.

Subsequently, in method step 45 and 46 under Ver Applying the SP mask carried out a Borimplantation where through the source / drain islands for the p-channel MISFETs and ISFETs are formed.

FIGS. 6a and 6b show the structures after the removal of the photoresist and the annealing, which is carried out in method steps 47 and 48, respectively.

This is the realization of the device level in silicon completed. The MISFETs and ISFETs were used during the carried out the previous procedure identical. In the night following is the structuring of the "semiconductor superstructure" described for the sensors as well as the metallization.

The process module 5 , which includes the method steps 49 to 55, will be described below with reference to FIGS. 7a, 7b.

By means of the phototechnology SO, the active sensor FET areas are defined in method step 49, the active sensor FET areas being those areas in which the gate insulator 12 comes into contact with the sample liquid above the channel area and effects the field effect , For this purpose, successively in process step 50 and 51, the oxide and polysilicon layer 14 , 16 of the polysilicon gate, which is net angeord above the active sensor FET area, etched wet chemically, whereby the gate insulator is exposed. Then, in step 52, the photoresist is removed. Subsequently, in method step 53, an oxide layer 20 is deposited on the entire surface by CVD deposition. This serves to protect the Gateiso lators in the active sensor area (for example, to protect against possible polymerization reactions with photoresists or as Ätzstopschicht) and remains there until the end of the process.

In method step 54, the wafer rear side is etched, to enable the use of the getter process. The Getter method is used to clean the semiconductor of Heavy metal or alkali ions, such as Na⁺. Out This reason will be sequential on the back etched the CVD layer, the gate nitride and gate oxide layers. Subsequently, in step 55, the gettering with POCl₃, whereby the last high-temperature step before Me tallization and passivation is performed.

FIGS. 7 a, 7 b show the structures after completion of the process module 5 .

The process module 6 , which comprises the method steps 56 to 64, will be described below with reference to FIGS. 8a, 8b.

In step 56, the structure with respect to the contact holes 22 is determined based on the CO mask. These contact holes lead to the source / drain regions. In the procedural step 57, 58, 59, the oxide layer 20 , the gate nitride layer 12 b and the gate oxide layer 12 a are etched dry and thus anisotropically to realize the contact holes. After removal of the paint in step 60 Alumi is nium 24 deposited before in step 62 with the help of the photo technology ME1 the tracks of the first Me tallebene and contact pads ("bond pads") in the process step Ver 63 are dry etched. Finally, the photoresist is removed in method step 64.

FIGS. 8a, 8b show the structures after completion of the process module 6 .

The following is the description of the process module 7 , which includes the Ver process steps 65 to 75, with reference to FIGS . 9a, 9b.

The optional connection technology to be integrated and the second metallization level utilizes a PECVD oxide layer 26 applied in process step 65 for surface planarization.

In process steps 66 and 67, the oxide layer 26 for the contacting of the first metal level is etched dry via the VIA mask, in step 68 the photoresist is removed and in step 69 aluminum 28 is applied for the second metal level. The phototechnology ME2 used in method steps 70 and 71 serves for structuring of these printed conductors. Once the photoresist is removed in process step 72, in process step 73, an alloy joins in a forming gas. In order to protect the aluminum from corrosion and for further surface planarization, a further PECVD oxide layer 26 'and a PECVD nitride layer 30 are deposited one after the other in method steps 74 and 75.

In Fig. 9a, 9b, the structures after completion of the pro zeßmoduls 7 are shown.

Hereinafter, the process module 8 will be described with reference to FIGS. 10a, 10b, which includes the process steps 76 to 79 a.

The integrated solution contact (which can optionally be provided), which brings the sample liquid to a defined potential and replaced due to its miniaturization an additionally required reference electrode, is prepared in structured gold. Due to the desired compatibility with the CMOS process, the integration after the deposition of the plasma layers 26 , 26 ', 30 is performed. As a result, a contact with the aluminum webs avoided the, as well as a negative temperature gradient in the single process manufacturing met.

In contrast to the other layers, this new metalization level is only limited to the solution contact, the associated trace to the terminal pad and the terminal contact surface itself. In order to avoid deposition of gold and the associated danger of outdiffusion, the phototechnology LK is used in method step 76, which is also referred to as "lift-off technique". In this case, the thickness of the deposited on the silicon wafer hurled photoresist is larger than that of the metallization dimensioned, so that the metallization already tears during the manufacturing process at the lacquer edges. For this purpose, in step 77, nickel 32 is deposited as an adhesive material abge, before in step 78 with the same process gold 34 is applied to the silicon wafer. When removing the lacquer in method step 79, the metal layers on the sem are also removed.

FIGS. 10 a, 10 b show the structures after completion of the process module 8 .

With reference to FIGS . 11 a, 11 b, the process module 9 will now be described, which includes the method steps 80 to 84.

To the sensor device outside the sensitive area liquid-tight to housings and thus even agressi to protect the fluid, the device with a suitable passivation are covered. The invention The appropriate method uses silicon carbide for this purpose.

After the phototechnology VE used in step 80, the plasma oxide layer 26 , 26 'and the plasma nitride layer 30 are removed at the flanges of the sensitive channel region of the ISFET in the form of trenches (trenches) 36 in method steps 81 and 82. As soon as the photoresist has been removed in process step 83, a PECVD silicon carbide layer 38 is deposited on the component in method step 84 over the entire surface, closing the etched trenches 36 and consequently protecting the hydrophilic insulator layers 20 , 26 , 26 ', 30 as well as the Protection of the metal tracks 24 , 28 allows.

The structures resulting after the execution of the process module 9 are shown in FIGS. 11a, 11b.

This passivation process allows for improvement of the ISFET design, since now to increase the electric Properties (reduction of the track resistance of Source and drain) contacting the source and drain means the tracks can be made directly on the ISFET itself.

The process module 10 will now be described with reference to FIGS . 12a, 12b, which includes the method steps 85 to 89.

In method steps 85 and 86, the active sensor region 40 is opened by means of the phototechnology of the PA mask, and, in the case of the structure from FIG. 12 b, the integrated solution contact 42 opens. After removing the photoresist in the process step 87, the plasma nitride and plasma oxide layer 30 , 26 , 26 'as well as the required during the semiconductor manufacturing process CVD oxide protective layer 20 selectively wet etched down to the gate nitride layer 12 b in step 88 and 89.

Figures 12a, 12b show the completed devices MISFET and ISFET in their n-channel and p-channel designs after removal of the photoresist.

Finally, it should be noted that in the above be written embodiment all Lithographiepro  zesse use the positive coating process, in which the be Photoresist areas were cleared by the development process be replaced.

Claims (7)

1. A method for producing an ion-sensitive field effect transistor, characterized by the following method steps:

• - structuring a drain region, a source region and an ion-sensitive gate region;
• - depositing a silicon dioxide-silicon nitride double layer ( 12 a, 12 b) as a gate insulator ( 12 );
• - Forming of contacting openings ( 22 ) in the Si silicon dioxide silicon nitride bilayer ( 12 a, 12 b) above the drain region and the Sourcebe rich;
• - depositing and patterning conductor tracks ( 24 , 28 ) which directly contact the drain region and the source region;
• - depositing an insulating surface leveling layer ( 26 , 26 ', 30 );
• - etching a trench (36) extending up to the Si liziumdioxid-silicon nitride double layer (12 a, 12 b) adjacent extends above the drain region or the Sourcebe kingdom to the ion-sensitive portion;
• - depositing a silicon carbide layer ( 38 ); and
• - Etching of one of the trench ( 36 ) encompassed recess ( 40 ) extending to the silicon dioxide silicon nitride bilayer ( 12 a, 12 b) above the ion-sensitive region.

2. The method according to claim 1, characterized that patterning by photolithographic pro Zesse takes place. 3. The method of claim 1 or 2, characterized in that the deposition of the insulating Oberflächenplanari sierungsschicht the deposition of a PECVD oxide layer ( 26 , 26 ') and a PECVD nitride layer ( 30 ). 4. The method according to any one of claims 1 to 3, characterized in that the etching of the trench ( 36 ) takes place by a dry etching process. 5. The method according to any one of claims 1 to 4, characterized in that the deposition of the silicon carbide layer from the deposition of PECVD silicon carbide ( 38 ). 6. The method according to any one of claims 1 to 5, characterized in that the etching of the region of the trench ( 36 ) Be rich done by a wet chemical etching process. 7. The method according to any one of claims 1 to 6, characterized in that before forming the contacting openings ( 22 ) an oxide layer ( 20 ) on the silicon dioxide-silicon nitride double layer ( 12 a, 12 b) is deposited by a CVD process ,