DE50209514D1 - Verfahren zur Herstellung eines Silizium-Wafers - Google Patents
Verfahren zur Herstellung eines Silizium-WafersInfo
- Publication number
- DE50209514D1 DE50209514D1 DE50209514T DE50209514T DE50209514D1 DE 50209514 D1 DE50209514 D1 DE 50209514D1 DE 50209514 T DE50209514 T DE 50209514T DE 50209514 T DE50209514 T DE 50209514T DE 50209514 D1 DE50209514 D1 DE 50209514D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- silicon wafer
- wafer
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE50209514T DE50209514D1 (de) | 2001-05-16 | 2002-05-04 | Verfahren zur Herstellung eines Silizium-Wafers |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10124030A DE10124030A1 (de) | 2001-05-16 | 2001-05-16 | Verfahren zur Herstellung eines Silizium-Wafers |
| DE50209514T DE50209514D1 (de) | 2001-05-16 | 2002-05-04 | Verfahren zur Herstellung eines Silizium-Wafers |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE50209514D1 true DE50209514D1 (de) | 2007-04-05 |
Family
ID=7685132
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE10124030A Withdrawn DE10124030A1 (de) | 2001-05-16 | 2001-05-16 | Verfahren zur Herstellung eines Silizium-Wafers |
| DE50209514T Expired - Lifetime DE50209514D1 (de) | 2001-05-16 | 2002-05-04 | Verfahren zur Herstellung eines Silizium-Wafers |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE10124030A Withdrawn DE10124030A1 (de) | 2001-05-16 | 2001-05-16 | Verfahren zur Herstellung eines Silizium-Wafers |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6716721B2 (de) |
| EP (1) | EP1258919B1 (de) |
| DE (2) | DE10124030A1 (de) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10124038A1 (de) | 2001-05-16 | 2002-11-21 | Atmel Germany Gmbh | Verfahren zur Herstellung vergrabener Bereiche |
| JP2005064188A (ja) * | 2003-08-11 | 2005-03-10 | Sumitomo Electric Ind Ltd | 基板の回収方法および再生方法、ならびに半導体ウエハの製造方法 |
| US7696058B2 (en) * | 2007-10-31 | 2010-04-13 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
| FR2980916B1 (fr) * | 2011-10-03 | 2014-03-28 | Soitec Silicon On Insulator | Procede de fabrication d'une structure de type silicium sur isolant |
| US9209345B2 (en) | 2013-06-29 | 2015-12-08 | Sionyx, Inc. | Shallow trench textured regions and associated methods |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3974006A (en) * | 1975-03-21 | 1976-08-10 | Valentin Rodriguez | Method of obtaining high temperature resistant assemblies comprising isolated silicon islands bonded to a substrate |
| DE2535813C2 (de) * | 1975-08-11 | 1980-11-20 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zur Herstellung einkristalliner Schichten aus Halbleitermaterial auf einer elektrisch isolierenden Unterlage |
| JP3237888B2 (ja) * | 1992-01-31 | 2001-12-10 | キヤノン株式会社 | 半導体基体及びその作製方法 |
| US5234535A (en) * | 1992-12-10 | 1993-08-10 | International Business Machines Corporation | Method of producing a thin silicon-on-insulator layer |
| JP2980497B2 (ja) * | 1993-11-15 | 1999-11-22 | 株式会社東芝 | 誘電体分離型バイポーラトランジスタの製造方法 |
| US5583059A (en) | 1994-06-01 | 1996-12-10 | International Business Machines Corporation | Fabrication of vertical SiGe base HBT with lateral collector contact on thin SOI |
| JP3250721B2 (ja) * | 1995-12-12 | 2002-01-28 | キヤノン株式会社 | Ｓｏｉ基板の製造方法 |
| DE19609933A1 (de) | 1996-03-14 | 1997-09-18 | Daimler Benz Ag | Verfahren zur Herstellung eines Heterobipolartransistors |
| KR100218347B1 (ko) | 1996-12-24 | 1999-09-01 | 구본준 | 반도체기판 및 그 제조방법 |
| US6155909A (en) * | 1997-05-12 | 2000-12-05 | Silicon Genesis Corporation | Controlled cleavage system using pressurized fluid |
| US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
| US6413874B1 (en) * | 1997-12-26 | 2002-07-02 | Canon Kabushiki Kaisha | Method and apparatus for etching a semiconductor article and method of preparing a semiconductor article by using the same |
| JP3218564B2 (ja) * | 1998-01-14 | 2001-10-15 | キヤノン株式会社 | 多孔質領域の除去方法及び半導体基体の製造方法 |
| US6057212A (en) * | 1998-05-04 | 2000-05-02 | International Business Machines Corporation | Method for making bonded metal back-plane substrates |
| JP2000124092A (ja) * | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ |
| FR2784800B1 (fr) | 1998-10-20 | 2000-12-01 | Commissariat Energie Atomique | Procede de realisation de composants passifs et actifs sur un meme substrat isolant |
| DE10124032B4 (de) | 2001-05-16 | 2011-02-17 | Telefunken Semiconductors Gmbh & Co. Kg | Verfahren zur Herstellung von Bauelementen auf einem SOI-Wafer |
| DE10124038A1 (de) | 2001-05-16 | 2002-11-21 | Atmel Germany Gmbh | Verfahren zur Herstellung vergrabener Bereiche |
-
2001
- 2001-05-16 DE DE10124030A patent/DE10124030A1/de not_active Withdrawn
-
2002
- 2002-05-04 DE DE50209514T patent/DE50209514D1/de not_active Expired - Lifetime
- 2002-05-04 EP EP02010015A patent/EP1258919B1/de not_active Expired - Fee Related
- 2002-05-13 US US10/145,169 patent/US6716721B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE10124030A1 (de) | 2002-11-21 |
| EP1258919A3 (de) | 2005-03-16 |
| US20020173119A1 (en) | 2002-11-21 |
| EP1258919A2 (de) | 2002-11-20 |
| US6716721B2 (en) | 2004-04-06 |
| EP1258919B1 (de) | 2007-02-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE60022857D1 (de) | Verfahren zur Herstellung eines Halbleiterbauelements | |
| DE60038423D1 (de) | Verfahren zur Herstellung eines Halbleiterbauelements | |
| DE60212699D1 (de) | Verfahren zur herstellung eines verbundes | |
| DE60327721D1 (de) | Verfahren zur Herstellung eines Halbleiterbauelements | |
| DE602006011362D1 (de) | Verfahren zur herstellung eines (110) silizium-wafers | |
| DE50214957D1 (de) | Verfahren zur Herstellung eines Trägermaterials für eine Spiegelschicht | |
| DE60135992D1 (de) | Verfahren zur herstellung von silizium-einkristall-wafer | |
| DE60219497D1 (de) | Verfahren zur herstellung von silicium | |
| DE60231787D1 (de) | Verfahren zur herstellung eines aktuators | |
| DE60238399D1 (de) | Verfahren zur herstellung von silicium | |
| DE50113179D1 (de) | Verfahren zur Herstellung eines Halbleiterbauelements | |
| DE60044470D1 (de) | Verfahren zur herstellung eines halbleiterelement | |
| DE60205676D1 (de) | Verfahren zur Herstellung eines Gegenstandes | |
| DE60225135D1 (de) | Verfahren zur herstellung eines halbleiterswafers | |
| DE60212643D1 (de) | Verfahren zur herstellung eines reifenkomponentenglieds | |
| DE50212806D1 (de) | Verfahren zur herstellung eines brillenglases | |
| DE60223328D1 (de) | Verfahren zur Herstellung einer Halbleiteranordnung | |
| DE60230982D1 (de) | Verfahren zur herstellung eines halbleiterbauelements | |
| DE60236171D1 (de) | Verfahren for zur herstellung eines 14-hydroxynormorphinon-derivats | |
| DE60209835D1 (de) | Verfahren zur Herstellung eines Halbleiterbauelements | |
| DE50208706D1 (de) | Verfahren zur herstellung eines quarzglastiegels | |
| DE50208521D1 (de) | Verfahren zur Ausbildung eines Silizium-Halbleiterkörpers | |
| DE50212805D1 (de) | Verfahren zur Herstellung eines Querträgers | |
| DE60140362D1 (de) | Verfahren zur herstellung eines halbleiterbauelements | |
| DE60217701D1 (de) | Verfahren zur herstellung eines siliciumdioxidfilms |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8320 | Willingness to grant licences declared (paragraph 23) | ||
| 8327 | Change in the person/name/address of the patent owner |
Owner name: ATMEL AUTOMOTIVE GMBH, 74072 HEILBRONN, DE |
|
| 8327 | Change in the person/name/address of the patent owner |
Owner name: DUDEK, VOLKER, DR.-ING., 76275 ETTLINGEN, DE |
|
| 8327 | Change in the person/name/address of the patent owner |
Owner name: TELEFUNKEN SEMICONDUCTORS GMBH & CO. KG, 74072, DE |
|
| R082 | Change of representative |
Ref document number: 1258919 Country of ref document: EP |