DE583361T1 - Programmierbare verbindungsstruktur für logische blöcke. - Google Patents

Programmierbare verbindungsstruktur für logische blöcke.

Info

Publication number
DE583361T1
DE583361T1 DE0583361T DE92911404T DE583361T1 DE 583361 T1 DE583361 T1 DE 583361T1 DE 0583361 T DE0583361 T DE 0583361T DE 92911404 T DE92911404 T DE 92911404T DE 583361 T1 DE583361 T1 DE 583361T1
Authority
DE
Germany
Prior art keywords
connecting structure
logical blocks
programmable connecting
programmable
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE0583361T
Other languages
English (en)
Inventor
Kapil Shankar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lattice Semiconductor Corp
Original Assignee
Lattice Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lattice Semiconductor Corp filed Critical Lattice Semiconductor Corp
Publication of DE583361T1 publication Critical patent/DE583361T1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
DE0583361T 1991-05-06 1992-05-06 Programmierbare verbindungsstruktur für logische blöcke. Pending DE583361T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/696,462 US5204556A (en) 1991-05-06 1991-05-06 Programmable interconnect structure for logic blocks
PCT/US1992/003575 WO1992020159A1 (en) 1991-05-06 1992-05-06 Programmable interconnect structure for logic blocks

Publications (1)

Publication Number Publication Date
DE583361T1 true DE583361T1 (de) 1995-03-16

Family

ID=24797175

Family Applications (1)

Application Number Title Priority Date Filing Date
DE0583361T Pending DE583361T1 (de) 1991-05-06 1992-05-06 Programmierbare verbindungsstruktur für logische blöcke.

Country Status (5)

Country Link
US (1) US5204556A (de)
EP (1) EP0583361A4 (de)
JP (1) JPH06510403A (de)
DE (1) DE583361T1 (de)
WO (1) WO1992020159A1 (de)

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US5367208A (en) 1986-09-19 1994-11-22 Actel Corporation Reconfigurable programmable interconnect architecture
US5489857A (en) * 1992-08-03 1996-02-06 Advanced Micro Devices, Inc. Flexible synchronous/asynchronous cell structure for a high density programmable logic device
US5457409A (en) * 1992-08-03 1995-10-10 Advanced Micro Devices, Inc. Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices
US5198705A (en) * 1990-05-11 1993-03-30 Actel Corporation Logic module with configurable combinational and sequential blocks
US6759870B2 (en) 1991-09-03 2004-07-06 Altera Corporation Programmable logic array integrated circuits
US20020130681A1 (en) * 1991-09-03 2002-09-19 Cliff Richard G. Programmable logic array integrated circuits
US5260610A (en) * 1991-09-03 1993-11-09 Altera Corporation Programmable logic element interconnections for programmable logic array integrated circuits
JP2965802B2 (ja) * 1991-12-19 1999-10-18 株式会社東芝 半導体集積回路
DE69304471T2 (de) * 1992-08-03 1997-03-20 Advanced Micro Devices Inc Programmierbare logische Vorrichtung
JP3313848B2 (ja) * 1992-11-10 2002-08-12 インフィニット テクノロジー コーポレーション ロジックネットワーク
US5396126A (en) * 1993-02-19 1995-03-07 At&T Corp. FPGA with distributed switch matrix
US5483178A (en) * 1993-03-29 1996-01-09 Altera Corporation Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers
US6051991A (en) * 1993-08-03 2000-04-18 Btr, Inc. Architecture and interconnect scheme for programmable logic circuits
US5457410A (en) * 1993-08-03 1995-10-10 Btr, Inc. Architecture and interconnect scheme for programmable logic circuits
US6462578B2 (en) 1993-08-03 2002-10-08 Btr, Inc. Architecture and interconnect scheme for programmable logic circuits
US5742179A (en) * 1994-01-27 1998-04-21 Dyna Logic Corporation High speed programmable logic architecture
US5581200A (en) * 1994-03-04 1996-12-03 Gudger; Keith H. Stored and combinational logic function generator without dedicated storage elements
US5436576A (en) * 1994-05-20 1995-07-25 Intel Corporation Switch matrices using reduced number of switching devices for signal routing
US5572198A (en) * 1994-07-25 1996-11-05 Intel Corporation Method and apparatus for routing in reduced switch matrices to provide one hundred percent coverage
US5689686A (en) * 1994-07-29 1997-11-18 Cypress Semiconductor Corp. Methods for maximizing routability in a programmable interconnect matrix having less than full connectability
US5581199A (en) * 1995-01-04 1996-12-03 Xilinx, Inc. Interconnect architecture for field programmable gate array using variable length conductors
JP3727065B2 (ja) 1995-05-03 2005-12-14 ビィティアール・インコーポレーテッド スケーリング可能な多重レベル相互接続アーキテクチャ
US5850564A (en) * 1995-05-03 1998-12-15 Btr, Inc, Scalable multiple level tab oriented interconnect architecture
US5818254A (en) * 1995-06-02 1998-10-06 Advanced Micro Devices, Inc. Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices
US5521529A (en) * 1995-06-02 1996-05-28 Advanced Micro Devices, Inc. Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation
US6028446A (en) * 1995-06-06 2000-02-22 Advanced Micro Devices, Inc. Flexible synchronous and asynchronous circuits for a very high density programmable logic device
US5744995A (en) * 1996-04-17 1998-04-28 Xilinx, Inc. Six-input multiplexer wtih two gate levels and three memory cells
US5625631A (en) * 1996-04-26 1997-04-29 International Business Machines Corporation Pass through mode for multi-chip-module die
US5894565A (en) * 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
US6624658B2 (en) 1999-02-04 2003-09-23 Advantage Logic, Inc. Method and apparatus for universal program controlled bus architecture
US6034547A (en) * 1996-09-04 2000-03-07 Advantage Logic, Inc. Method and apparatus for universal program controlled bus
JP3614264B2 (ja) * 1997-01-09 2005-01-26 富士通株式会社 プログラム可能な接続部を有する集積回路装置
EP0858167A1 (de) 1997-01-29 1998-08-12 Hewlett-Packard Company Feldprogrammierbarer Prozessor
EP0858168A1 (de) 1997-01-29 1998-08-12 Hewlett-Packard Company Feldprogrammierbarer Gatterprozessor
DE69827589T2 (de) 1997-12-17 2005-11-03 Elixent Ltd. Konfigurierbare Verarbeitungsanordnung und Verfahren zur Benutzung dieser Anordnung, um eine Zentraleinheit aufzubauen
JP2003526129A (ja) 1997-12-17 2003-09-02 エリクセントリミティド プログラマブル・アレイにおける乗算器の実現
DE69841256D1 (de) 1997-12-17 2009-12-10 Panasonic Corp Befehlsmaskierung um Befehlsströme einem Prozessor zuzuleiten
US6243664B1 (en) 1998-10-27 2001-06-05 Cypress Semiconductor Corporation Methods for maximizing routability in a programmable interconnect matrix having less than full connectability
US6320412B1 (en) 1999-12-20 2001-11-20 Btr, Inc. C/O Corporate Trust Co. Architecture and interconnect for programmable logic circuits
US6636930B1 (en) * 2000-03-06 2003-10-21 Actel Corporation Turn architecture for routing resources in a field programmable gate array
US6288937B1 (en) 2000-05-10 2001-09-11 Lattice Semiconductor Corporation Decoded generic routing pool
US6720796B1 (en) 2001-05-06 2004-04-13 Altera Corporation Multiple size memories in a programmable logic device
US7255437B2 (en) * 2003-10-09 2007-08-14 Howell Thomas A Eyeglasses with activity monitoring
US6975139B2 (en) 2004-03-30 2005-12-13 Advantage Logic, Inc. Scalable non-blocking switching network for programmable logic
US20050278464A1 (en) * 2004-05-13 2005-12-15 Claseman George R Multiple state configuration method
US7460529B2 (en) * 2004-07-29 2008-12-02 Advantage Logic, Inc. Interconnection fabric using switching networks in hierarchy
US7423453B1 (en) 2006-01-20 2008-09-09 Advantage Logic, Inc. Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric
US7999570B2 (en) * 2009-06-24 2011-08-16 Advantage Logic, Inc. Enhanced permutable switching network with multicasting signals for interconnection fabric
US10447276B2 (en) 2015-10-27 2019-10-15 Andapt, Inc. Power management integrated circuit integrating field effect transistors and programmable fabric

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58142629A (ja) * 1982-02-17 1983-08-24 Toshiba Corp 対角型マトリクス回路網
JP2540794B2 (ja) * 1985-03-04 1996-10-09 株式会社日立製作所 プログラマブルロジツクアレイ回路
US5015884A (en) * 1985-03-29 1991-05-14 Advanced Micro Devices, Inc. Multiple array high performance programmable logic device family
US4758746A (en) * 1985-08-12 1988-07-19 Monolithic Memories, Inc. Programmable logic array with added array of gates and added output routing flexibility
US4965472A (en) * 1988-08-11 1990-10-23 Cypress Semiconductor Corp. Programmable high speed state machine with sequencing capabilities
IT1225638B (it) * 1988-12-28 1990-11-22 Sgs Thomson Microelectronics Dispositivo logico integrato come una rete di maglie di memorie distribuite

Also Published As

Publication number Publication date
JPH06510403A (ja) 1994-11-17
US5204556A (en) 1993-04-20
WO1992020159A1 (en) 1992-11-12
EP0583361A4 (en) 1994-07-06
EP0583361A1 (de) 1994-02-23

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