DE59926T1 - Verfahren zum herstellen einer in kunststoff verkapselten halbleiteranordnung und ein leitergitter dafuer. - Google Patents

Verfahren zum herstellen einer in kunststoff verkapselten halbleiteranordnung und ein leitergitter dafuer.

Info

Publication number
DE59926T1
DE59926T1 DE198282101605T DE82101605T DE59926T1 DE 59926 T1 DE59926 T1 DE 59926T1 DE 198282101605 T DE198282101605 T DE 198282101605T DE 82101605 T DE82101605 T DE 82101605T DE 59926 T1 DE59926 T1 DE 59926T1
Authority
DE
Germany
Prior art keywords
substrate carrier
strips
plastic
munich
protrude
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE198282101605T
Other languages
English (en)
Inventor
Hiroyuki Osaka Fujii
Mikio Shimogyo-Ku Kyoto-Shi Kyoto Nishikawa
Kenichi Shiga Tateno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Publication of DE59926T1 publication Critical patent/DE59926T1/de
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Claims (8)

BERG STAPF SCHWABE · SANDMAIR MAUERKIRCHERSTRASSE 45 8000 MÜNCHEN 80 Anwaltsakte: 50 239 MATSUSHITA ELECTRONICS CORPORATION Osaka / Japan Patentansprüche
1. Verfahren zum Herstellen einer in Kunststoff vergossenen Halbleitereinrichtung, dadurch gekennze ichnet, daß zumindest äußere Anschlußleitungen (6,10, 11) und Streifen (15,16) einer Halbleiteranordnung festgeklemmt werden, die mit Hilfe eines Anschlußrahmens gebildet ist, welcher ein erstes Verbindungsband (9), das mit den äußeren Anschlußieitungen (9,10,11) verbunden ist, die von einer Seite eines Substratträgers (2) vorstehen, der auch als Wärmesenke verwendet wird, und ein zweites Verbindungsband (17) aufweist, das mit den Streifen (15,16) verbunden ist, die von der anderen Seite des Substratträgers (2) vorstehen, daß zumindest die äußeren Anschlußleitungen (6,10,11) und die streifen (15,16) durch obere und untere Spritzformen (13,14) festgeklemmt werden, so daß der Substratträger (2) in einem durch die oberen und unteren Formen (13,14) gebildeten Hohlraum schwimmen kann, daß Kunststoff (30) in den Hohlraum injiziert wird, während Teile der Streifen (15,16) in dem Hohlraum angeordnet sind, daß Teile der Streifen (15,16) abgetrennt werden, welche auf der Außenseite eines Kunststoff gehäuses vorstehen, und daß ein Verbindungsteil zwischen den äußeren Anschlußleitungen (6,10,11) und dem ersten Ver-
«(089)9882 72^'— ' Telex: 524560 BERG d Bankkonten: Bayer. Vereinsbank München 453100 (BLZ 70(720270)
Telegramme (cable): Telekopierer: (089) 983049 Hypo-Bank München 4410122850(BLZ 70020011) Swift Code: HYPO DE MM
BERGSTAPFPATENT München KaIIe Infotec 6350 Gr. II + III Postscheck München 653 43-808 (BLZ 700100 80)
bindungsband (9) durchtrennt wird.
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Dicke des Kunststoffes (30) unter den Streifen (15,16) größer ist als die Dicke des Kunststoffs (30) unter dem Substratträger (2).
3. Verfahren nach Anspruch 1, dadurch g e k e η nzeichnetf daß der durch die oberen und unteren Formen (13, 1.4) gebildete Hohlraum aus einem ersten Teil (22) und einem zweiten Teil (21) besteht, wobei der Abstand zwischen einer Oberseite und einer Unterseite des ersten Teils größer ist als der Abstand zwischen der Ober- und Unterseite des zweiten Teils, um dadurch einen Halbleiterelement-Halteteil der Halbleiteranordnung mit Hilfe des ersten Teils (22) in einer vorgegebenen Lage anzuordnen.
4. Verfahren nach Anspruch 3, dadurch g e k e η η-zeichnet, daß ein Formansatz (20) zum Ausbilden eines Durchgangsloches (4), um die Halbleitereinrichtung an dem Substraträger (2) mit Hilfe einer Schraube zu haltern, in dem zweiten Teil (21) ausgebildet ist.
5. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Dicke des Kunststoffes uni dem Substratträger (2) 0,3 bis 0,5mm ist.
6. Anschlußrahmen, gekennzeichnet durch ein erstes Verbindungsband (9), durch eine Anzahl äußerer Anschlußleitungen (6,10,11), die in einer Richtung von dem ersten Verbindungsband (9) vorstehen, durch einen Substratträger (2), welcher auch als Wärmesenke dient, und welcher mit einem oberen Teil eines (6) der äußeren Anschlußleitungen verbunden ist, durch Streifen (15,16), deren Enden mit einer Seite des Substratträgers (2) verbunden sind, welche der anderen Seite gegenüberliegt, mit welcher die äußeren Anschlußleitungen ( 6,10,11)
verbunden sind, und durch ein zweites Verbindungsband (17), das parallel zu dem ersten Verbindungsband (9) verläuft, wobei der Substratträger (2) dazwischen angeordnet ist und wobei die Streifen (15,16) eine geringere Dicke als der Substratträger (2) haben, so daß dazwischen eine Stufe ausgebildet ist, und die Unterseiten der Streifen (15,16) höher liegen als die Unterseite des Substraträgers (2)
7. Anschlußrahmen nach Anspruch 6, dadurch g e k e η n-10
zeichnet, daß die Anzahl Streifen (15,16), deren Enden mit dem Substratträger (2) verbunden sind, zwei ist.
8. Anschlußrahmen nach Anspruch 6, dadurch g e k e η η-15
zeichnet, daß eine Anzahl öffnungen (8,18) in jeder der beiden Verbindungsbänder (9,17) in gleichem Abstand voneinander ausgebildet sind.
DE198282101605T 1981-03-05 1982-03-02 Verfahren zum herstellen einer in kunststoff verkapselten halbleiteranordnung und ein leitergitter dafuer. Pending DE59926T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3222981A JPS57147260A (en) 1981-03-05 1981-03-05 Manufacture of resin-sealed semiconductor device and lead frame used therefor

Publications (1)

Publication Number Publication Date
DE59926T1 true DE59926T1 (de) 1983-02-03

Family

ID=12353135

Family Applications (2)

Application Number Title Priority Date Filing Date
DE8282101605T Expired DE3273693D1 (en) 1981-03-05 1982-03-02 A method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor
DE198282101605T Pending DE59926T1 (de) 1981-03-05 1982-03-02 Verfahren zum herstellen einer in kunststoff verkapselten halbleiteranordnung und ein leitergitter dafuer.

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE8282101605T Expired DE3273693D1 (en) 1981-03-05 1982-03-02 A method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor

Country Status (5)

Country Link
US (2) US4507675A (de)
EP (1) EP0059926B1 (de)
JP (1) JPS57147260A (de)
CA (1) CA1174821A (de)
DE (2) DE3273693D1 (de)

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JPS57147260A (en) 1982-09-11
EP0059926A1 (de) 1982-09-15
US4507675A (en) 1985-03-26
DE3273693D1 (en) 1986-11-13
CA1174821A (en) 1984-09-25
JPS6220705B2 (de) 1987-05-08
EP0059926B1 (de) 1986-10-08
US4637130A (en) 1987-01-20

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