DE60006842D1 - Mehrprozessoren knotensteuerschaltkreis sowie verfahren - Google Patents

Mehrprozessoren knotensteuerschaltkreis sowie verfahren

Info

Publication number
DE60006842D1
DE60006842D1 DE60006842T DE60006842T DE60006842D1 DE 60006842 D1 DE60006842 D1 DE 60006842D1 DE 60006842 T DE60006842 T DE 60006842T DE 60006842 T DE60006842 T DE 60006842T DE 60006842 D1 DE60006842 D1 DE 60006842D1
Authority
DE
Germany
Prior art keywords
control circuit
node control
processors
processors node
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60006842T
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English (en)
Other versions
DE60006842T2 (de
Inventor
M Deneroff
G Kaldani
Yuval Koren
Edward Mccracken
Swaminathan Venkataraman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Graphics Properties Holdings Inc
Original Assignee
Silicon Graphics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Graphics Inc filed Critical Silicon Graphics Inc
Publication of DE60006842D1 publication Critical patent/DE60006842D1/de
Application granted granted Critical
Publication of DE60006842T2 publication Critical patent/DE60006842T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
DE60006842T 1999-09-29 2000-09-29 Multiprozessor-Node-Controller-Schaltung und Verfahren Expired - Fee Related DE60006842T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US407428 1982-08-12
US09/407,428 US6751698B1 (en) 1999-09-29 1999-09-29 Multiprocessor node controller circuit and method
PCT/US2000/027003 WO2001024031A2 (en) 1999-09-29 2000-09-29 Multiprocessor node controller circuit and method

Publications (2)

Publication Number Publication Date
DE60006842D1 true DE60006842D1 (de) 2004-01-08
DE60006842T2 DE60006842T2 (de) 2004-09-02

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE60006842T Expired - Fee Related DE60006842T2 (de) 1999-09-29 2000-09-29 Multiprozessor-Node-Controller-Schaltung und Verfahren

Country Status (5)

Country Link
US (3) US6751698B1 (de)
EP (1) EP1222559B1 (de)
JP (1) JP4472909B2 (de)
DE (1) DE60006842T2 (de)
WO (1) WO2001024031A2 (de)

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US20090024833A1 (en) 2009-01-22
US20050053057A1 (en) 2005-03-10
US7881321B2 (en) 2011-02-01
JP4472909B2 (ja) 2010-06-02
WO2001024031A2 (en) 2001-04-05
WO2001024031A3 (en) 2001-08-23
US7406086B2 (en) 2008-07-29
DE60006842T2 (de) 2004-09-02
JP2003510721A (ja) 2003-03-18
EP1222559A2 (de) 2002-07-17
US6751698B1 (en) 2004-06-15

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