DE60033740D1 - Rechnerperipheriegerät und rechnerlesbares Medium mit einem Program zum Steuern des Rechnerperipheriegerätes - Google Patents

Rechnerperipheriegerät und rechnerlesbares Medium mit einem Program zum Steuern des Rechnerperipheriegerätes

Info

Publication number
DE60033740D1
DE60033740D1 DE60033740T DE60033740T DE60033740D1 DE 60033740 D1 DE60033740 D1 DE 60033740D1 DE 60033740 T DE60033740 T DE 60033740T DE 60033740 T DE60033740 T DE 60033740T DE 60033740 D1 DE60033740 D1 DE 60033740D1
Authority
DE
Germany
Prior art keywords
peripheral device
computer
cpu
computer peripheral
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60033740T
Other languages
English (en)
Other versions
DE60033740T2 (de
Inventor
Motoki Yoshizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of DE60033740D1 publication Critical patent/DE60033740D1/de
Application granted granted Critical
Publication of DE60033740T2 publication Critical patent/DE60033740T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40123—Interconnection of computers and peripherals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
DE60033740T 1999-07-06 2000-07-06 Rechnerperipheriegerät und rechnerlesbares Medium mit einem Program zum Steuern des Rechnerperipheriegerätes Expired - Lifetime DE60033740T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP19163599 1999-07-06
JP11191635A JP2001022680A (ja) 1999-07-06 1999-07-06 コンピュータ周辺機器

Publications (2)

Publication Number Publication Date
DE60033740D1 true DE60033740D1 (de) 2007-04-19
DE60033740T2 DE60033740T2 (de) 2007-12-06

Family

ID=16277945

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60033740T Expired - Lifetime DE60033740T2 (de) 1999-07-06 2000-07-06 Rechnerperipheriegerät und rechnerlesbares Medium mit einem Program zum Steuern des Rechnerperipheriegerätes

Country Status (5)

Country Link
US (1) US6789138B1 (de)
EP (1) EP1067462B1 (de)
JP (1) JP2001022680A (de)
AT (1) ATE356383T1 (de)
DE (1) DE60033740T2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6728801B2 (en) * 2001-06-29 2004-04-27 Intel Corporation Method and apparatus for period promotion avoidance for hubs
US8060662B2 (en) * 2007-12-17 2011-11-15 Ricoh Company, Ltd. Recording control apparatus, recording control method, and computer program product

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4476522A (en) * 1981-03-09 1984-10-09 International Business Machines Corporation Programmable peripheral processing controller with mode-selectable address register sequencing
JPS5952333A (ja) * 1982-09-17 1984-03-26 Hitachi Ltd システム拡張方式
DE3586557D1 (de) * 1984-10-26 1992-10-01 Ibm Datenverarbeitungsvorrichtung mit festem adressraum und variablem speicher.
JPS6431217A (en) 1987-07-27 1989-02-01 Sharp Kk Method for selecting interface for computer equipment
FR2645989A1 (fr) 1989-04-17 1990-10-19 Bull Sa Coupleur multifonctions entre une unite centrale d'ordinateur et les differents organes peripheriques de ce dernier
JP3128817B2 (ja) 1990-11-09 2001-01-29 オムロン株式会社 メモリの種別判定方法
US5842041A (en) * 1994-05-20 1998-11-24 Advanced Micro Devices, Inc. Computer system employing a control signal indicative of whether address is within address space of devices on processor local bus
JP3919238B2 (ja) 1994-05-31 2007-05-23 キヤノン株式会社 印刷システムおよび印刷システムの印刷制御方法および印刷制御装置
KR100365169B1 (ko) * 1995-05-26 2003-05-16 내셔널 세미콘덕터 코포레이션 감소된핀계수를가진집적된제1버스및제2버스콘트롤러
US5835760A (en) * 1995-10-13 1998-11-10 Texas Instruments Incorporated Method and arrangement for providing BIOS to a host computer
US5872998A (en) * 1995-11-21 1999-02-16 Seiko Epson Corporation System using a primary bridge to recapture shared portion of a peripheral memory of a peripheral device to provide plug and play capability
JP3403284B2 (ja) * 1995-12-14 2003-05-06 インターナショナル・ビジネス・マシーンズ・コーポレーション 情報処理システム及びその制御方法
JPH10171957A (ja) * 1996-12-04 1998-06-26 Murata Mfg Co Ltd Ｐｃカードのｃｉｓ切り替え機構
US5944806A (en) * 1997-09-26 1999-08-31 Hewlett-Packard Company Microprocessor with versatile addressing
US5928347A (en) * 1997-11-18 1999-07-27 Shuttle Technology Group Ltd. Universal memory card interface apparatus
JPH11259605A (ja) * 1998-01-08 1999-09-24 Tdk Corp Ｐｃカード
US6480948B1 (en) * 1999-06-24 2002-11-12 Cirrus Logic, Inc. Configurable system memory map
US6446139B1 (en) * 1999-06-28 2002-09-03 Adaptec, Inc. Multiple chip single image BIOS

Also Published As

Publication number Publication date
US6789138B1 (en) 2004-09-07
EP1067462A1 (de) 2001-01-10
EP1067462B1 (de) 2007-03-07
JP2001022680A (ja) 2001-01-26
DE60033740T2 (de) 2007-12-06
ATE356383T1 (de) 2007-03-15

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