DE60045286D1 - Registerumbenennungssystem - Google Patents

Registerumbenennungssystem

Info

Publication number
DE60045286D1
DE60045286D1 DE60045286T DE60045286T DE60045286D1 DE 60045286 D1 DE60045286 D1 DE 60045286D1 DE 60045286 T DE60045286 T DE 60045286T DE 60045286 T DE60045286 T DE 60045286T DE 60045286 D1 DE60045286 D1 DE 60045286D1
Authority
DE
Germany
Prior art keywords
register
hold
physical
register rename
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60045286T
Other languages
English (en)
Inventor
Hajime Seki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Application granted granted Critical
Publication of DE60045286D1 publication Critical patent/DE60045286D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
DE60045286T 1999-09-08 2000-09-06 Registerumbenennungssystem Expired - Lifetime DE60045286D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP25414999 1999-09-08
PCT/JP2000/006070 WO2001018645A1 (fr) 1999-09-08 2000-09-06 Systeme de renommage de registre

Publications (1)

Publication Number Publication Date
DE60045286D1 true DE60045286D1 (de) 2011-01-05

Family

ID=17260916

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60045286T Expired - Lifetime DE60045286D1 (de) 1999-09-08 2000-09-06 Registerumbenennungssystem

Country Status (7)

Country Link
US (1) US7171541B1 (de)
EP (1) EP1237072B1 (de)
JP (1) JP3592673B2 (de)
CN (1) CN1264087C (de)
AT (1) ATE489674T1 (de)
DE (1) DE60045286D1 (de)
WO (1) WO2001018645A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7200738B2 (en) * 2002-04-18 2007-04-03 Micron Technology, Inc. Reducing data hazards in pipelined processors to provide high processor utilization
AU2002368121A1 (en) * 2002-07-30 2004-02-16 The Circle For The Promotion Of Science And Engineering Command control device, function unit, program converter, and language processor
CN100524208C (zh) * 2006-10-26 2009-08-05 中国科学院计算技术研究所 对状态寄存器进行重命名的方法和使用该方法的处理器
KR100861701B1 (ko) 2007-01-10 2008-10-06 연세대학교 산학협력단 레지스터 값의 유사성에 기반을 둔 레지스터 리네이밍시스템 및 방법
CN101794214B (zh) * 2009-02-04 2013-11-20 世意法（北京）半导体研发有限责任公司 使用多块物理寄存器映射表的寄存器重命名系统及其方法
GB2496934B (en) * 2012-08-07 2014-06-11 Imagination Tech Ltd Multi-stage register renaming using dependency removal
US9471325B2 (en) * 2013-07-12 2016-10-18 Qualcomm Incorporated Method and apparatus for selective renaming in a microprocessor
WO2015061697A1 (en) * 2013-10-27 2015-04-30 Advanced Micro Devices, Inc. Processor and methods for floating point register aliasing
CN111506347B (zh) * 2020-03-27 2023-05-26 上海赛昉科技有限公司 一种基于指令写后读相关假设的重命名的方法
US11294683B2 (en) 2020-03-30 2022-04-05 SiFive, Inc. Duplicate detection for register renaming
CN114356420B (zh) * 2021-12-28 2023-02-17 海光信息技术股份有限公司 指令流水线的处理方法及装置、电子装置及存储介质
US11714620B1 (en) 2022-01-14 2023-08-01 Triad National Security, Llc Decoupling loop dependencies using buffers to enable pipelining of loops

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4992938A (en) * 1987-07-01 1991-02-12 International Business Machines Corporation Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers
US5197132A (en) * 1990-06-29 1993-03-23 Digital Equipment Corporation Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery
JPH06149569A (ja) * 1992-11-10 1994-05-27 Oki Electric Ind Co Ltd レジスタ番号変更装置
US5694564A (en) * 1993-01-04 1997-12-02 Motorola, Inc. Data processing system a method for performing register renaming having back-up capability
US5655115A (en) * 1995-02-14 1997-08-05 Hal Computer Systems, Inc. Processor structure and method for watchpoint of plural simultaneous unresolved branch evaluation
US6112019A (en) * 1995-06-12 2000-08-29 Georgia Tech Research Corp. Distributed instruction queue
US5919256A (en) * 1996-03-26 1999-07-06 Advanced Micro Devices, Inc. Operand cache addressed by the instruction address for reducing latency of read instruction
US5893145A (en) * 1996-12-02 1999-04-06 Compaq Computer Corp. System and method for routing operands within partitions of a source register to partitions within a destination register
JP2953451B2 (ja) * 1997-12-25 1999-09-27 日本電気株式会社 割り込み処理方法
US6185671B1 (en) * 1998-03-31 2001-02-06 Intel Corporation Checking data type of operands specified by an instruction using attributes in a tagged array architecture
JP2000172505A (ja) * 1998-12-11 2000-06-23 Hitachi Ltd レジスタ番号変換を行うプロセッサ
US6442677B1 (en) * 1999-06-10 2002-08-27 Advanced Micro Devices, Inc. Apparatus and method for superforwarding load operands in a microprocessor

Also Published As

Publication number Publication date
EP1237072B1 (de) 2010-11-24
CN1264087C (zh) 2006-07-12
CN1373869A (zh) 2002-10-09
EP1237072A1 (de) 2002-09-04
WO2001018645A1 (fr) 2001-03-15
ATE489674T1 (de) 2010-12-15
EP1237072A4 (de) 2003-01-08
JP3592673B2 (ja) 2004-11-24
US7171541B1 (en) 2007-01-30

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