DE60045416D1 - Verfahren zur behandlung von mikroelektroniksubstraten - Google Patents
Verfahren zur behandlung von mikroelektroniksubstratenInfo
- Publication number
- DE60045416D1 DE60045416D1 DE60045416T DE60045416T DE60045416D1 DE 60045416 D1 DE60045416 D1 DE 60045416D1 DE 60045416 T DE60045416 T DE 60045416T DE 60045416 T DE60045416 T DE 60045416T DE 60045416 D1 DE60045416 D1 DE 60045416D1
- Authority
- DE
- Germany
- Prior art keywords
- microelectronic substrates
- treating microelectronic
- treating
- substrates
- microelectronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/974—Substrate surface preparation
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9910667A FR2797713B1 (fr) | 1999-08-20 | 1999-08-20 | Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede |
PCT/FR2000/002330 WO2001015215A1 (fr) | 1999-08-20 | 2000-08-17 | Procede de traitement de substrats pour la micro-electronique et substrats obtenus par ce procede |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60045416D1 true DE60045416D1 (de) | 2011-02-03 |
Family
ID=9549260
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60045416T Expired - Lifetime DE60045416D1 (de) | 1999-08-20 | 2000-08-17 | Verfahren zur behandlung von mikroelektroniksubstraten |
Country Status (9)
Country | Link |
---|---|
US (2) | US7029993B1 (de) |
EP (1) | EP1208589B1 (de) |
JP (2) | JP2003509838A (de) |
KR (1) | KR100764978B1 (de) |
DE (1) | DE60045416D1 (de) |
FR (1) | FR2797713B1 (de) |
MY (1) | MY133102A (de) |
TW (1) | TW515000B (de) |
WO (1) | WO2001015215A1 (de) |
Families Citing this family (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8507361B2 (en) | 2000-11-27 | 2013-08-13 | Soitec | Fabrication of substrates with a useful layer of monocrystalline semiconductor material |
FR2894990B1 (fr) * | 2005-12-21 | 2008-02-22 | Soitec Silicon On Insulator | Procede de fabrication de substrats, notamment pour l'optique,l'electronique ou l'optoelectronique et substrat obtenu selon ledit procede |
FR2840731B3 (fr) * | 2002-06-11 | 2004-07-30 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees |
FR2827078B1 (fr) | 2001-07-04 | 2005-02-04 | Soitec Silicon On Insulator | Procede de diminution de rugosite de surface |
US7749910B2 (en) | 2001-07-04 | 2010-07-06 | S.O.I.Tec Silicon On Insulator Technologies | Method of reducing the surface roughness of a semiconductor wafer |
US7883628B2 (en) | 2001-07-04 | 2011-02-08 | S.O.I.Tec Silicon On Insulator Technologies | Method of reducing the surface roughness of a semiconductor wafer |
FR2827423B1 (fr) * | 2001-07-16 | 2005-05-20 | Soitec Silicon On Insulator | Procede d'amelioration d'etat de surface |
US7189606B2 (en) * | 2002-06-05 | 2007-03-13 | Micron Technology, Inc. | Method of forming fully-depleted (FD) SOI MOSFET access transistor |
US6953736B2 (en) | 2002-07-09 | 2005-10-11 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Process for transferring a layer of strained semiconductor material |
WO2004015759A2 (en) | 2002-08-12 | 2004-02-19 | S.O.I.Tec Silicon On Insulator Technologies | A method of preparing a thin layer, the method including a step of correcting thickness by sacrificial oxidation, and an associated machine |
FR2845202B1 (fr) * | 2002-10-01 | 2004-11-05 | Soitec Silicon On Insulator | Procede de recuit rapide de tranches de materiau semiconducteur. |
KR100874788B1 (ko) * | 2003-01-07 | 2008-12-18 | 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 | 박층 박리 후에 박리 구조를 포함하는 웨이퍼의 기계적수단에 의한 재활용 방법 |
JP4407127B2 (ja) * | 2003-01-10 | 2010-02-03 | 信越半導体株式会社 | Soiウエーハの製造方法 |
DE60336543D1 (de) | 2003-05-27 | 2011-05-12 | Soitec Silicon On Insulator | Verfahren zur Herstellung einer heteroepitaktischen Mikrostruktur |
FR2858462B1 (fr) * | 2003-07-29 | 2005-12-09 | Soitec Silicon On Insulator | Procede d'obtention d'une couche mince de qualite accrue par co-implantation et recuit thermique |
EP1652230A2 (de) * | 2003-07-29 | 2006-05-03 | S.O.I.Tec Silicon on Insulator Technologies | Verfahren zum erhalten einer qualitativ hochwertigen dünnschicht durch coimplantation und thermisches ausheizen |
US7563697B2 (en) | 2003-09-05 | 2009-07-21 | Sumco Corporation | Method for producing SOI wafer |
FR2867607B1 (fr) | 2004-03-10 | 2006-07-14 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat pour la microelectronique, l'opto-electronique et l'optique avec limitaton des lignes de glissement et substrat correspondant |
JP4826994B2 (ja) * | 2004-09-13 | 2011-11-30 | 信越半導体株式会社 | Soiウェーハの製造方法 |
WO2006030699A1 (ja) * | 2004-09-13 | 2006-03-23 | Shin-Etsu Handotai Co., Ltd. | Soiウェーハの製造方法及びsoiウェーハ |
JP4696510B2 (ja) * | 2004-09-15 | 2011-06-08 | 信越半導体株式会社 | Soiウェーハの製造方法 |
CN101036222A (zh) * | 2004-09-21 | 2007-09-12 | S.O.I.Tec绝缘体上硅技术公司 | 通过实施共注入获得薄层的方法和随后的注入 |
DE602004022882D1 (de) * | 2004-12-28 | 2009-10-08 | Soitec Silicon On Insulator | Ner geringen dichte von löchern |
FR2880988B1 (fr) | 2005-01-19 | 2007-03-30 | Soitec Silicon On Insulator | TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE |
FR2881573B1 (fr) * | 2005-01-31 | 2008-07-11 | Soitec Silicon On Insulator | Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunes |
JP2006279015A (ja) * | 2005-03-02 | 2006-10-12 | Seiko Epson Corp | 半導体装置の製造方法、集積回路、電気光学装置、及び電子機器 |
FR2884647B1 (fr) | 2005-04-15 | 2008-02-22 | Soitec Silicon On Insulator | Traitement de plaques de semi-conducteurs |
FR2895563B1 (fr) | 2005-12-22 | 2008-04-04 | Soitec Silicon On Insulator | Procede de simplification d'une sequence de finition et structure obtenue par le procede |
WO2008082920A1 (en) * | 2006-12-28 | 2008-07-10 | Memc Electronic Materials, Inc. | Methods for producing smooth wafers |
FR2912259B1 (fr) | 2007-02-01 | 2009-06-05 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat du type "silicium sur isolant". |
FR2912258B1 (fr) * | 2007-02-01 | 2009-05-08 | Soitec Silicon On Insulator | "procede de fabrication d'un substrat du type silicium sur isolant" |
JP5125194B2 (ja) * | 2007-04-10 | 2013-01-23 | 信越半導体株式会社 | 貼り合わせウエーハの製造方法 |
JP5135935B2 (ja) * | 2007-07-27 | 2013-02-06 | 信越半導体株式会社 | 貼り合わせウエーハの製造方法 |
JP5654206B2 (ja) * | 2008-03-26 | 2015-01-14 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法及び該soi基板を用いた半導体装置 |
JP2009260315A (ja) * | 2008-03-26 | 2009-11-05 | Semiconductor Energy Lab Co Ltd | Soi基板の作製方法及び半導体装置の作製方法 |
FR2929758B1 (fr) | 2008-04-07 | 2011-02-11 | Commissariat Energie Atomique | Procede de transfert a l'aide d'un substrat ferroelectrique |
EP2161741B1 (de) * | 2008-09-03 | 2014-06-11 | Soitec | Verfahren zur Herstellung eines Halbleiters auf einem Isoliersubstrat mit verringerter SECCO-Fehlerdichte |
FR2938119B1 (fr) * | 2008-10-30 | 2011-04-22 | Soitec Silicon On Insulator | Procede de detachement de couches semi-conductrices a basse temperature |
WO2010062852A1 (en) * | 2008-11-26 | 2010-06-03 | Memc Electronic Materials, Inc. | Method for processing a silicon-on-insulator structure |
FR2943458B1 (fr) | 2009-03-18 | 2011-06-10 | Soitec Silicon On Insulator | Procede de finition d'un substrat de type "silicium sur isolant" soi |
US20120038022A1 (en) * | 2009-03-25 | 2012-02-16 | Sharp Kabushiki Kaisha | Insulating substrate for semiconductor device, and semiconductor device |
FR2987166B1 (fr) | 2012-02-16 | 2017-05-12 | Soitec Silicon On Insulator | Procede de transfert d'une couche |
JP5096634B2 (ja) * | 2012-06-14 | 2012-12-12 | ソイテック | 低いホール密度を有する薄層を得るための方法 |
EP2685297B1 (de) * | 2012-07-13 | 2017-12-06 | Huawei Technologies Co., Ltd. | Verfahren zur Herstellung einer photonischen Schaltung mit aktiven und passiven Strukturen |
US9098666B2 (en) | 2012-11-28 | 2015-08-04 | Qualcomm Incorporated | Clock distribution network for 3D integrated circuit |
US9064077B2 (en) | 2012-11-28 | 2015-06-23 | Qualcomm Incorporated | 3D floorplanning using 2D and 3D blocks |
US9536840B2 (en) | 2013-02-12 | 2017-01-03 | Qualcomm Incorporated | Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods |
US9041448B2 (en) | 2013-03-05 | 2015-05-26 | Qualcomm Incorporated | Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods |
US9177890B2 (en) | 2013-03-07 | 2015-11-03 | Qualcomm Incorporated | Monolithic three dimensional integration of semiconductor integrated circuits |
US9171608B2 (en) | 2013-03-15 | 2015-10-27 | Qualcomm Incorporated | Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods |
DE102015106441B4 (de) * | 2015-04-27 | 2022-01-27 | Infineon Technologies Ag | Verfahren zum Planarisieren eines Halbleiterwafers |
KR102424963B1 (ko) | 2015-07-30 | 2022-07-25 | 삼성전자주식회사 | 집적회로 소자 및 그 제조 방법 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
JPH05102112A (ja) * | 1991-10-04 | 1993-04-23 | Kyushu Electron Metal Co Ltd | 半導体シリコンウエーハの製造方法 |
JP2994837B2 (ja) | 1992-01-31 | 1999-12-27 | キヤノン株式会社 | 半導体基板の平坦化方法、半導体基板の作製方法、及び半導体基板 |
DE69333619T2 (de) | 1992-01-30 | 2005-09-29 | Canon K.K. | Herstellungsverfahren für Halbleitersubstrate |
US5589422A (en) * | 1993-01-15 | 1996-12-31 | Intel Corporation | Controlled, gas phase process for removal of trace metal contamination and for removal of a semiconductor layer |
JPH09260620A (ja) * | 1996-03-25 | 1997-10-03 | Shin Etsu Handotai Co Ltd | 結合ウエーハの製造方法およびこの方法で製造される結合ウエーハ |
FR2748851B1 (fr) | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
JP3660469B2 (ja) * | 1996-07-05 | 2005-06-15 | 日本電信電話株式会社 | Soi基板の製造方法 |
JP3522482B2 (ja) | 1997-02-24 | 2004-04-26 | 三菱住友シリコン株式会社 | Soi基板の製造方法 |
JPH10275905A (ja) | 1997-03-31 | 1998-10-13 | Mitsubishi Electric Corp | シリコンウェーハの製造方法およびシリコンウェーハ |
JP3346249B2 (ja) * | 1997-10-30 | 2002-11-18 | 信越半導体株式会社 | シリコンウエーハの熱処理方法及びシリコンウエーハ |
JP3451908B2 (ja) * | 1997-11-05 | 2003-09-29 | 信越半導体株式会社 | Soiウエーハの熱処理方法およびsoiウエーハ |
JP2998724B2 (ja) * | 1997-11-10 | 2000-01-11 | 日本電気株式会社 | 張り合わせsoi基板の製造方法 |
JPH11195774A (ja) * | 1997-12-26 | 1999-07-21 | Canon Inc | 半導体基板の作成方法 |
FR2774510B1 (fr) | 1998-02-02 | 2001-10-26 | Soitec Silicon On Insulator | Procede de traitement de substrats, notamment semi-conducteurs |
FR2777115B1 (fr) * | 1998-04-07 | 2001-07-13 | Commissariat Energie Atomique | Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede |
AU3488699A (en) * | 1998-04-10 | 1999-11-01 | Silicon Genesis Corporation | Surface treatment process and system |
US6287941B1 (en) * | 1999-04-21 | 2001-09-11 | Silicon Genesis Corporation | Surface finishing of SOI substrates using an EPI process |
-
1999
- 1999-08-20 FR FR9910667A patent/FR2797713B1/fr not_active Expired - Lifetime
-
2000
- 2000-08-16 MY MYPI20003740 patent/MY133102A/en unknown
- 2000-08-17 DE DE60045416T patent/DE60045416D1/de not_active Expired - Lifetime
- 2000-08-17 EP EP00958696A patent/EP1208589B1/de not_active Expired - Lifetime
- 2000-08-17 KR KR1020027002224A patent/KR100764978B1/ko active IP Right Grant
- 2000-08-17 WO PCT/FR2000/002330 patent/WO2001015215A1/fr active Application Filing
- 2000-08-17 US US10/069,058 patent/US7029993B1/en not_active Expired - Lifetime
- 2000-08-17 JP JP2001519480A patent/JP2003509838A/ja active Pending
- 2000-10-05 TW TW089116691A patent/TW515000B/zh not_active IP Right Cessation
-
2006
- 2006-02-07 US US11/348,502 patent/US7288418B2/en not_active Expired - Lifetime
-
2011
- 2011-12-09 JP JP2011270460A patent/JP2012104839A/ja not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
EP1208589A1 (de) | 2002-05-29 |
EP1208589B1 (de) | 2010-12-22 |
US7029993B1 (en) | 2006-04-18 |
JP2012104839A (ja) | 2012-05-31 |
FR2797713A1 (fr) | 2001-02-23 |
KR100764978B1 (ko) | 2007-10-09 |
US20060189102A1 (en) | 2006-08-24 |
WO2001015215A1 (fr) | 2001-03-01 |
KR20020026375A (ko) | 2002-04-09 |
JP2003509838A (ja) | 2003-03-11 |
MY133102A (en) | 2007-10-31 |
FR2797713B1 (fr) | 2002-08-02 |
TW515000B (en) | 2002-12-21 |
US7288418B2 (en) | 2007-10-30 |
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Legal Events
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