DE60128960D1 - Architektur für ziegelförmig aufbaubares nutzerprogrammierbares gatterfeld - Google Patents

Architektur für ziegelförmig aufbaubares nutzerprogrammierbares gatterfeld

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Publication number
DE60128960D1
DE60128960D1 DE60128960T DE60128960T DE60128960D1 DE 60128960 D1 DE60128960 D1 DE 60128960D1 DE 60128960 T DE60128960 T DE 60128960T DE 60128960 T DE60128960 T DE 60128960T DE 60128960 D1 DE60128960 D1 DE 60128960D1
Authority
DE
Germany
Prior art keywords
tilting
architecture
built
programmable gate
gate frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60128960T
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English (en)
Other versions
DE60128960T2 (de
Inventor
Jung-Cheun Lien
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi SoC Corp
Original Assignee
Actel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Actel Corp filed Critical Actel Corp
Publication of DE60128960D1 publication Critical patent/DE60128960D1/de
Application granted granted Critical
Publication of DE60128960T2 publication Critical patent/DE60128960T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3947—Routing global
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17732—Macroblocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
DE60128960T 2000-09-02 2001-08-31 Architektur für ziegelförmig aufbaubares nutzerprogrammierbares gatterfeld Expired - Lifetime DE60128960T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US654240 2000-09-02
US09/654,240 US6476636B1 (en) 2000-09-02 2000-09-02 Tileable field-programmable gate array architecture
PCT/US2001/027172 WO2002021694A2 (en) 2000-09-02 2001-08-31 Tileable field-programmable gate array architecture

Publications (2)

Publication Number Publication Date
DE60128960D1 true DE60128960D1 (de) 2007-07-26
DE60128960T2 DE60128960T2 (de) 2008-02-14

Family

ID=24624042

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60128960T Expired - Lifetime DE60128960T2 (de) 2000-09-02 2001-08-31 Architektur für ziegelförmig aufbaubares nutzerprogrammierbares gatterfeld

Country Status (6)

Country Link
US (11) US6476636B1 (de)
EP (1) EP1354404B1 (de)
JP (1) JP2004524715A (de)
AU (1) AU2001286979A1 (de)
DE (1) DE60128960T2 (de)
WO (1) WO2002021694A2 (de)

Families Citing this family (378)

* Cited by examiner, † Cited by third party
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US6731133B1 (en) 2004-05-04
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US6888375B2 (en) 2005-05-03
EP1354404B1 (de) 2007-06-13
US6611153B1 (en) 2003-08-26
US6700404B1 (en) 2004-03-02
DE60128960T2 (de) 2008-02-14
AU2001286979A1 (en) 2002-03-22
US7137095B1 (en) 2006-11-14
EP1354404A2 (de) 2003-10-22
US6968487B1 (en) 2005-11-22
WO2002021694A2 (en) 2002-03-14
JP2004524715A (ja) 2004-08-12
US6476636B1 (en) 2002-11-05
US6531891B1 (en) 2003-03-11
US20070089082A1 (en) 2007-04-19
US20030218479A1 (en) 2003-11-27

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