DE602004003475D1 - Testen von integrierten schaltungen - Google Patents

Testen von integrierten schaltungen

Info

Publication number
DE602004003475D1
DE602004003475D1 DE602004003475T DE602004003475T DE602004003475D1 DE 602004003475 D1 DE602004003475 D1 DE 602004003475D1 DE 602004003475 T DE602004003475 T DE 602004003475T DE 602004003475 T DE602004003475 T DE 602004003475T DE 602004003475 D1 DE602004003475 D1 DE 602004003475D1
Authority
DE
Germany
Prior art keywords
cells
scan chain
ones
mode
boundary scan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004003475T
Other languages
English (en)
Other versions
DE602004003475T2 (de
Inventor
De Logt M Van
F Waayers
Der Heyden Frank Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of DE602004003475D1 publication Critical patent/DE602004003475D1/de
Application granted granted Critical
Publication of DE602004003475T2 publication Critical patent/DE602004003475T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
DE602004003475T 2003-02-10 2004-01-28 Testen von integrierten schaltungen Expired - Lifetime DE602004003475T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
EP03075382 2003-02-10
EP03075382 2003-02-10
EP03102367 2003-07-30
EP03102367 2003-07-30
PCT/IB2004/050057 WO2004070395A2 (en) 2003-02-10 2004-01-28 Testing of integrated circuits

Publications (2)

Publication Number Publication Date
DE602004003475D1 true DE602004003475D1 (de) 2007-01-11
DE602004003475T2 DE602004003475T2 (de) 2007-09-20

Family

ID=32852240

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004003475T Expired - Lifetime DE602004003475T2 (de) 2003-02-10 2004-01-28 Testen von integrierten schaltungen

Country Status (6)

Country Link
US (1) US7409612B2 (de)
EP (1) EP1595156B1 (de)
JP (1) JP4579230B2 (de)
AT (1) ATE347112T1 (de)
DE (1) DE602004003475T2 (de)
WO (1) WO2004070395A2 (de)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7308629B2 (en) 2004-12-07 2007-12-11 Texas Instruments Incorporated Addressable tap domain selection circuit with TDI/TDO external terminal
US7657810B2 (en) * 2006-02-03 2010-02-02 Texas Instruments Incorporated Scan testing using scan frames with embedded commands
US7941717B2 (en) 2005-10-24 2011-05-10 Nxp B.V. IC testing methods and apparatus
DE602006013339D1 (de) * 2005-10-24 2010-05-12 Nxp Bv Ic-testverfahren und vorrichtung
DE602006015082D1 (de) * 2005-10-24 2010-08-05 Nxp Bv Ic-testverfahren und vorrichtung
WO2007069097A1 (en) * 2005-11-02 2007-06-21 Nxp B.V. Ic testing methods and apparatus
US7818641B2 (en) 2006-10-18 2010-10-19 Texas Instruments Incorporated Interface to full and reduce pin JTAG devices
US7861128B1 (en) * 2006-12-14 2010-12-28 Xilinx, Inc. Scan element with self scan-mode toggle
US7554858B2 (en) * 2007-08-10 2009-06-30 Micron Technology, Inc. System and method for reducing pin-count of memory devices, and memory device testers for same
US7958479B2 (en) * 2007-12-04 2011-06-07 Alcatel-Lucent Usa Inc. Method and apparatus for describing and testing a system-on-chip
US7890824B2 (en) * 2008-07-24 2011-02-15 International Business Machines Corporation Asynchronous communication apparatus using JTAG test data registers
CN102043124B (zh) * 2009-10-12 2013-07-17 炬力集成电路设计有限公司 一种具有扫描链的集成电路
US8527822B2 (en) 2009-10-19 2013-09-03 Nxp B.V. System and method for single terminal boundary scan
US8205125B2 (en) * 2009-10-23 2012-06-19 Texas Instruments Incorporated Enhanced control in scan tests of integrated circuits with partitioned scan chains
NL1037457C2 (en) * 2009-11-10 2011-05-12 Jtag Technologies Bv A method of and an arrangement for testing connections on a printed circuit board.
US8566656B2 (en) * 2009-12-22 2013-10-22 Nxp B.V. Testing circuit and method
JP5703605B2 (ja) * 2010-06-28 2015-04-22 富士通セミコンダクター株式会社 半導体集積回路
CN101995546B (zh) * 2010-11-16 2013-02-27 复旦大学 基于边界扫描的可编程逻辑器件自动测试系统与方法
NL2006759C2 (en) 2011-05-10 2012-11-13 Jtag Technologies Bv A method of and an arrangement for automatically measuring electric connections of electronic circuit arrangements mounted on printed circuit boards.
CN103033741B (zh) * 2011-09-30 2015-05-27 重庆重邮信科通信技术有限公司 一种具有扫描链测试功能的芯片及测试方法
US20130086441A1 (en) * 2011-09-30 2013-04-04 Qualcomm Incorporated Dynamically self-reconfigurable daisy-chain of tap controllers
EP2595059B1 (de) * 2011-11-18 2014-10-01 IHP GmbH-Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik Testprozessor für asynchronen Chiptest
US8533546B1 (en) * 2011-12-01 2013-09-10 Pmc-Sierra Us, Inc. Reconfigurable scan chain connectivity to enable flexible device I/O utilization
EP2749894A1 (de) * 2012-12-31 2014-07-02 Testonica Lab Oü System und Verfahren für optimierte Leiterplattenprüfung und -konfiguration
US9904749B2 (en) * 2014-02-13 2018-02-27 Synopsys, Inc. Configurable FPGA sockets
US10481203B2 (en) 2015-04-04 2019-11-19 Nvidia Corporation Granular dynamic test systems and methods
US10317463B2 (en) 2015-10-27 2019-06-11 Nvidia Corporation Scan system interface (SSI) module
US10310013B2 (en) * 2016-12-12 2019-06-04 Samsung Electronics Co., Ltd. Test mode isolation and power reduction in embedded core-based digital systems of integrated circuits (ICs) with multiple power domains
US10866283B2 (en) 2018-11-29 2020-12-15 Nxp B.V. Test system with embedded tester
US11442106B2 (en) 2020-12-14 2022-09-13 Western Digital Technologies, Inc. Method and apparatus for debugging integrated circuit systems using scan chain
US20220357394A1 (en) * 2021-05-04 2022-11-10 University Of Florida Research Foundation, Incorporated Reconfigurable jtag architecture for implementation of programmable hardware security features in digital designs

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03252569A (ja) * 1990-02-26 1991-11-11 Advanced Micro Devicds Inc スキャンパス用レジスタ回路
DE69333479T2 (de) * 1992-06-17 2005-03-24 Texas Instruments Inc., Dallas Hierarchisches Verbindungsverfahren und -gerät
US5627842A (en) * 1993-01-21 1997-05-06 Digital Equipment Corporation Architecture for system-wide standardized intra-module and inter-module fault testing
JPH1090369A (ja) * 1996-05-08 1998-04-10 Texas Instr Inc <Ti> 集積回路の試験及び評価方法及び装置
JPH1019983A (ja) * 1996-07-02 1998-01-23 Matsushita Electric Ind Co Ltd バウンダリスキャンテスト方法
FR2790832B1 (fr) * 1999-03-08 2001-06-08 France Telecom Procede de test de circuits integres avec acces a des points de memorisation du circuit
US6343358B1 (en) * 1999-05-19 2002-01-29 Arm Limited Executing multiple debug instructions
US7003707B2 (en) * 2000-04-28 2006-02-21 Texas Instruments Incorporated IC tap/scan test port access with tap lock circuitry
US6961884B1 (en) * 2000-06-12 2005-11-01 Altera Corporation JTAG mirroring circuitry and methods
EP1233276B1 (de) * 2001-02-19 2004-12-01 Lucent Technologies Inc. Abtastverzögerungskette zur Verzögerungsmessung
JP2003004818A (ja) * 2001-06-26 2003-01-08 Mitsubishi Electric Corp 半導体集積回路およびテスト方法
JP2003121497A (ja) * 2001-10-09 2003-04-23 Fujitsu Ltd 論理回路テスト用スキャンパス回路及びこれを備えた集積回路装置
US7000163B1 (en) * 2002-02-25 2006-02-14 Lsi Logic Corporation Optimized buffering for JTAG boundary scan nets
US6862705B1 (en) * 2002-08-21 2005-03-01 Applied Micro Circuits Corporation System and method for testing high pin count electronic devices using a test board with test channels

Also Published As

Publication number Publication date
EP1595156B1 (de) 2006-11-29
EP1595156A2 (de) 2005-11-16
JP4579230B2 (ja) 2010-11-10
DE602004003475T2 (de) 2007-09-20
JP2006517295A (ja) 2006-07-20
WO2004070395A3 (en) 2004-09-16
US20060100810A1 (en) 2006-05-11
WO2004070395A2 (en) 2004-08-19
ATE347112T1 (de) 2006-12-15
US7409612B2 (en) 2008-08-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL

8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN