DE602004006841D1 - Elektronischer schaltkreis mit einem feld programmierbarer logischer zellen - Google Patents

Elektronischer schaltkreis mit einem feld programmierbarer logischer zellen

Info

Publication number
DE602004006841D1
DE602004006841D1 DE602004006841T DE602004006841T DE602004006841D1 DE 602004006841 D1 DE602004006841 D1 DE 602004006841D1 DE 602004006841 T DE602004006841 T DE 602004006841T DE 602004006841 T DE602004006841 T DE 602004006841T DE 602004006841 D1 DE602004006841 D1 DE 602004006841D1
Authority
DE
Germany
Prior art keywords
programmable logic
logic units
mode
bit operand
electronic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004006841T
Other languages
English (en)
Other versions
DE602004006841T2 (de
Inventor
Katarzyna Leijten-Nowak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of DE602004006841D1 publication Critical patent/DE602004006841D1/de
Application granted granted Critical
Publication of DE602004006841T2 publication Critical patent/DE602004006841T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
    • G06F7/5272—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products
DE602004006841T 2003-02-19 2004-02-12 Elektronischer schaltkreis mit einem feld programmierbarer logischer zellen Expired - Lifetime DE602004006841T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP03100383 2003-02-19
EP03100383 2003-02-19
PCT/IB2004/050108 WO2004075403A2 (en) 2003-02-19 2004-02-12 Electronic circuit with array of programmable logic cells

Publications (2)

Publication Number Publication Date
DE602004006841D1 true DE602004006841D1 (de) 2007-07-19
DE602004006841T2 DE602004006841T2 (de) 2008-02-07

Family

ID=32892951

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004006841T Expired - Lifetime DE602004006841T2 (de) 2003-02-19 2004-02-12 Elektronischer schaltkreis mit einem feld programmierbarer logischer zellen

Country Status (9)

Country Link
US (1) US7271617B2 (de)
EP (1) EP1597825B1 (de)
JP (1) JP2006518143A (de)
KR (1) KR101067727B1 (de)
CN (1) CN100576355C (de)
AT (1) ATE364260T1 (de)
DE (1) DE602004006841T2 (de)
TW (1) TW200505163A (de)
WO (1) WO2004075403A2 (de)

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* Cited by examiner, † Cited by third party
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US7461234B2 (en) * 2002-07-01 2008-12-02 Panasonic Corporation Loosely-biased heterogeneous reconfigurable arrays
US7471643B2 (en) 2002-07-01 2008-12-30 Panasonic Corporation Loosely-biased heterogeneous reconfigurable arrays
EP1854035A1 (de) * 2006-02-28 2007-11-14 Mentor Graphics Corporation Auf speicher basierendes trigger-erzeugungsschema in einer emulationsumgebung
US9450585B2 (en) 2011-04-20 2016-09-20 Microchip Technology Incorporated Selecting four signals from sixteen inputs
US20120268162A1 (en) * 2011-04-21 2012-10-25 Microchip Technology Incorporated Configurable logic cells
CN103257842B (zh) * 2012-02-17 2016-05-04 京微雅格（北京）科技有限公司 一种加法进位信息输出的方法和一种加法器
US9515656B2 (en) * 2013-11-01 2016-12-06 Semiconductor Energy Laboratory Co., Ltd. Reconfigurable circuit, storage device, and electronic device including storage device
CN103580678B (zh) * 2013-11-04 2016-08-17 复旦大学 一种基于fgpa的高性能查找表电路
JP2015231205A (ja) * 2014-06-06 2015-12-21 国立大学法人静岡大学 フィールドプログラマブルゲートアレイ、フィールドプログラマブルゲートアレイ開発ツール、及び、フィールドプログラマブルゲートアレイ開発方法
CN105589981B (zh) * 2014-10-22 2019-04-09 京微雅格（北京）科技有限公司 基于fpga的优化布局结构的加法器的工艺映射方法
US9954533B2 (en) * 2014-12-16 2018-04-24 Samsung Electronics Co., Ltd. DRAM-based reconfigurable logic
CN106528920B (zh) * 2016-09-27 2019-07-26 京微齐力(北京)科技有限公司 一种级联查找表的工艺映射方法
CN107885485B (zh) * 2017-11-08 2021-07-06 无锡中微亿芯有限公司 一种基于超前进位实现快速加法的可编程逻辑单元结构
CN108182303B (zh) * 2017-12-13 2020-08-28 京微齐力(北京)科技有限公司 基于混合功能存储单元的可编程器件结构
KR101986206B1 (ko) * 2018-01-03 2019-06-05 연세대학교 산학협력단 비휘발성 메모리 소자를 이용한 가변 입출력 구조의 룩업 테이블 회로
US10482209B1 (en) 2018-08-06 2019-11-19 HLS Logix LLC Field programmable operation block array
CN109992255B (zh) * 2019-03-07 2022-06-24 中科亿海微电子科技（苏州）有限公司 具有进位链结构的双输出查找表及可编程逻辑单元
CN114489563B (zh) * 2021-12-13 2023-08-29 深圳市紫光同创电子有限公司 一种电路结构

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6288570B1 (en) * 1993-09-02 2001-09-11 Xilinx, Inc. Logic structure and circuit for fast carry
US5546018A (en) * 1993-09-02 1996-08-13 Xilinx, Inc. Fast carry structure with synchronous input
US6427156B1 (en) * 1997-01-21 2002-07-30 Xilinx, Inc. Configurable logic block with AND gate for efficient multiplication in FPGAS
US5920202A (en) * 1997-02-26 1999-07-06 Xilinx, Inc. Configurable logic element with ability to evaluate five and six input functions
US5963050A (en) * 1997-02-26 1999-10-05 Xilinx, Inc. Configurable logic element with fast feedback paths
US5889411A (en) * 1997-02-26 1999-03-30 Xilinx, Inc. FPGA having logic element carry chains capable of generating wide XOR functions
US6157209A (en) * 1998-12-18 2000-12-05 Xilinx, Inc. Loadable up-down counter with asynchronous reset
US6278290B1 (en) * 1999-08-13 2001-08-21 Xilinx, Inc. Method and circuit for operating programmable logic devices during power-up and stand-by modes
US6466052B1 (en) * 2001-05-15 2002-10-15 Xilinx, Inc. Implementing wide multiplexers in an FPGA using a horizontal chain structure
US6617876B1 (en) * 2002-02-01 2003-09-09 Xilinx, Inc. Structures and methods for distributing high-fanout signals in FPGAs using carry multiplexers
US6937064B1 (en) * 2002-10-24 2005-08-30 Altera Corporation Versatile logic element and logic array block
JP2006519548A (ja) * 2003-02-19 2006-08-24 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ プログラム可能な論理セルのアレイをもつ電子回路
US7193433B1 (en) * 2005-06-14 2007-03-20 Xilinx, Inc. Programmable logic block having lookup table with partial output signal driving carry multiplexer

Also Published As

Publication number Publication date
CN100576355C (zh) 2009-12-30
KR20050106014A (ko) 2005-11-08
JP2006518143A (ja) 2006-08-03
TW200505163A (en) 2005-02-01
KR101067727B1 (ko) 2011-09-28
WO2004075403A2 (en) 2004-09-02
US20060158218A1 (en) 2006-07-20
EP1597825A2 (de) 2005-11-23
ATE364260T1 (de) 2007-06-15
WO2004075403A3 (en) 2004-11-04
US7271617B2 (en) 2007-09-18
DE602004006841T2 (de) 2008-02-07
CN1751361A (zh) 2006-03-22
EP1597825B1 (de) 2007-06-06

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8364 No opposition during term of opposition