DE602004017270D1 - Speicheranordnung mit schneller Leseoperation und niedrigerem Stromverbrauch sowie entsprechendes Leseverfahren - Google Patents

Speicheranordnung mit schneller Leseoperation und niedrigerem Stromverbrauch sowie entsprechendes Leseverfahren

Info

Publication number
DE602004017270D1
DE602004017270D1 DE602004017270T DE602004017270T DE602004017270D1 DE 602004017270 D1 DE602004017270 D1 DE 602004017270D1 DE 602004017270 T DE602004017270 T DE 602004017270T DE 602004017270 T DE602004017270 T DE 602004017270T DE 602004017270 D1 DE602004017270 D1 DE 602004017270D1
Authority
DE
Germany
Prior art keywords
power consumption
read operation
lower power
reading method
memory arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004017270T
Other languages
English (en)
Inventor
Claudio Resta
Ferdinando Bedeschi
Guido Torelli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Ovonyx Inc
Original Assignee
STMicroelectronics SRL
Ovonyx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL, Ovonyx Inc filed Critical STMicroelectronics SRL
Publication of DE602004017270D1 publication Critical patent/DE602004017270D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
DE602004017270T 2003-12-23 2004-12-22 Speicheranordnung mit schneller Leseoperation und niedrigerem Stromverbrauch sowie entsprechendes Leseverfahren Active DE602004017270D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03425820A EP1548744A1 (de) 2003-12-23 2003-12-23 Speicheranordnung mit schneller Leseoperation und niedrigerem Stromverbrauch sowie entsprechendes Leseverfahren

Publications (1)

Publication Number Publication Date
DE602004017270D1 true DE602004017270D1 (de) 2008-12-04

Family

ID=34530875

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004017270T Active DE602004017270D1 (de) 2003-12-23 2004-12-22 Speicheranordnung mit schneller Leseoperation und niedrigerem Stromverbrauch sowie entsprechendes Leseverfahren

Country Status (3)

Country Link
US (1) US7203087B2 (de)
EP (1) EP1548744A1 (de)
DE (1) DE602004017270D1 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7471556B2 (en) * 2007-05-15 2008-12-30 Super Talent Electronics, Inc. Local bank write buffers for accelerating a phase-change memory
US7889544B2 (en) 2004-04-05 2011-02-15 Super Talent Electronics, Inc. High-speed controller for phase-change memory peripheral device
US7966429B2 (en) * 2007-05-28 2011-06-21 Super Talent Electronics, Inc. Peripheral devices using phase-change memory
US7282730B2 (en) * 2005-01-18 2007-10-16 Intel Corporation Forming a carbon layer between phase change layers of a phase change memory
US7501880B2 (en) * 2005-02-28 2009-03-10 International Business Machines Corporation Body-biased enhanced precision current mirror
US7154774B2 (en) * 2005-03-30 2006-12-26 Ovonyx, Inc. Detecting switching of access elements of phase change memory cells
KR100699837B1 (ko) * 2005-04-04 2007-03-27 삼성전자주식회사 반도체 메모리 장치 및 반도체 메모리 장치의 프로그래밍방법
US7655938B2 (en) * 2005-07-20 2010-02-02 Kuo Charles C Phase change memory with U-shaped chalcogenide cell
KR100690914B1 (ko) * 2005-08-10 2007-03-09 삼성전자주식회사 상변화 메모리 장치
US8143653B2 (en) 2005-08-10 2012-03-27 Samsung Electronics Co., Ltd. Variable resistance memory device and system thereof
KR100757410B1 (ko) * 2005-09-16 2007-09-11 삼성전자주식회사 상 변화 메모리 장치 및 그것의 프로그램 방법
US20070292985A1 (en) * 2006-06-16 2007-12-20 Yuegang Zhang Phase change memory with nanofiber heater
US7626860B2 (en) * 2007-03-23 2009-12-01 International Business Machines Corporation Optimized phase change write method
US20080270811A1 (en) * 2007-04-26 2008-10-30 Super Talent Electronics Inc. Fast Suspend-Resume of Computer Motherboard Using Phase-Change Memory
US7643334B1 (en) 2007-04-26 2010-01-05 Super Talent Electronics, Inc. High-speed controller for phase-change memory peripheral device
US7440316B1 (en) 2007-04-30 2008-10-21 Super Talent Electronics, Inc 8/9 and 8/10-bit encoding to reduce peak surge currents when writing phase-change memory
US7791933B2 (en) * 2007-12-21 2010-09-07 International Business Machines Corporation Optimized phase change write method
US7848133B2 (en) * 2007-12-31 2010-12-07 Intel Corporation Phase change memory with bipolar junction transistor select device
US7869267B2 (en) * 2008-12-29 2011-01-11 Numonyx B.V. Method for low power accessing a phase change memory device
WO2010076833A1 (en) * 2008-12-31 2010-07-08 Fabio Pellizzer Word-line driver including pull-up resistor and pull-down transistor
US8897072B2 (en) 2012-10-11 2014-11-25 Micron Technology, Inc. Sensing data stored in memory
US9786345B1 (en) * 2016-09-16 2017-10-10 Micron Technology, Inc. Compensation for threshold voltage variation of memory cell components
US10424358B2 (en) 2017-06-12 2019-09-24 Sandisk Technologies Llc Bias control circuit with distributed architecture for memory cells
US11139025B2 (en) 2020-01-22 2021-10-05 International Business Machines Corporation Multi-level cell threshold voltage operation of one-selector-one-resistor structure included in a crossbar array

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5789776A (en) * 1995-09-22 1998-08-04 Nvx Corporation Single poly memory cell and array
US5883827A (en) * 1996-08-26 1999-03-16 Micron Technology, Inc. Method and apparatus for reading/writing data in a memory system including programmable resistors
US6590807B2 (en) * 2001-08-02 2003-07-08 Intel Corporation Method for reading a structural phase-change memory
EP1326258B1 (de) * 2001-12-27 2016-03-23 STMicroelectronics Srl Nichtflüchtiger Phasenänderungsspeicher mit nur einer Speisespannung, Kaskoden-Spaltenauswahl und gleichzeitigen Wortlese- und -schreiboperationen
US6498758B1 (en) * 2002-01-16 2002-12-24 Lsi Logic Corporation Twisted bitlines to reduce coupling effects (dual port memories)
JP2004110961A (ja) * 2002-09-19 2004-04-08 Renesas Technology Corp 電流駆動回路および半導体記憶装置
US6965521B2 (en) * 2003-07-31 2005-11-15 Bae Systems, Information And Electronics Systems Integration, Inc. Read/write circuit for accessing chalcogenide non-volatile memory cells

Also Published As

Publication number Publication date
US7203087B2 (en) 2007-04-10
EP1548744A1 (de) 2005-06-29
US20050185572A1 (en) 2005-08-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition