DE602005010652D1 - Entwurf für Kanalausrichtung, Fehlerbehandlung und Taktrouting unter Verwendung von festverdrahteten Blöcken zur Datenübertragung innerhalb von programmierbaren integrierten Schaltungen - Google Patents
Entwurf für Kanalausrichtung, Fehlerbehandlung und Taktrouting unter Verwendung von festverdrahteten Blöcken zur Datenübertragung innerhalb von programmierbaren integrierten SchaltungenInfo
- Publication number
- DE602005010652D1 DE602005010652D1 DE602005010652T DE602005010652T DE602005010652D1 DE 602005010652 D1 DE602005010652 D1 DE 602005010652D1 DE 602005010652 T DE602005010652 T DE 602005010652T DE 602005010652 T DE602005010652 T DE 602005010652T DE 602005010652 D1 DE602005010652 D1 DE 602005010652D1
- Authority
- DE
- Germany
- Prior art keywords
- channel alignment
- error handling
- data
- hip
- programmable logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Logic Circuits (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/011,543 US7434192B2 (en) | 2004-12-13 | 2004-12-13 | Techniques for optimizing design of a hard intellectual property block for data transmission |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602005010652D1 true DE602005010652D1 (de) | 2008-12-11 |
Family
ID=35406162
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602005010652T Active DE602005010652D1 (de) | 2004-12-13 | 2005-09-02 | Entwurf für Kanalausrichtung, Fehlerbehandlung und Taktrouting unter Verwendung von festverdrahteten Blöcken zur Datenübertragung innerhalb von programmierbaren integrierten Schaltungen |
Country Status (6)
Country | Link |
---|---|
US (2) | US7434192B2 (de) |
EP (1) | EP1670199B1 (de) |
JP (1) | JP2006174460A (de) |
CN (1) | CN1791120B (de) |
AT (1) | ATE413049T1 (de) |
DE (1) | DE602005010652D1 (de) |
Families Citing this family (28)
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US7218141B2 (en) * | 2004-12-07 | 2007-05-15 | Altera Corporation | Techniques for implementing hardwired decoders in differential input circuits |
WO2006136201A1 (de) * | 2005-06-23 | 2006-12-28 | Hilscher Gesellschaft für Systemautomation mbH | Verfahren zur datenkommunikation von busteilnehmern eines offenen automatisierungssystems |
US7548085B2 (en) | 2005-07-15 | 2009-06-16 | Tabula, Inc. | Random access of user design states in a configurable IC |
US7375550B1 (en) * | 2005-07-15 | 2008-05-20 | Tabula, Inc. | Configurable IC with packet switch configuration network |
JP5127241B2 (ja) * | 2007-01-19 | 2013-01-23 | 三菱電機株式会社 | 剰余演算装置及び剰余演算方法 |
US8069425B2 (en) * | 2007-06-27 | 2011-11-29 | Tabula, Inc. | Translating a user design in a configurable IC for debugging the user design |
US7652498B2 (en) * | 2007-06-27 | 2010-01-26 | Tabula, Inc. | Integrated circuit with delay selecting input selection circuitry |
US8412990B2 (en) * | 2007-06-27 | 2013-04-02 | Tabula, Inc. | Dynamically tracking data values in a configurable IC |
US7839162B2 (en) | 2007-06-27 | 2010-11-23 | Tabula, Inc. | Configurable IC with deskewing circuits |
WO2009039462A1 (en) * | 2007-09-19 | 2009-03-26 | Tabula, Inc. | Method and system for reporting on a primary circuit structure of an integrated circuit (ic) using a secondary circuit structure of the ic |
WO2009046300A2 (en) * | 2007-10-05 | 2009-04-09 | Violin Memory, Inc. | Mesosynchronous data bus apparatus and method of data transmission |
WO2010016857A1 (en) | 2008-08-04 | 2010-02-11 | Tabula, Inc. | Trigger circuits and event counters for an ic |
US8136080B2 (en) * | 2008-09-22 | 2012-03-13 | Verizon Patent And Licensing Inc. | Graphic rendering of circuit positions |
US8072234B2 (en) | 2009-09-21 | 2011-12-06 | Tabula, Inc. | Micro-granular delay testing of configurable ICs |
US8638792B2 (en) * | 2010-01-22 | 2014-01-28 | Synopsys, Inc. | Packet switch based logic replication |
US8397195B2 (en) * | 2010-01-22 | 2013-03-12 | Synopsys, Inc. | Method and system for packet switch based logic replication |
US8839066B2 (en) * | 2010-03-22 | 2014-09-16 | Infinera Corporation | Apparatus and method for optimizing an iterative FEC decoder |
CN102710240B (zh) * | 2011-03-08 | 2016-03-02 | 浙江彩虹鱼通讯技术有限公司 | 信号处理装置、方法、serdes和处理器 |
WO2012149239A1 (en) * | 2011-04-28 | 2012-11-01 | Thomson Licensing | Video buffer management technique |
CN102761396B (zh) * | 2012-07-30 | 2015-01-07 | 哈尔滨工业大学 | 基于fpga的高速串行接口 |
US9436565B2 (en) | 2013-07-04 | 2016-09-06 | Altera Corporation | Non-intrusive monitoring and control of integrated circuits |
CN105335321A (zh) * | 2015-08-31 | 2016-02-17 | 成都嘉纳海威科技有限责任公司 | 一种用于数据收发的自对准接口电路 |
CN105263264A (zh) * | 2015-10-08 | 2016-01-20 | 上海新跃仪表厂 | 具有简单连接结构的复杂走线pcb及其制备方法 |
US10002100B2 (en) | 2016-02-02 | 2018-06-19 | Xilinx, Inc. | Active-by-active programmable device |
US10042806B2 (en) | 2016-02-02 | 2018-08-07 | Xilinx, Inc. | System-level interconnect ring for a programmable integrated circuit |
KR102093459B1 (ko) * | 2016-02-02 | 2020-03-25 | 자일링크스 인코포레이티드 | 액티브-바이-액티브 프로그래밍가능 디바이스 |
CN111385065B (zh) * | 2020-05-29 | 2020-09-11 | 湖南戎腾网络科技有限公司 | 一种接口速率自适应装置及方法 |
CN114371822B (zh) * | 2021-12-13 | 2023-12-01 | 青岛信芯微电子科技股份有限公司 | 数据传输装置、芯片、显示设备和数据传输方法 |
Family Cites Families (29)
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US4062699A (en) * | 1976-02-20 | 1977-12-13 | Western Digital Corporation | Method for fabricating diffusion self-aligned short channel MOS device |
US4745564B2 (en) * | 1986-02-07 | 2000-07-04 | Us Agriculture | Impact detection apparatus |
US5369624A (en) * | 1993-03-26 | 1994-11-29 | Siemens Medical Systems, Inc. | Digital beamformer having multi-phase parallel processing |
US5576910A (en) * | 1993-06-04 | 1996-11-19 | Cirrus Logic, Inc. | Burst comparison and sequential technique for determining servo control in a mass storage disk device |
JP2694807B2 (ja) * | 1993-12-16 | 1997-12-24 | 日本電気株式会社 | データ伝送方式 |
US5708436A (en) * | 1996-06-24 | 1998-01-13 | Northrop Grumman Corporation | Multi-mode radar system having real-time ultra high resolution synthetic aperture radar (SAR) capability |
US5825202A (en) * | 1996-09-26 | 1998-10-20 | Xilinx, Inc. | Integrated circuit with field programmable and application specific logic areas |
US5874834A (en) * | 1997-03-04 | 1999-02-23 | Xilinx, Inc. | Field programmable gate array with distributed gate-array functionality |
WO1999014870A2 (en) * | 1997-09-15 | 1999-03-25 | Adaptive Telecom, Inc. | Practical space-time radio method for cdma communication capacity enhancement |
CN1214689C (zh) * | 1998-06-19 | 2005-08-10 | 杜松网络公司 | 用于把数据导向目的地址的设备和方法 |
US6317804B1 (en) * | 1998-11-30 | 2001-11-13 | Philips Semiconductors Inc. | Concurrent serial interconnect for integrating functional blocks in an integrated circuit device |
US6292116B1 (en) * | 1999-05-17 | 2001-09-18 | Altera Corporation | Techniques and circuitry for accurately sampling high frequency data signals input to an integrated circuit |
GB0006291D0 (en) | 2000-03-15 | 2000-05-03 | Lucent Technologies Inc | Data communication link |
US6490707B1 (en) * | 2000-07-13 | 2002-12-03 | Xilinx, Inc. | Method for converting programmable logic devices into standard cell devices |
US6515509B1 (en) * | 2000-07-13 | 2003-02-04 | Xilinx, Inc. | Programmable logic device structures in standard cell devices |
US6526563B1 (en) * | 2000-07-13 | 2003-02-25 | Xilinx, Inc. | Method for improving area in reduced programmable logic devices |
AU2001288828A1 (en) * | 2000-09-14 | 2002-03-26 | Ensemble Communications, Inc. | A system and method for wireless communication in a frequency division duplexingregion |
EP1417590A2 (de) * | 2000-10-02 | 2004-05-12 | Altera Corporation (a Delaware Corporation) | Programmierbare logische integrierte schaltung mit spezifischen prozessorkomponenten |
US6650140B2 (en) * | 2001-03-19 | 2003-11-18 | Altera Corporation | Programmable logic device with high speed serial interface circuitry |
US7602818B2 (en) * | 2001-04-27 | 2009-10-13 | The Boeing Company | Fibre channel transceiver |
US6874107B2 (en) * | 2001-07-24 | 2005-03-29 | Xilinx, Inc. | Integrated testing of serializer/deserializer in FPGA |
US6744274B1 (en) * | 2001-08-09 | 2004-06-01 | Stretch, Inc. | Programmable logic core adapter |
US6750675B2 (en) * | 2001-09-17 | 2004-06-15 | Altera Corporation | Programmable logic devices with multi-standard byte synchronization and channel alignment for communication |
US7496780B2 (en) * | 2003-02-11 | 2009-02-24 | Agere Systems Inc. | Reduction of data skew in parallel processing circuits |
US6894530B1 (en) * | 2003-04-28 | 2005-05-17 | Lattice Semiconductor Corporation | Programmable and fixed logic circuitry for high-speed interfaces |
US6724328B1 (en) * | 2003-06-03 | 2004-04-20 | Altera Corporation | Byte alignment for serial data receiver |
US6879598B2 (en) * | 2003-06-11 | 2005-04-12 | Lattice Semiconductor Corporation | Flexible media access control architecture |
WO2004114166A2 (en) * | 2003-06-18 | 2004-12-29 | Ambric, Inc. | Integrated circuit development system |
US7129859B2 (en) * | 2004-07-22 | 2006-10-31 | International Business Machines Corporation | Method and apparatus for minimizing threshold variation from body charge in silicon-on-insulator circuitry |
-
2004
- 2004-12-13 US US11/011,543 patent/US7434192B2/en not_active Expired - Fee Related
-
2005
- 2005-09-02 EP EP05255410A patent/EP1670199B1/de not_active Not-in-force
- 2005-09-02 DE DE602005010652T patent/DE602005010652D1/de active Active
- 2005-09-02 AT AT05255410T patent/ATE413049T1/de not_active IP Right Cessation
- 2005-12-13 CN CN200510137027.6A patent/CN1791120B/zh not_active Expired - Fee Related
- 2005-12-13 JP JP2005358600A patent/JP2006174460A/ja active Pending
-
2008
- 2008-08-18 US US12/193,532 patent/US7843216B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20060125517A1 (en) | 2006-06-15 |
EP1670199B1 (de) | 2008-10-29 |
US20080297192A1 (en) | 2008-12-04 |
CN1791120A (zh) | 2006-06-21 |
JP2006174460A (ja) | 2006-06-29 |
US7434192B2 (en) | 2008-10-07 |
EP1670199A1 (de) | 2006-06-14 |
US7843216B2 (en) | 2010-11-30 |
CN1791120B (zh) | 2010-10-13 |
ATE413049T1 (de) | 2008-11-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |