DE602005023542D1 - Einrichtung und verfahren zum ausführen einer dma-task - Google Patents

Einrichtung und verfahren zum ausführen einer dma-task

Info

Publication number
DE602005023542D1
DE602005023542D1 DE602005023542T DE602005023542T DE602005023542D1 DE 602005023542 D1 DE602005023542 D1 DE 602005023542D1 DE 602005023542 T DE602005023542 T DE 602005023542T DE 602005023542 T DE602005023542 T DE 602005023542T DE 602005023542 D1 DE602005023542 D1 DE 602005023542D1
Authority
DE
Germany
Prior art keywords
executing
dma task
dma
task
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005023542T
Other languages
English (en)
Inventor
Uri Shasha
Sagi Gurfinkel
Gilad Hassid
Eran Kahn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of DE602005023542D1 publication Critical patent/DE602005023542D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
DE602005023542T 2005-06-30 2005-06-30 Einrichtung und verfahren zum ausführen einer dma-task Active DE602005023542D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2005/052176 WO2007003987A1 (en) 2005-06-30 2005-06-30 Device and method for executing a dma task

Publications (1)

Publication Number Publication Date
DE602005023542D1 true DE602005023542D1 (de) 2010-10-21

Family

ID=35094494

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005023542T Active DE602005023542D1 (de) 2005-06-30 2005-06-30 Einrichtung und verfahren zum ausführen einer dma-task

Country Status (4)

Country Link
US (1) US20090125647A1 (de)
EP (1) EP1899827B1 (de)
DE (1) DE602005023542D1 (de)
WO (1) WO2007003987A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
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DE602005017948D1 (de) * 2005-06-30 2010-01-07 Freescale Semiconductor Inc Einrichtung und verfahren zum arbitrieren zwischen direktspeicherzugriffs-task-anforderungen
US7930444B2 (en) 2005-06-30 2011-04-19 Freescale Semiconductor, Inc. Device and method for controlling multiple DMA tasks
EP1899826B1 (de) 2005-06-30 2011-03-16 Freescale Semiconductor, Inc. Einrichtung und verfahren zur steuerung einer ausführung einer dma-task
JP4516999B2 (ja) * 2008-03-28 2010-08-04 富士通株式会社 データ通信制御装置、データ通信制御方法およびそのためのプログラム
US8250253B2 (en) * 2010-06-23 2012-08-21 Intel Corporation Method, apparatus and system for reduced channel starvation in a DMA engine
US9779044B2 (en) 2014-11-25 2017-10-03 Nxp Usa, Inc. Access extent monitoring for data transfer reduction
DE102016211386A1 (de) * 2016-06-14 2017-12-14 Robert Bosch Gmbh Verfahren zum Betreiben einer Recheneinheit
US11314674B2 (en) 2020-02-14 2022-04-26 Google Llc Direct memory access architecture with multi-level multi-striding

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DE602005017948D1 (de) * 2005-06-30 2010-01-07 Freescale Semiconductor Inc Einrichtung und verfahren zum arbitrieren zwischen direktspeicherzugriffs-task-anforderungen
EP1899826B1 (de) * 2005-06-30 2011-03-16 Freescale Semiconductor, Inc. Einrichtung und verfahren zur steuerung einer ausführung einer dma-task
US7930444B2 (en) * 2005-06-30 2011-04-19 Freescale Semiconductor, Inc. Device and method for controlling multiple DMA tasks

Also Published As

Publication number Publication date
US20090125647A1 (en) 2009-05-14
EP1899827B1 (de) 2010-09-08
EP1899827A1 (de) 2008-03-19
WO2007003987A1 (en) 2007-01-11

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