DE602005025407D1 - Fehlerschutz für gruppen von datenwörtern - Google Patents

Fehlerschutz für gruppen von datenwörtern

Info

Publication number
DE602005025407D1
DE602005025407D1 DE602005025407T DE602005025407T DE602005025407D1 DE 602005025407 D1 DE602005025407 D1 DE 602005025407D1 DE 602005025407 T DE602005025407 T DE 602005025407T DE 602005025407 T DE602005025407 T DE 602005025407T DE 602005025407 D1 DE602005025407 D1 DE 602005025407D1
Authority
DE
Germany
Prior art keywords
error
data word
data words
correction code
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005025407T
Other languages
English (en)
Inventor
Oded Trainin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cisco Technology Inc
Original Assignee
Cisco Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cisco Technology Inc filed Critical Cisco Technology Inc
Publication of DE602005025407D1 publication Critical patent/DE602005025407D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2909—Product codes
    • H03M13/2915—Product codes with an error detection code in one dimension
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2942—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes wherein a block of parity bits is computed only from combined information bits or only from parity bits, e.g. a second block of parity bits is computed from a first block of parity bits obtained by systematic encoding of a block of information bits, or a block of parity bits is obtained by an XOR combination of sub-blocks of information bits
DE602005025407T 2005-01-22 2005-12-26 Fehlerschutz für gruppen von datenwörtern Active DE602005025407D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/040,678 US7350131B2 (en) 2005-01-22 2005-01-22 Error protecting groups of data words
PCT/US2005/046910 WO2006078418A2 (en) 2005-01-22 2005-12-26 Error protecting groups of data words

Publications (1)

Publication Number Publication Date
DE602005025407D1 true DE602005025407D1 (de) 2011-01-27

Family

ID=36692698

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005025407T Active DE602005025407D1 (de) 2005-01-22 2005-12-26 Fehlerschutz für gruppen von datenwörtern

Country Status (6)

Country Link
US (1) US7350131B2 (de)
EP (1) EP1839394B1 (de)
CN (1) CN101040445B (de)
AT (1) ATE492072T1 (de)
DE (1) DE602005025407D1 (de)
WO (1) WO2006078418A2 (de)

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US10318588B2 (en) 2017-07-01 2019-06-11 Cisco Technology, Inc. Searching varying selectable physical blocks of entries within a content-addressable memory
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DE102018126051A1 (de) * 2018-01-12 2019-07-18 Taiwan Semiconductor Manufacturing Co. Ltd. Neuartige Speichervorrichtung
US11194475B2 (en) 2018-04-16 2021-12-07 Cisco Technology, Inc. Coordinated updating and searching a content-addressable memory including for packet processing operations
US11467899B2 (en) 2018-04-16 2022-10-11 Cisco Technology, Inc. Efficient content-addressable memory lookup result integrity checking and correcting operations including for protecting the accuracy of packet processing operations
US10496299B2 (en) 2018-04-16 2019-12-03 Cisco Technology, Inc. Efficient content-addressable memory entry integrity checking including for protecting the accuracy of packet processing operations
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US11108894B2 (en) * 2019-08-09 2021-08-31 Microsoft Technology Licensing, Llc Masked packet checksums for more efficient digital communication
US11694761B2 (en) * 2021-09-17 2023-07-04 Nxp B.V. Method to increase the usable word width of a memory providing an error correction scheme

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Also Published As

Publication number Publication date
WO2006078418A3 (en) 2007-01-25
US20060168494A1 (en) 2006-07-27
CN101040445B (zh) 2012-08-08
EP1839394A4 (de) 2008-04-02
EP1839394B1 (de) 2010-12-15
EP1839394A2 (de) 2007-10-03
ATE492072T1 (de) 2011-01-15
WO2006078418A2 (en) 2006-07-27
US7350131B2 (en) 2008-03-25
CN101040445A (zh) 2007-09-19

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