DE602006009967D1 - Verfahren zur gemeinsamen herstellung von elektronischen 3d-modulen - Google Patents

Verfahren zur gemeinsamen herstellung von elektronischen 3d-modulen

Info

Publication number
DE602006009967D1
DE602006009967D1 DE602006009967T DE602006009967T DE602006009967D1 DE 602006009967 D1 DE602006009967 D1 DE 602006009967D1 DE 602006009967 T DE602006009967 T DE 602006009967T DE 602006009967 T DE602006009967 T DE 602006009967T DE 602006009967 D1 DE602006009967 D1 DE 602006009967D1
Authority
DE
Germany
Prior art keywords
modules
electronic
joint manufacture
joint
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006009967T
Other languages
English (en)
Inventor
Christian Val
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3D Plus SA
Original Assignee
3D Plus SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3D Plus SA filed Critical 3D Plus SA
Publication of DE602006009967D1 publication Critical patent/DE602006009967D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
DE602006009967T 2005-12-23 2006-12-19 Verfahren zur gemeinsamen herstellung von elektronischen 3d-modulen Active DE602006009967D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0513217A FR2895568B1 (fr) 2005-12-23 2005-12-23 Procede de fabrication collective de modules electroniques 3d
PCT/EP2006/069948 WO2007071696A1 (fr) 2005-12-23 2006-12-19 Procede de fabrication collective de modules electroniques 3d

Publications (1)

Publication Number Publication Date
DE602006009967D1 true DE602006009967D1 (de) 2009-12-03

Family

ID=36764718

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006009967T Active DE602006009967D1 (de) 2005-12-23 2006-12-19 Verfahren zur gemeinsamen herstellung von elektronischen 3d-modulen

Country Status (6)

Country Link
US (1) US7877874B2 (de)
EP (1) EP1966825B1 (de)
JP (1) JP5211396B2 (de)
DE (1) DE602006009967D1 (de)
FR (1) FR2895568B1 (de)
WO (1) WO2007071696A1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2905198B1 (fr) * 2006-08-22 2008-10-17 3D Plus Sa Sa Procede de fabrication collective de modules electroniques 3d
FR2911995B1 (fr) * 2007-01-30 2009-03-06 3D Plus Sa Sa Procede d'interconnexion de tranches electroniques
US7846772B2 (en) * 2008-06-23 2010-12-07 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US7745259B2 (en) * 2008-06-30 2010-06-29 Headway Technologies, Inc. Layered chip package and method of manufacturing same
FR2940521B1 (fr) 2008-12-19 2011-11-11 3D Plus Procede de fabrication collective de modules electroniques pour montage en surface
EP2202789A1 (de) * 2008-12-24 2010-06-30 Nxp B.V. Stapel von verkapselten IC-Chips mit seitlichen Leiterbahnen
EP2207200A1 (de) * 2008-12-24 2010-07-14 Nxp B.V. Stapel von verkapselten IC-Chips mit seitlichen Leiterbahnen
US8274165B2 (en) * 2009-02-10 2012-09-25 Headway Technologies, Inc. Semiconductor substrate, laminated chip package, semiconductor plate and method of manufacturing the same
JP4956567B2 (ja) 2009-02-17 2012-06-20 本田技研工業株式会社 燃料電池システムおよび燃料電池システムの制御方法
FR2943176B1 (fr) 2009-03-10 2011-08-05 3D Plus Procede de positionnement des puces lors de la fabrication d'une plaque reconstituee
US8569878B2 (en) * 2009-10-22 2013-10-29 Headway Technologies, Inc. Semiconductor substrate, laminated chip package, semiconductor plate and method of manufacturing the same
US7902677B1 (en) * 2009-10-28 2011-03-08 Headway Technologies, Inc. Composite layered chip package and method of manufacturing same
US8263876B2 (en) * 2009-12-30 2012-09-11 Harvatek Corporation Conductive substrate structure with conductive channels formed by using a two-sided cut approach and a method for manufacturing the same
US8587125B2 (en) 2010-01-22 2013-11-19 Headway Technologies, Inc. Method of manufacturing layered chip package
US8298862B2 (en) 2010-02-04 2012-10-30 Headway Technologies, Inc. Method of manufacturing layered chip package
US8426946B2 (en) 2010-06-28 2013-04-23 Headway Technologies, Inc. Laminated semiconductor substrate, laminated chip package and method of manufacturing the same
US8426948B2 (en) * 2010-08-02 2013-04-23 Headway Technologies, Inc. Laminated semiconductor wafer, laminated chip package and method of manufacturing the same
US8541887B2 (en) 2010-09-03 2013-09-24 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8441112B2 (en) * 2010-10-01 2013-05-14 Headway Technologies, Inc. Method of manufacturing layered chip package
US8618646B2 (en) 2010-10-12 2013-12-31 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8652877B2 (en) * 2010-12-06 2014-02-18 Headway Technologies, Inc. Method of manufacturing layered chip package
US8824161B2 (en) 2012-06-15 2014-09-02 Medtronic, Inc. Integrated circuit packaging for implantable medical devices
US9252415B2 (en) 2012-06-15 2016-02-02 Medtronic, Inc. Power sources suitable for use in implantable medical devices and corresponding fabrication methods
US11213690B2 (en) 2012-06-15 2022-01-04 Medtronic, Inc. Wafer level packages of high voltage units for implantable medical devices
KR20150141440A (ko) * 2014-06-10 2015-12-18 삼성전자주식회사 반도체 칩, 이를 갖는 반도체 패키지 및 반도체 패키지의 제조 방법
FR3048123B1 (fr) 2016-02-19 2018-11-16 3D Plus Procede d'interconnexion chip on chip miniaturisee d'un module electronique 3d

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2403688A1 (fr) 1977-09-16 1979-04-13 Thomson Csf Dispositif attenuateur reglable
FR2456388A1 (fr) * 1979-05-10 1980-12-05 Thomson Brandt Microboitier de circuit electronique, et circuit hybride comportant un tel microboitier
US4251644A (en) * 1979-10-01 1981-02-17 Copolymer Rubber & Chemical Corporation Polar resins having improved characteristics by blending with EPM and EPDM polymers
FR2485262A1 (fr) * 1980-06-19 1981-12-24 Thomson Csf Boitier d'encapsulation resistant a de fortes pressions externes
FR2485796A1 (fr) * 1980-06-24 1981-12-31 Thomson Csf Resistance electrique chauffante et tete d'imprimante thermique comportant de telles resistances chauffantes
FR2525815B1 (fr) * 1982-04-27 1985-08-30 Inf Milit Spatiale Aeronaut Substrat composite a haute conduction thermique et application aux boitiers de dispositifs semi-conducteurs
FR2527039A1 (fr) * 1982-05-14 1983-11-18 Inf Milit Spatiale Aeronaut Dispositif de protection d'un dispositif electronique contre les tensions engendrees par un champ electromagnetique
FR2538618B1 (fr) * 1982-12-28 1986-03-07 Inf Milit Spatiale Aeronaut Boitier pour composant electronique comportant un element fixant l'humidite
FR2547113B1 (fr) * 1983-06-03 1986-11-07 Inf Milit Spatiale Aeronaut Boitier d'encapsulation de composant electronique, durci vis-a-vis des radiations
FR2550009B1 (fr) * 1983-07-29 1986-01-24 Inf Milit Spatiale Aeronaut Boitier de composant electronique muni d'un condensateur
US5237204A (en) * 1984-05-25 1993-08-17 Compagnie D'informatique Militaire Spatiale Et Aeronautique Electric potential distribution device and an electronic component case incorporating such a device
FR2591801B1 (fr) * 1985-12-17 1988-10-14 Inf Milit Spatiale Aeronaut Boitier d'encapsulation d'un circuit electronique
FR2614134B1 (fr) * 1987-04-17 1990-01-26 Cimsa Sintra Procede de connexion d'un composant electronique pour son test et son montage, et dispositif de mise en oeuvre de ce procede
US5016138A (en) * 1987-10-27 1991-05-14 Woodman John K Three dimensional integrated circuit package
FR2666190B1 (fr) * 1990-08-24 1996-07-12 Thomson Csf Procede et dispositif d'encapsulation hermetique de composants electroniques.
US5847448A (en) * 1990-12-11 1998-12-08 Thomson-Csf Method and device for interconnecting integrated circuits in three dimensions
FR2674680B1 (fr) * 1991-03-26 1993-12-03 Thomson Csf Procede de realisation de connexions coaxiales pour composant electronique, et boitier de composant comportant de telles connexions.
FR2688629A1 (fr) * 1992-03-10 1993-09-17 Thomson Csf Procede et dispositif d'encapsulation en trois dimensions de pastilles semi-conductrices.
FR2688630B1 (fr) * 1992-03-13 2001-08-10 Thomson Csf Procede et dispositif d'interconnexion en trois dimensions de boitiers de composants electroniques.
FR2691836B1 (fr) * 1992-05-27 1997-04-30 Ela Medical Sa Procede de fabrication d'un dispositif a semi-conducteurs comportant au moins une puce et dispositif correspondant.
FR2696871B1 (fr) * 1992-10-13 1994-11-18 Thomson Csf Procédé d'interconnexion 3D de boîtiers de composants électroniques, et composants 3D en résultant.
FR2709020B1 (fr) * 1993-08-13 1995-09-08 Thomson Csf Procédé d'interconnexion de pastilles semi-conductrices en trois dimensions, et composant en résultant.
US5502667A (en) * 1993-09-13 1996-03-26 International Business Machines Corporation Integrated multichip memory module structure
FR2719967B1 (fr) * 1994-05-10 1996-06-07 Thomson Csf Interconnexion en trois dimensions de boîtiers de composants électroniques utilisant des circuits imprimés.
KR100253352B1 (ko) * 1997-11-19 2000-04-15 김영환 적층가능한 반도체 칩 및 적층된 반도체 칩 모듈의 제조 방법
JP2000243900A (ja) * 1999-02-23 2000-09-08 Rohm Co Ltd 半導体チップおよびそれを用いた半導体装置、ならびに半導体チップの製造方法
KR100333385B1 (ko) * 1999-06-29 2002-04-18 박종섭 웨이퍼 레벨 스택 패키지 및 그의 제조 방법
FR2802706B1 (fr) * 1999-12-15 2002-03-01 3D Plus Sa Procede et dispositif d'interconnexion en trois dimensions de composants electroniques
FR2805082B1 (fr) * 2000-02-11 2003-01-31 3D Plus Sa Procede d'interconnexion en trois dimensions et dispositif electronique obtenu par ce procede
FR2812453B1 (fr) * 2000-07-25 2004-08-20 3D Plus Sa Procede de blindage et/ou de decouplage repartis pour un dispositif electronique a interconnexion en trois dimensions , dispositif ainsi obtenu et procede d'obtention de celui- ci
JP4361670B2 (ja) * 2000-08-02 2009-11-11 富士通マイクロエレクトロニクス株式会社 半導体素子積層体、半導体素子積層体の製造方法、及び半導体装置
JP3420748B2 (ja) * 2000-12-14 2003-06-30 松下電器産業株式会社 半導体装置及びその製造方法
JP4191908B2 (ja) * 2001-04-18 2008-12-03 株式会社東芝 積層型半導体装置
FR2832136B1 (fr) * 2001-11-09 2005-02-18 3D Plus Sa Dispositif d'encapsulation hermetique de composant devant etre protege de toute contrainte
JP4154478B2 (ja) * 2002-02-20 2008-09-24 独立行政法人産業技術総合研究所 感光性ポリイミドを用いた貫通電極形成方法
AU2003217142A1 (en) * 2002-02-26 2003-09-09 Gautham Viswanadam Integrated circuit device and method of manufacturing thereof
SG119185A1 (en) * 2003-05-06 2006-02-28 Micron Technology Inc Method for packaging circuits and packaged circuits
JP2004342861A (ja) * 2003-05-16 2004-12-02 Sony Corp チップ状電子部品及び擬似ウェーハ、これらの製造方法、並びに電子部品の実装構造
FR2857157B1 (fr) * 2003-07-01 2005-09-23 3D Plus Sa Procede d'interconnexion de composants actif et passif et composant heterogene a faible epaisseur en resultant
FR2875672B1 (fr) * 2004-09-21 2007-05-11 3D Plus Sa Sa Dispositif electronique avec repartiteur de chaleur integre

Also Published As

Publication number Publication date
FR2895568B1 (fr) 2008-02-08
WO2007071696A1 (fr) 2007-06-28
US7877874B2 (en) 2011-02-01
EP1966825B1 (de) 2009-10-21
FR2895568A1 (fr) 2007-06-29
EP1966825A1 (de) 2008-09-10
JP2009521116A (ja) 2009-05-28
US20080289174A1 (en) 2008-11-27
JP5211396B2 (ja) 2013-06-12

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