DE602007011105D1 - Konfigurierbarer cache für einen mikroprozessor - Google Patents

Konfigurierbarer cache für einen mikroprozessor

Info

Publication number
DE602007011105D1
DE602007011105D1 DE602007011105T DE602007011105T DE602007011105D1 DE 602007011105 D1 DE602007011105 D1 DE 602007011105D1 DE 602007011105 T DE602007011105 T DE 602007011105T DE 602007011105 T DE602007011105 T DE 602007011105T DE 602007011105 D1 DE602007011105 D1 DE 602007011105D1
Authority
DE
Germany
Prior art keywords
cache
bit field
memory
coupled
address tag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007011105T
Other languages
English (en)
Inventor
Rodney J Pesavento
Gregg D Lahti
Joseph W Triece
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
Microchip Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Publication of DE602007011105D1 publication Critical patent/DE602007011105D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
DE602007011105T 2006-12-15 2007-12-12 Konfigurierbarer cache für einen mikroprozessor Active DE602007011105D1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US87018806P 2006-12-15 2006-12-15
US87062206P 2006-12-19 2006-12-19
US11/928,479 US7877537B2 (en) 2006-12-15 2007-10-30 Configurable cache for a microprocessor
PCT/US2007/087249 WO2008073974A1 (en) 2006-12-15 2007-12-12 Configurable cache for a microprocessor

Publications (1)

Publication Number Publication Date
DE602007011105D1 true DE602007011105D1 (de) 2011-01-20

Family

ID=39145114

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007011105T Active DE602007011105D1 (de) 2006-12-15 2007-12-12 Konfigurierbarer cache für einen mikroprozessor

Country Status (7)

Country Link
US (1) US7877537B2 (de)
EP (1) EP2092429B1 (de)
KR (1) KR101441019B1 (de)
AT (1) ATE491181T1 (de)
DE (1) DE602007011105D1 (de)
TW (1) TWI431472B (de)
WO (1) WO2008073974A1 (de)

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US7966457B2 (en) * 2006-12-15 2011-06-21 Microchip Technology Incorporated Configurable cache for a microprocessor
US9208095B2 (en) 2006-12-15 2015-12-08 Microchip Technology Incorporated Configurable cache for a microprocessor
US8543769B2 (en) * 2009-07-27 2013-09-24 International Business Machines Corporation Fine grained cache allocation
US8745618B2 (en) * 2009-08-25 2014-06-03 International Business Machines Corporation Cache partitioning with a partition table to effect allocation of ways and rows of the cache to virtual machine in virtualized environments
US20120324195A1 (en) * 2011-06-14 2012-12-20 Alexander Rabinovitch Allocation of preset cache lines
US8700864B2 (en) * 2011-11-11 2014-04-15 Microsoft Corporation Self-disabling working set cache
US8966185B2 (en) * 2012-06-14 2015-02-24 International Business Machines Corporation Cache memory prefetching
CN103019959B (zh) * 2012-11-21 2016-05-04 中国科学院声学研究所 一种指令高速缓冲存储器
US20150006815A1 (en) * 2013-06-28 2015-01-01 Lsi Corporation Backup of cached dirty data during power outages
US9405690B2 (en) * 2013-08-07 2016-08-02 Oracle International Corporation Method for storing modified instruction data in a shared cache
KR102074329B1 (ko) * 2013-09-06 2020-02-06 삼성전자주식회사 데이터 저장 장치 및 그것의 데이터 처리 방법
US9507527B2 (en) 2014-02-21 2016-11-29 International Business Machines Corporation Efficient cache management of multi-target peer-to-peer remote copy (PPRC) modified sectors bitmap
KR20180012565A (ko) 2016-07-27 2018-02-06 에스케이하이닉스 주식회사 휘발성 메모리를 캐쉬로 사용하는 비휘발성 메모리 시스템
US10613860B2 (en) * 2016-11-09 2020-04-07 Arm Limited Computer architecture
CN112685335B (zh) * 2020-12-28 2022-07-15 湖南博匠信息科技有限公司 数据存储系统
US11861190B2 (en) * 2021-04-08 2024-01-02 Marvell Asia Pte, Ltd. Memory allocation and reallocation for memory access instructions and data using intermediate processor

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US7966457B2 (en) 2006-12-15 2011-06-21 Microchip Technology Incorporated Configurable cache for a microprocessor

Also Published As

Publication number Publication date
ATE491181T1 (de) 2010-12-15
EP2092429B1 (de) 2010-12-08
KR20090096722A (ko) 2009-09-14
WO2008073974A1 (en) 2008-06-19
US7877537B2 (en) 2011-01-25
TWI431472B (zh) 2014-03-21
TW200834306A (en) 2008-08-16
US20080147990A1 (en) 2008-06-19
KR101441019B1 (ko) 2014-09-17
EP2092429A1 (de) 2009-08-26

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