DE60217120D1 - Zellenanordnung mit Bipolar-Auswahl-Transistor und Herstellungsverfahren - Google Patents

Zellenanordnung mit Bipolar-Auswahl-Transistor und Herstellungsverfahren

Info

Publication number
DE60217120D1
DE60217120D1 DE60217120T DE60217120T DE60217120D1 DE 60217120 D1 DE60217120 D1 DE 60217120D1 DE 60217120 T DE60217120 T DE 60217120T DE 60217120 T DE60217120 T DE 60217120T DE 60217120 D1 DE60217120 D1 DE 60217120D1
Authority
DE
Germany
Prior art keywords
manufacturing
selection transistor
cell arrangement
bipolar selection
bipolar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60217120T
Other languages
English (en)
Other versions
DE60217120T2 (de
Inventor
Fabio Pellizzer
Giulio Casagrande
Roberto Bez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Ovonyx Inc
Original Assignee
STMicroelectronics SRL
Ovonyx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL, Ovonyx Inc filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE60217120D1 publication Critical patent/DE60217120D1/de
Publication of DE60217120T2 publication Critical patent/DE60217120T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/32—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the bipolar type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/685—Hi-Lo semiconductor devices, e.g. memory devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
DE60217120T 2002-10-08 2002-10-08 Zellenanordnung mit einem darin enthaltenen Auswähl-Bipolartransistor sowie Verfahren zum Herstellen derselben Expired - Lifetime DE60217120T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02425605A EP1408550B1 (de) 2002-10-08 2002-10-08 Zellenanordnung mit Bipolar-Auswahl-Transistor und Herstellungsverfahren

Publications (2)

Publication Number Publication Date
DE60217120D1 true DE60217120D1 (de) 2007-02-08
DE60217120T2 DE60217120T2 (de) 2007-10-25

Family

ID=32011065

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60217120T Expired - Lifetime DE60217120T2 (de) 2002-10-08 2002-10-08 Zellenanordnung mit einem darin enthaltenen Auswähl-Bipolartransistor sowie Verfahren zum Herstellen derselben

Country Status (3)

Country Link
US (2) US7135756B2 (de)
EP (1) EP1408550B1 (de)
DE (1) DE60217120T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1408549B1 (de) * 2002-10-08 2007-03-07 STMicroelectronics S.r.l. Herstellungsverfahren für Zellenanordnung mit bipolaren Auswahltransistoren und zugehörige Zellenanordnung
US6804137B1 (en) * 2003-06-12 2004-10-12 Hewlett-Packard Development Company, L.P. Data storage medium having layers acting as transistor
US7875513B2 (en) * 2006-04-26 2011-01-25 Fabio Pellizzer Self-aligned bipolar junction transistors
US7767994B2 (en) * 2006-12-05 2010-08-03 Electronics And Telecommunications Research Institute Phase-change random access memory device and method of manufacturing the same
KR100825767B1 (ko) * 2006-12-05 2008-04-29 한국전자통신연구원 상변화 메모리 소자 및 그의 제조 방법
EP1965427A1 (de) 2007-02-28 2008-09-03 STMicroelectronics S.r.l. Matrix vertikaler Bipolartransistoren, insbesondere Auswahlschalter in einer Phasenwechsel-Speichervorrichtung
KR100929633B1 (ko) * 2007-05-11 2009-12-03 주식회사 하이닉스반도체 상변화 기억 소자
US7663134B2 (en) * 2007-07-10 2010-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Memory array with a selector connected to multiple resistive cells
US7550313B2 (en) * 2007-07-21 2009-06-23 International Business Machines Corporation Method for delineation of phase change memory (PCM) cells separated by PCM and upper electrode regions modified to have high film resistivity
US20090225580A1 (en) * 2008-03-07 2009-09-10 Peng-Fei Wang Integrated Circuit, Memory Module, and Method of Manufacturing an Integrated Circuit
KR101490429B1 (ko) * 2008-03-11 2015-02-11 삼성전자주식회사 저항 메모리 소자 및 그 형성 방법
IT1391861B1 (it) 2008-09-10 2012-01-27 St Microelectronics Rousset Processo per la realizzazione di un dispositivo di memoria includente un transistore verticale bipolare a giunzione ed un transistore cmos con spaziatori
US7869267B2 (en) * 2008-12-29 2011-01-11 Numonyx B.V. Method for low power accessing a phase change memory device
US9525007B2 (en) 2010-12-28 2016-12-20 Micron Technology, Inc. Phase change memory device with voltage control elements
US9520554B2 (en) 2013-03-04 2016-12-13 Micron Technology, Inc. Clamp elements for phase change memory arrays

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4180866A (en) * 1977-08-01 1979-12-25 Burroughs Corporation Single transistor memory cell employing an amorphous semiconductor threshold device
US4981807A (en) * 1988-10-31 1991-01-01 International Business Machines Corporation Process for fabricating complementary vertical transistor memory cell
KR940001425B1 (ko) * 1990-11-06 1994-02-23 재단법인 한국전자통신연구소 수직구조를 갖는 바이폴라형 다이내믹 램을 제조하는 방법 및 그 다이내믹 램의 구조
US5276638A (en) * 1991-07-31 1994-01-04 International Business Machines Corporation Bipolar memory cell with isolated PNP load
US5789758A (en) 1995-06-07 1998-08-04 Micron Technology, Inc. Chalcogenide memory cell with a plurality of chalcogenide electrodes
US6043527A (en) * 1998-04-14 2000-03-28 Micron Technology, Inc. Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
JP2001035926A (ja) 1999-07-19 2001-02-09 Nec Corp 半導体装置及びその製造方法
US6649928B2 (en) 2000-12-13 2003-11-18 Intel Corporation Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby
US6437383B1 (en) * 2000-12-21 2002-08-20 Intel Corporation Dual trench isolation for a phase-change memory cell and method of making same
US6534781B2 (en) * 2000-12-26 2003-03-18 Ovonyx, Inc. Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact
US6531373B2 (en) 2000-12-27 2003-03-11 Ovonyx, Inc. Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements
JP3869682B2 (ja) 2001-06-12 2007-01-17 株式会社ルネサステクノロジ 半導体装置
US6838723B2 (en) 2002-08-29 2005-01-04 Micron Technology, Inc. Merged MOS-bipolar capacitor memory cell
EP1408549B1 (de) 2002-10-08 2007-03-07 STMicroelectronics S.r.l. Herstellungsverfahren für Zellenanordnung mit bipolaren Auswahltransistoren und zugehörige Zellenanordnung

Also Published As

Publication number Publication date
US7135756B2 (en) 2006-11-14
EP1408550A1 (de) 2004-04-14
US20040150093A1 (en) 2004-08-05
US20070099347A1 (en) 2007-05-03
EP1408550B1 (de) 2006-12-27
US7446011B2 (en) 2008-11-04
DE60217120T2 (de) 2007-10-25

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