DE60221406D1 - Mehrprozessor-infrastruktur zur bereitstellung einer flexiblen bandweitenzuteilung über mehrere instanziierungen separater datenbusse, steuerbusse und unterstützungsmechanismen - Google Patents

Mehrprozessor-infrastruktur zur bereitstellung einer flexiblen bandweitenzuteilung über mehrere instanziierungen separater datenbusse, steuerbusse und unterstützungsmechanismen

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Publication number
DE60221406D1
DE60221406D1 DE60221406T DE60221406T DE60221406D1 DE 60221406 D1 DE60221406 D1 DE 60221406D1 DE 60221406 T DE60221406 T DE 60221406T DE 60221406 T DE60221406 T DE 60221406T DE 60221406 D1 DE60221406 D1 DE 60221406D1
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Germany
Prior art keywords
bus
buses
push
command
target
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Expired - Lifetime
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DE60221406T
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DE60221406T2 (de
Inventor
Mark Rosenbluth
Gilbert Wolrich
Debra Bernstein
Myles Wilde
Matthew Adiletta
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Intel Corp
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Intel Corp
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Publication of DE60221406D1 publication Critical patent/DE60221406D1/de
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Publication of DE60221406T2 publication Critical patent/DE60221406T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
DE60221406T 2001-08-27 2002-08-27 Mehrprozessor-infrastruktur zur bereitstellung einer flexiblen bandweitenzuteilung über mehrere instanziierungen separater datenbusse, steuerbusse und unterstützungsmechanismen Expired - Lifetime DE60221406T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US212944 1980-12-04
US31514401P 2001-08-27 2001-08-27
US315144P 2001-08-27
US10/212,944 US7225281B2 (en) 2001-08-27 2002-08-05 Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
PCT/US2002/027430 WO2003019399A1 (en) 2001-08-27 2002-08-27 A multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms

Publications (2)

Publication Number Publication Date
DE60221406D1 true DE60221406D1 (de) 2007-09-06
DE60221406T2 DE60221406T2 (de) 2008-04-17

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Application Number Title Priority Date Filing Date
DE60221406T Expired - Lifetime DE60221406T2 (de) 2001-08-27 2002-08-27 Mehrprozessor-infrastruktur zur bereitstellung einer flexiblen bandweitenzuteilung über mehrere instanziierungen separater datenbusse, steuerbusse und unterstützungsmechanismen

Country Status (8)

Country Link
US (1) US7225281B2 (de)
EP (1) EP1421504B1 (de)
AT (1) ATE368259T1 (de)
AU (1) AU2002339857A1 (de)
CA (1) CA2458572C (de)
DE (1) DE60221406T2 (de)
TW (1) TWI249674B (de)
WO (1) WO2003019399A1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7681018B2 (en) 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US7216204B2 (en) * 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US6868476B2 (en) * 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US7487505B2 (en) * 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US7610451B2 (en) * 2002-01-25 2009-10-27 Intel Corporation Data transfer mechanism using unidirectional pull bus and push bus
US7337275B2 (en) * 2002-08-13 2008-02-26 Intel Corporation Free list and ring data structure management
US6941438B2 (en) * 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
KR100555501B1 (ko) * 2003-06-26 2006-03-03 삼성전자주식회사 동적으로 버스 점유 우선 순위를 정하는 버스 중재기 및그 버스 중재 방법
US20050198361A1 (en) * 2003-12-29 2005-09-08 Chandra Prashant R. Method and apparatus for meeting a given content throughput using at least one memory channel
US20060067348A1 (en) * 2004-09-30 2006-03-30 Sanjeev Jain System and method for efficient memory access of queue control data structures
US7401184B2 (en) 2004-11-19 2008-07-15 Intel Corporation Matching memory transactions to cache line boundaries
US7555630B2 (en) * 2004-12-21 2009-06-30 Intel Corporation Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit
US20060140203A1 (en) * 2004-12-28 2006-06-29 Sanjeev Jain System and method for packet queuing
CN100365602C (zh) * 2004-12-31 2008-01-30 北京中星微电子有限公司 实现多个主动装置对单一总线上从动装置进行存取的设备
US7283418B2 (en) * 2005-07-26 2007-10-16 Micron Technology, Inc. Memory device and method having multiple address, data and command buses
JP2007122410A (ja) * 2005-10-28 2007-05-17 Nec Electronics Corp バス調停回路及びバス調停方法
US20070157030A1 (en) * 2005-12-30 2007-07-05 Feghali Wajdi K Cryptographic system component
US8185680B2 (en) * 2006-02-06 2012-05-22 Standard Microsystems Corporation Method for changing ownership of a bus between master/slave devices
JP5057833B2 (ja) * 2007-04-24 2012-10-24 株式会社日立製作所 転送システム、イニシエータデバイス及びデータ転送方法
US7774529B2 (en) * 2007-07-03 2010-08-10 Panasonic Corporation Bus communication apparatus that uses shared memory
US8055719B2 (en) * 2008-07-16 2011-11-08 International Business Machines Corporation Performance and reduce network traffic for remote hardware data scan operations
DE102009001898A1 (de) 2009-03-26 2010-09-30 Robert Bosch Gmbh Schaltungsanordnungen und Verfahren zur Steuerung eines Datenaustauschs in einer Schaltungsanordnung
KR20120037785A (ko) * 2010-10-12 2012-04-20 삼성전자주식회사 부하 균형을 유지하는 시스템 온 칩 및 그것의 부하 균형 유지 방법

Family Cites Families (172)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US388173A (en) * 1888-08-21 Eobeet b
US3373408A (en) 1965-04-16 1968-03-12 Rca Corp Computer capable of switching between programs without storage and retrieval of the contents of operation registers
US3478322A (en) 1967-05-23 1969-11-11 Ibm Data processor employing electronically changeable control storage
BE795789A (fr) 1972-03-08 1973-06-18 Burroughs Corp Microprogramme comportant une micro-instruction de recouvrement
US3881173A (en) 1973-05-14 1975-04-29 Amdahl Corp Condition code determination and data processing
IT986411B (it) 1973-06-05 1975-01-30 Olivetti E C Spa Sistema per trasferire il control lo delle elaborazioni da un primo livello prioritario ad un secondo livello prioritario
FR2253415A5 (de) * 1973-12-04 1975-06-27 Cii
US3913074A (en) 1973-12-18 1975-10-14 Honeywell Inf Systems Search processing apparatus
US4045782A (en) * 1976-03-29 1977-08-30 The Warner & Swasey Company Microprogrammed processor system having external memory
US4130890A (en) 1977-06-08 1978-12-19 Itt Industries, Inc. Integrated DDC memory with bitwise erase
US4392758A (en) * 1978-05-22 1983-07-12 International Business Machines Corporation Underscore erase
US4189767A (en) 1978-06-05 1980-02-19 Bell Telephone Laboratories, Incorporated Accessing arrangement for interleaved modular memories
JPS56164464A (en) 1980-05-21 1981-12-17 Tatsuo Nogi Parallel processing computer
US4400770A (en) 1980-11-10 1983-08-23 International Business Machines Corporation Cache synonym detection and handling means
CA1179069A (en) 1981-04-10 1984-12-04 Yasushi Fukunaga Data transmission apparatus for a multiprocessor system
US4569016A (en) * 1983-06-30 1986-02-04 International Business Machines Corporation Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system
US4868735A (en) * 1984-05-08 1989-09-19 Advanced Micro Devices, Inc. Interruptible structured microprogrammed sixteen-bit address sequence controller
US4742451A (en) * 1984-05-21 1988-05-03 Digital Equipment Corporation Instruction prefetch system for conditional branch instruction for central processor unit
US4777587A (en) 1985-08-30 1988-10-11 Advanced Micro Devices, Inc. System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses
JPS62103893A (ja) 1985-10-30 1987-05-14 Toshiba Corp 半導体メモリ及び半導体メモリシステム
US5021945A (en) * 1985-10-31 1991-06-04 Mcc Development, Ltd. Parallel processor system for processing natural concurrencies and method therefor
US4745544A (en) 1985-12-12 1988-05-17 Texas Instruments Incorporated Master/slave sequencing processor with forced I/O
US4724521A (en) * 1986-01-14 1988-02-09 Veri-Fone, Inc. Method for operating a local terminal to execute a downloaded application program
US5297260A (en) 1986-03-12 1994-03-22 Hitachi, Ltd. Processor having a plurality of CPUS with one CPU being normally connected to common bus
US4992934A (en) * 1986-12-15 1991-02-12 United Technologies Corporation Reduced instruction set computing apparatus and methods
US5073864A (en) 1987-02-10 1991-12-17 Davin Computer Corporation Parallel string processor and method for a minicomputer
US4866664A (en) 1987-03-09 1989-09-12 Unisys Corporation Intercomputer communication control apparatus & method
US5142683A (en) 1987-03-09 1992-08-25 Unisys Corporation Intercomputer communication control apparatus and method
DE68913629T2 (de) 1988-03-14 1994-06-16 Unisys Corp Satzverriegelungsprozessor für vielfachverarbeitungsdatensystem.
US5008808A (en) * 1988-06-23 1991-04-16 Storage Technology Corporation Consolidation of commands in a buffered input/output device
US5165025A (en) 1988-10-06 1992-11-17 Lass Stanley E Interlacing the paths after a conditional branch like instruction
US5142676A (en) * 1988-12-28 1992-08-25 Gte Laboratories Incorporated Separate content addressable memories for storing locked segment addresses and locking processor identifications for controlling access to shared memory
US5155854A (en) 1989-02-03 1992-10-13 Digital Equipment Corporation System for arbitrating communication requests using multi-pass control unit based on availability of system resources
US5155831A (en) 1989-04-24 1992-10-13 International Business Machines Corporation Data processing system with fast queue store interposed between store-through caches and a main memory
US5166872A (en) 1989-07-17 1992-11-24 Ability Technologies Corporation System and method for controlling devices through communication processors and pluralities of address-associated device controllers sharing each communication processor
US5113516A (en) * 1989-07-31 1992-05-12 North American Philips Corporation Data repacker having controlled feedback shifters and registers for changing data format
US5168555A (en) 1989-09-06 1992-12-01 Unisys Corporation Initial program load control
US5263169A (en) 1989-11-03 1993-11-16 Zoran Corporation Bus arbitration and resource management for concurrent vector signal processor architecture
DE3942977A1 (de) 1989-12-23 1991-06-27 Standard Elektrik Lorenz Ag Verfahren zum wiederherstellen der richtigen zellfolge, insbesondere in einer atm-vermittlungsstelle, sowie ausgangseinheit hierfuer
US5247671A (en) * 1990-02-14 1993-09-21 International Business Machines Corporation Scalable schedules for serial communications controller in data processing systems
JPH0799812B2 (ja) * 1990-03-26 1995-10-25 株式会社グラフイックス・コミュニケーション・テクノロジーズ 信号符号化装置および信号復号化装置、並びに信号符号化復号化装置
EP0449369B1 (de) 1990-03-27 1998-07-29 Koninklijke Philips Electronics N.V. Datenverarbeitungssystem mit einem leistungsverbessernden Befehlscachespeicher
US5390329A (en) 1990-06-11 1995-02-14 Cray Research, Inc. Responding to service requests using minimal system-side context in a multiprocessor environment
CA2045790A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites Branch prediction in high-performance processor
US5347648A (en) 1990-06-29 1994-09-13 Digital Equipment Corporation Ensuring write ordering under writeback cache error conditions
US5404482A (en) 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills
US5432918A (en) 1990-06-29 1995-07-11 Digital Equipment Corporation Method and apparatus for ordering read and write operations using conflict bits in a write queue
US5367678A (en) 1990-12-06 1994-11-22 The Regents Of The University Of California Multiprocessor system having statically determining resource allocation schedule at compile time and the using of static schedule with processor signals to control the execution time dynamically
EP0522513A2 (de) * 1991-07-09 1993-01-13 Hughes Aircraft Company Hochgeschwindigkeitsparallelmicrokodeprogrammsteuerung
US5255239A (en) 1991-08-13 1993-10-19 Cypress Semiconductor Corporation Bidirectional first-in-first-out memory device with transparent and user-testable capabilities
US5623489A (en) 1991-09-26 1997-04-22 Ipc Information Systems, Inc. Channel allocation system for distributed digital switching network
US5392412A (en) 1991-10-03 1995-02-21 Standard Microsystems Corporation Data communication controller for use with a single-port data packet buffer
GB2260429B (en) 1991-10-11 1995-05-24 Intel Corp Versatile cache memory
US5392391A (en) 1991-10-18 1995-02-21 Lsi Logic Corporation High performance graphics applications controller
DE69231957T2 (de) 1991-10-21 2002-04-04 Toshiba Kawasaki Kk Hochgeschwindigkeitsprozessor zum fähiger Abhandeln mehrerer Unterbrechungen
US5452437A (en) 1991-11-18 1995-09-19 Motorola, Inc. Methods of debugging multiprocessor system
US5357617A (en) 1991-11-22 1994-10-18 International Business Machines Corporation Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
US5442797A (en) 1991-12-04 1995-08-15 Casavant; Thomas L. Latency tolerant risc-based multiple processor with event driven locality managers resulting from variable tagging
JP2823767B2 (ja) 1992-02-03 1998-11-11 松下電器産業株式会社 レジスタファイル
US5459842A (en) 1992-06-26 1995-10-17 International Business Machines Corporation System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory
DE4223600C2 (de) 1992-07-17 1994-10-13 Ibm Mehrprozessor-Computersystem und Verfahren zum Übertragen von Steuerinformationen und Dateninformation zwischen wenigstens zwei Prozessoreinheiten eines Computersystems
US5274770A (en) 1992-07-29 1993-12-28 Tritech Microelectronics International Pte Ltd. Flexible register-based I/O microcontroller with single cycle instruction execution
US5442756A (en) * 1992-07-31 1995-08-15 Intel Corporation Branch prediction and resolution apparatus for a superscalar computer processor
US5692167A (en) 1992-07-31 1997-11-25 Intel Corporation Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor
US5649109A (en) * 1992-10-22 1997-07-15 Digital Equipment Corporation Apparatus and method for maintaining forwarding information in a bridge or router using multiple free queues having associated free space sizes
US5481683A (en) * 1992-10-30 1996-01-02 International Business Machines Corporation Super scalar computer architecture using remand and recycled general purpose register to manage out-of-order execution of instructions
US5450603A (en) * 1992-12-18 1995-09-12 Xerox Corporation SIMD architecture with transfer register or value source circuitry connected to bus
KR100313261B1 (ko) 1992-12-23 2002-02-28 앙드래베이너,조엘브르리아드 저전력형다중작업제어기(명칭정정)
US5404464A (en) 1993-02-11 1995-04-04 Ast Research, Inc. Bus control system and method that selectively generate an early address strobe
US5448702A (en) 1993-03-02 1995-09-05 International Business Machines Corporation Adapters with descriptor queue management capability
US5522069A (en) 1993-04-30 1996-05-28 Zenith Data Systems Corporation Symmetric multiprocessing system with unified environment and distributed system functions
WO1994027216A1 (en) 1993-05-14 1994-11-24 Massachusetts Institute Of Technology Multiprocessor coupling system with integrated compile and run time scheduling for parallelism
CA2122182A1 (en) 1993-05-20 1994-11-21 Rene Leblanc Method for rapid prototyping of programming problems
US5363448A (en) 1993-06-30 1994-11-08 United Technologies Automotive, Inc. Pseudorandom number generation and cryptographic authentication
CA2107299C (en) 1993-09-29 1997-02-25 Mehrad Yasrebi High performance machine for switched communications in a heterogenous data processing network gateway
US5446736A (en) 1993-10-07 1995-08-29 Ast Research, Inc. Method and apparatus for connecting a node to a wireless network using a standard protocol
US5450351A (en) 1993-11-19 1995-09-12 International Business Machines Corporation Content addressable memory implementation with random access memory
US6079014A (en) * 1993-12-02 2000-06-20 Intel Corporation Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state
US5487159A (en) * 1993-12-23 1996-01-23 Unisys Corporation System for processing shift, mask, and merge operations in one instruction
EP0661625B1 (de) * 1994-01-03 1999-09-08 Intel Corporation Verfahren und Vorrichtung zum Implementieren eines vierstufigen Verzweigungsauflosungssystem in einem Rechnerprozessor
US5490204A (en) 1994-03-01 1996-02-06 Safco Corporation Automated quality assessment system for cellular networks
US5659722A (en) * 1994-04-28 1997-08-19 International Business Machines Corporation Multiple condition code branching system in a multi-processor environment
US5542088A (en) 1994-04-29 1996-07-30 Intergraph Corporation Method and apparatus for enabling control of task execution
US5721870A (en) 1994-05-25 1998-02-24 Nec Corporation Lock control for a shared main storage data processing system
US5544236A (en) 1994-06-10 1996-08-06 At&T Corp. Access to unsubscribed features
US5574922A (en) 1994-06-17 1996-11-12 Apple Computer, Inc. Processor with sequences of processor instructions for locked memory updates
FR2722041B1 (fr) * 1994-06-30 1998-01-02 Samsung Electronics Co Ltd Decodeur de huffman
US5666551A (en) * 1994-06-30 1997-09-09 Digital Equipment Corporation Distributed data bus sequencing for a system bus with separate address and data bus protocols
US5640538A (en) * 1994-08-22 1997-06-17 Adaptec, Inc. Programmable timing mark sequencer for a disk drive
US5813031A (en) * 1994-09-21 1998-09-22 Industrial Technology Research Institute Caching tag for a large scale cache computer memory system
US5717760A (en) * 1994-11-09 1998-02-10 Channel One Communications, Inc. Message protection system and method
US5610864A (en) * 1994-12-23 1997-03-11 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US5550816A (en) 1994-12-29 1996-08-27 Storage Technology Corporation Method and apparatus for virtual switching
US5649157A (en) 1995-03-30 1997-07-15 Hewlett-Packard Co. Memory controller with priority queues
TW360852B (en) * 1995-04-12 1999-06-11 Matsushita Electric Ind Co Ltd Pipeline processor
US5592622A (en) 1995-05-10 1997-01-07 3Com Corporation Network intermediate system with message passing architecture
US5812799A (en) * 1995-06-07 1998-09-22 Microunity Systems Engineering, Inc. Non-blocking load buffer and a multiple-priority memory system for real-time multiprocessing
US5541920A (en) * 1995-06-15 1996-07-30 Bay Networks, Inc. Method and apparatus for a delayed replace mechanism for a streaming packet modification engine
KR0180169B1 (ko) * 1995-06-30 1999-05-01 배순훈 가변길이 부호기
US5613071A (en) * 1995-07-14 1997-03-18 Intel Corporation Method and apparatus for providing remote memory access in a distributed memory multiprocessor system
US5680641A (en) 1995-08-16 1997-10-21 Sharp Microelectronics Technology, Inc. Multiple register bank system for concurrent I/O operation in a CPU datapath
US5689566A (en) 1995-10-24 1997-11-18 Nguyen; Minhtam C. Network with secure communications sessions
KR0150072B1 (ko) 1995-11-30 1998-10-15 양승택 병렬처리 컴퓨터 시스템에서의 메모리 데이타 경로 제어장치
US5699537A (en) 1995-12-22 1997-12-16 Intel Corporation Processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions
US5790813A (en) * 1996-01-05 1998-08-04 Unisys Corporation Pre-arbitration system allowing look-around and bypass for significant operations
US5978874A (en) * 1996-07-01 1999-11-02 Sun Microsystems, Inc. Implementing snooping on a split-transaction computer system bus
US5829033A (en) * 1996-07-01 1998-10-27 Sun Microsystems, Inc. Optimizing responses in a coherent distributed electronic system including a computer system
US5933627A (en) * 1996-07-01 1999-08-03 Sun Microsystems Thread switch on blocked load or store using instruction thread field
US6058465A (en) * 1996-08-19 2000-05-02 Nguyen; Le Trong Single-instruction-multiple-data processing in a multimedia signal processor
US6173349B1 (en) * 1996-10-18 2001-01-09 Samsung Electronics Co., Ltd. Shared bus system with transaction and destination ID
US6029228A (en) * 1996-12-31 2000-02-22 Texas Instruments Incorporated Data prefetching of a load target buffer for post-branch instructions based on past prediction accuracy's of branch predictions
EP0898819B1 (de) * 1997-01-10 2004-08-04 Koninklijke Philips Electronics N.V. Kommunikationsbussystem
US5893162A (en) * 1997-02-05 1999-04-06 Transwitch Corp. Method and apparatus for allocation and management of shared memory with data in memory stored as multiple linked lists
US5742587A (en) 1997-02-28 1998-04-21 Lanart Corporation Load balancing port switching hub
US5941949A (en) * 1997-05-14 1999-08-24 Citrix Systems, Inc. System and method for transmitting data from a server application to more than one client node
US6047334A (en) * 1997-06-17 2000-04-04 Intel Corporation System for delaying dequeue of commands received prior to fence command until commands received before fence command are ordered for execution in a fixed sequence
US6233599B1 (en) * 1997-07-10 2001-05-15 International Business Machines Corporation Apparatus and method for retrofitting multi-threaded operations on a computer by partitioning and overlapping registers
US6104700A (en) * 1997-08-29 2000-08-15 Extreme Networks Policy based quality of service
US6223277B1 (en) * 1997-11-21 2001-04-24 Texas Instruments Incorporated Data processing circuit with packed data structure capability
US6029170A (en) * 1997-11-25 2000-02-22 International Business Machines Corporation Hybrid tree array data structure and method
US6212602B1 (en) * 1997-12-17 2001-04-03 Sun Microsystems, Inc. Cache tag caching
US6230119B1 (en) * 1998-02-06 2001-05-08 Patrick Michael Mitchell Integrated circuit with embedded emulator and emulation system for use with such an integrated circuit
US6092175A (en) * 1998-04-02 2000-07-18 University Of Washington Shared register storage mechanisms for multithreaded computer systems with out-of-order execution
US6724767B1 (en) * 1998-06-27 2004-04-20 Intel Corporation Two-dimensional queuing/de-queuing methods and systems for implementing the same
US6505229B1 (en) * 1998-09-25 2003-01-07 Intelect Communications, Inc. Method for allowing multiple processing threads and tasks to execute on one or more processor units for embedded real-time processor systems
US6449289B1 (en) * 1998-10-09 2002-09-10 Adaptec, Inc. Multi-processor bus protocol system
US6247086B1 (en) * 1998-11-12 2001-06-12 Adaptec, Inc. PCI bridge for optimized command delivery
US6182183B1 (en) * 1998-11-13 2001-01-30 Sonics, Inc. Communications system and method with multilevel connection identification
US6230261B1 (en) * 1998-12-02 2001-05-08 I. P. First, L.L.C. Method and apparatus for predicting conditional branch instruction outcome based on branch condition test type
GB2344665B (en) * 1998-12-08 2003-07-30 Advanced Risc Mach Ltd Cache memory
US6378124B1 (en) * 1999-02-22 2002-04-23 International Business Machines Corporation Debugger thread synchronization control points
US6570877B1 (en) * 1999-04-07 2003-05-27 Cisco Technology, Inc. Search engine for forwarding table content addressable memory
US6401149B1 (en) * 1999-05-05 2002-06-04 Qlogic Corporation Methods for context switching within a disk controller
US6351808B1 (en) * 1999-05-11 2002-02-26 Sun Microsystems, Inc. Vertically and horizontally threaded processor with multidimensional storage for storing thread data
US6457078B1 (en) * 1999-06-17 2002-09-24 Advanced Micro Devices, Inc. Multi-purpose bi-directional control bus for carrying tokens between initiator devices and target devices
US6490642B1 (en) * 1999-08-12 2002-12-03 Mips Technologies, Inc. Locked read/write on separate address/data bus using write barrier
US6539439B1 (en) * 1999-08-18 2003-03-25 Ati International Srl Method and apparatus for interfacing a bus at an independent rate with input/output devices
US6643726B1 (en) * 1999-08-18 2003-11-04 Ati International Srl Method of manufacture and apparatus of an integrated computing system
US6430646B1 (en) * 1999-08-18 2002-08-06 Ati International Srl Method and apparatus for interfacing a processor with a bus
US6427196B1 (en) * 1999-08-31 2002-07-30 Intel Corporation SRAM controller for parallel processor architecture including address and command queue and arbiter
US6668317B1 (en) * 1999-08-31 2003-12-23 Intel Corporation Microengine for parallel processor architecture
US6606704B1 (en) * 1999-08-31 2003-08-12 Intel Corporation Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
US6529999B1 (en) * 1999-10-27 2003-03-04 Advanced Micro Devices, Inc. Computer system implementing system and method for ordering write operations and maintaining memory coherency
US6523108B1 (en) * 1999-11-23 2003-02-18 Sony Corporation Method of and apparatus for extracting a string of bits from a binary bit string and depositing a string of bits onto a binary bit string
US6823399B2 (en) * 1999-12-06 2004-11-23 Sony Corporation Apparatus control method and transmission device
US6889319B1 (en) * 1999-12-09 2005-05-03 Intel Corporation Method and apparatus for entering and exiting multiple threads within a multithreaded processor
US6357016B1 (en) * 1999-12-09 2002-03-12 Intel Corporation Method and apparatus for disabling a clock signal within a multithreaded processor
US6307789B1 (en) * 1999-12-28 2001-10-23 Intel Corporation Scratchpad memory
US7051329B1 (en) * 1999-12-28 2006-05-23 Intel Corporation Method and apparatus for managing resources in a multithreaded processor
US6625654B1 (en) * 1999-12-28 2003-09-23 Intel Corporation Thread signaling in multi-threaded network processor
US6631430B1 (en) * 1999-12-28 2003-10-07 Intel Corporation Optimizations to receive packet status from fifo bus
US6661794B1 (en) * 1999-12-29 2003-12-09 Intel Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US6631462B1 (en) * 2000-01-05 2003-10-07 Intel Corporation Memory shared between processing threads
US6278289B1 (en) * 2000-05-01 2001-08-21 Xilinx, Inc. Content-addressable memory implemented using programmable logic
KR100716950B1 (ko) * 2000-08-11 2007-05-10 삼성전자주식회사 버스 시스템
US7681018B2 (en) * 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US20020053017A1 (en) * 2000-09-01 2002-05-02 Adiletta Matthew J. Register instructions for a multithreaded processor
US6633938B1 (en) * 2000-10-06 2003-10-14 Broadcom Corporation Independent reset of arbiters and agents to allow for delayed agent reset
US6781992B1 (en) * 2000-11-30 2004-08-24 Netrake Corporation Queue engine for reassembling and reordering data packets in a network
US6847645B1 (en) * 2001-02-22 2005-01-25 Cisco Technology, Inc. Method and apparatus for controlling packet header buffer wrap around in a forwarding engine of an intermediate network node
US6785843B1 (en) * 2001-02-23 2004-08-31 Mcrae Andrew Data plane restart without state change in a control plane of an intermediate network node
TW556077B (en) * 2001-06-05 2003-10-01 Via Tech Inc Controller for improving buffer management efficiency and the buffer management method
JP3489573B2 (ja) * 2001-07-11 2004-01-19 日本電気株式会社 パケット処理装置
US6868476B2 (en) * 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US7487505B2 (en) * 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US7216204B2 (en) * 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US20030065862A1 (en) * 2001-09-28 2003-04-03 Wyland David C. Computer system and method for communications between bus devices
US6934729B2 (en) * 2001-10-18 2005-08-23 International Business Machines Corporation Method and system for performing shift operations
US6738831B2 (en) * 2001-12-12 2004-05-18 Intel Corporation Command ordering
US6754795B2 (en) * 2001-12-21 2004-06-22 Agere Systems Inc. Methods and apparatus for forming linked list queue using chunk-based structure
US7610451B2 (en) * 2002-01-25 2009-10-27 Intel Corporation Data transfer mechanism using unidirectional pull bus and push bus
US6941438B2 (en) * 2003-01-10 2005-09-06 Intel Corporation Memory interleaving

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US7225281B2 (en) 2007-05-29
EP1421504A1 (de) 2004-05-26
AU2002339857A1 (en) 2003-03-10
ATE368259T1 (de) 2007-08-15
WO2003019399A9 (en) 2004-01-29
DE60221406T2 (de) 2008-04-17
CA2458572A1 (en) 2003-03-06
TWI249674B (en) 2006-02-21
WO2003019399A8 (en) 2003-10-02
WO2003019399A1 (en) 2003-03-06
CA2458572C (en) 2010-03-16
EP1421504B1 (de) 2007-07-25
US20030105899A1 (en) 2003-06-05

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