DE60221836D1 - Verfahren und vorrichtung zur optimierten parallelen prüfung und zum zugriff auf elektronische schaltung - Google Patents

Verfahren und vorrichtung zur optimierten parallelen prüfung und zum zugriff auf elektronische schaltung

Info

Publication number
DE60221836D1
DE60221836D1 DE60221836T DE60221836T DE60221836D1 DE 60221836 D1 DE60221836 D1 DE 60221836D1 DE 60221836 T DE60221836 T DE 60221836T DE 60221836 T DE60221836 T DE 60221836T DE 60221836 D1 DE60221836 D1 DE 60221836D1
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DE
Germany
Prior art keywords
test
data
controllers
expected
communications path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60221836T
Other languages
English (en)
Other versions
DE60221836T2 (de
Inventor
Michael Ricchetti
Christopher J Clark
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intellitech Corp
Original Assignee
Intellitech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intellitech Corp filed Critical Intellitech Corp
Application granted granted Critical
Publication of DE60221836D1 publication Critical patent/DE60221836D1/de
Publication of DE60221836T2 publication Critical patent/DE60221836T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C2029/2602—Concurrent test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
DE60221836T 2001-07-05 2002-06-27 Verfahren und vorrichtung zur optimierten parallelen prüfung und zum zugriff auf elektronische schaltung Expired - Lifetime DE60221836T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US30305201P 2001-07-05 2001-07-05
US303052P 2001-07-05
US10/119,060 US6988232B2 (en) 2001-07-05 2002-04-09 Method and apparatus for optimized parallel testing and access of electronic circuits
US119060 2002-04-09
PCT/US2002/020505 WO2003005050A1 (en) 2001-07-05 2002-06-27 Method and apparatus for optimized parallel testing and access of electronic circuits

Publications (2)

Publication Number Publication Date
DE60221836D1 true DE60221836D1 (de) 2007-09-27
DE60221836T2 DE60221836T2 (de) 2008-04-30

Family

ID=26817004

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60221836T Expired - Lifetime DE60221836T2 (de) 2001-07-05 2002-06-27 Verfahren und vorrichtung zur optimierten parallelen prüfung und zum zugriff auf elektronische schaltung

Country Status (11)

Country Link
US (2) US6988232B2 (de)
EP (1) EP1402278B1 (de)
JP (1) JP4083117B2 (de)
KR (1) KR100623310B1 (de)
CN (1) CN100416288C (de)
AT (1) ATE370423T1 (de)
CA (1) CA2421047C (de)
DE (1) DE60221836T2 (de)
HK (1) HK1064444A1 (de)
TW (1) TWI250293B (de)
WO (1) WO2003005050A1 (de)

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CA2421047C (en) 2005-01-25
DE60221836T2 (de) 2008-04-30
US20030009715A1 (en) 2003-01-09
EP1402278B1 (de) 2007-08-15
EP1402278A4 (de) 2005-05-18
WO2003005050A1 (en) 2003-01-16
JP2004522169A (ja) 2004-07-22
ATE370423T1 (de) 2007-09-15
HK1064444A1 (en) 2005-01-28
US7574637B2 (en) 2009-08-11
CA2421047A1 (en) 2003-01-16
JP4083117B2 (ja) 2008-04-30
WO2003005050B1 (en) 2003-03-06
KR100623310B1 (ko) 2006-09-18
EP1402278A1 (de) 2004-03-31
US20060107160A1 (en) 2006-05-18
US6988232B2 (en) 2006-01-17
TWI250293B (en) 2006-03-01
KR20030048024A (ko) 2003-06-18
CN1610834A (zh) 2005-04-27
TW200305027A (en) 2003-10-16
CN100416288C (zh) 2008-09-03

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