DE60228768D1 - Verfahren zur Verarbeitung von Kompletierungspaketen und mit nicht erfolgreichem Kompletierungsstatus - Google Patents

Verfahren zur Verarbeitung von Kompletierungspaketen und mit nicht erfolgreichem Kompletierungsstatus

Info

Publication number
DE60228768D1
DE60228768D1 DE60228768T DE60228768T DE60228768D1 DE 60228768 D1 DE60228768 D1 DE 60228768D1 DE 60228768 T DE60228768 T DE 60228768T DE 60228768 T DE60228768 T DE 60228768T DE 60228768 D1 DE60228768 D1 DE 60228768D1
Authority
DE
Germany
Prior art keywords
completion
completer
packages
procedure
status
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60228768T
Other languages
English (en)
Inventor
David Harriman
David Lee
Kenneth Creta
Jasmin Ajanovic
Gary Solomon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE60228768D1 publication Critical patent/DE60228768D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
DE60228768T 2001-12-28 2002-12-06 Verfahren zur Verarbeitung von Kompletierungspaketen und mit nicht erfolgreichem Kompletierungsstatus Expired - Lifetime DE60228768D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/040,702 US7184399B2 (en) 2001-12-28 2001-12-28 Method for handling completion packets with a non-successful completion status

Publications (1)

Publication Number Publication Date
DE60228768D1 true DE60228768D1 (de) 2008-10-16

Family

ID=21912449

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60228768T Expired - Lifetime DE60228768D1 (de) 2001-12-28 2002-12-06 Verfahren zur Verarbeitung von Kompletierungspaketen und mit nicht erfolgreichem Kompletierungsstatus

Country Status (8)

Country Link
US (1) US7184399B2 (de)
EP (2) EP1585029B1 (de)
CN (1) CN1324499C (de)
AT (1) ATE407405T1 (de)
AU (1) AU2002360516A1 (de)
DE (1) DE60228768D1 (de)
TW (1) TWI264204B (de)
WO (1) WO2003058460A2 (de)

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US7099318B2 (en) * 2001-12-28 2006-08-29 Intel Corporation Communicating message request transaction types between agents in a computer system using multiple message groups
US20050034045A1 (en) * 2003-08-08 2005-02-10 Lueck Andrew W. System for optimizing PCI-Express communications
US20060271718A1 (en) * 2005-05-27 2006-11-30 Diplacido Bruno Jr Method of preventing error propagation in a PCI / PCI-X / PCI express link
US7873018B2 (en) * 2005-06-16 2011-01-18 Nokia Corporation Scheduling data transmissions to improve power efficiency in a wireless network
US8516165B2 (en) * 2005-10-19 2013-08-20 Nvidia Corporation System and method for encoding packet header to enable higher bandwidth efficiency across bus links
US7949794B2 (en) 2006-11-02 2011-05-24 Intel Corporation PCI express enhancements and extensions
US7925931B1 (en) * 2006-12-13 2011-04-12 Nvidia Corporation System and method of handling erroneous data in computer systems
JP5422168B2 (ja) 2008-09-29 2014-02-19 株式会社日立製作所 動画像符号化方法および動画像復号化方法
US8108584B2 (en) * 2008-10-15 2012-01-31 Intel Corporation Use of completer knowledge of memory region ordering requirements to modify transaction attributes
TWI469595B (zh) * 2008-11-27 2015-01-11 Realtek Semiconductor Corp 用於本地端實體層之控制方法及其裝置
WO2012143953A2 (en) * 2011-04-21 2012-10-26 Ineda Systems Pvt. Ltd Optimized multi-root input output virtualization aware switch
US10970238B2 (en) 2019-04-19 2021-04-06 Intel Corporation Non-posted write transactions for a computer bus

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Also Published As

Publication number Publication date
AU2002360516A8 (en) 2003-07-24
CN1324499C (zh) 2007-07-04
US20030174716A1 (en) 2003-09-18
EP1585029A1 (de) 2005-10-12
EP1461712A2 (de) 2004-09-29
CN1608254A (zh) 2005-04-20
ATE407405T1 (de) 2008-09-15
EP1585029B1 (de) 2008-09-03
TWI264204B (en) 2006-10-11
TW200302014A (en) 2003-07-16
WO2003058460A3 (en) 2003-11-20
WO2003058460A2 (en) 2003-07-17
US7184399B2 (en) 2007-02-27
AU2002360516A1 (en) 2003-07-24

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