DE60235697D1 - Vorrichtung zur datenwiederherstellung in einem synchronen chip-zu-chip-system - Google Patents

Vorrichtung zur datenwiederherstellung in einem synchronen chip-zu-chip-system

Info

Publication number
DE60235697D1
DE60235697D1 DE60235697T DE60235697T DE60235697D1 DE 60235697 D1 DE60235697 D1 DE 60235697D1 DE 60235697 T DE60235697 T DE 60235697T DE 60235697 T DE60235697 T DE 60235697T DE 60235697 D1 DE60235697 D1 DE 60235697D1
Authority
DE
Germany
Prior art keywords
chip
recovery device
data recovery
synchronized
chip system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60235697T
Other languages
English (en)
Inventor
Scott C Best
Richard E Warmke
David B Roberts
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc filed Critical Rambus Inc
Application granted granted Critical
Publication of DE60235697D1 publication Critical patent/DE60235697D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
DE60235697T 2001-06-25 2002-06-18 Vorrichtung zur datenwiederherstellung in einem synchronen chip-zu-chip-system Expired - Lifetime DE60235697D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/891,184 US6570944B2 (en) 2001-06-25 2001-06-25 Apparatus for data recovery in a synchronous chip-to-chip system
PCT/US2002/019287 WO2003001732A1 (en) 2001-06-25 2002-06-18 Apparatus for data recovery in a synchronous chip-to-chip system

Publications (1)

Publication Number Publication Date
DE60235697D1 true DE60235697D1 (de) 2010-04-29

Family

ID=25397753

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60235697T Expired - Lifetime DE60235697D1 (de) 2001-06-25 2002-06-18 Vorrichtung zur datenwiederherstellung in einem synchronen chip-zu-chip-system

Country Status (5)

Country Link
US (14) US6570944B2 (de)
EP (3) EP1400052B1 (de)
JP (1) JP4065234B2 (de)
DE (1) DE60235697D1 (de)
WO (1) WO2003001732A1 (de)

Families Citing this family (180)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6570944B2 (en) 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
IT1320459B1 (it) * 2000-06-27 2003-11-26 Cit Alcatel Metodo di allineamento di fase di flussi di dati appartenenti a tramea divisione di tempo relativo circuito.
US6633965B2 (en) * 2001-04-07 2003-10-14 Eric M. Rentschler Memory controller with 1×/M× read capability
US6678811B2 (en) * 2001-04-07 2004-01-13 Hewlett-Packard Development Company, L.P. Memory controller with 1X/MX write capability
US7180352B2 (en) * 2001-06-28 2007-02-20 Intel Corporation Clock recovery using clock phase interpolator
CN1272907C (zh) * 2001-07-27 2006-08-30 国际商业机器公司 具有外部早/晚输入的时钟数据恢复系统
JP2003068077A (ja) * 2001-08-28 2003-03-07 Mitsubishi Electric Corp 半導体記憶装置
US7167023B1 (en) 2001-08-29 2007-01-23 Altera Corporation Multiple data rate interface architecture
US7200769B1 (en) * 2001-08-29 2007-04-03 Altera Corporation Self-compensating delay chain for multiple-date-rate interfaces
US6889334B1 (en) 2001-10-02 2005-05-03 Advanced Micro Devices, Inc. Multimode system for calibrating a data strobe delay for a memory read operation
US20030081709A1 (en) * 2001-10-30 2003-05-01 Sun Microsystems, Inc. Single-ended IO with dynamic synchronous deskewing architecture
US7093150B1 (en) * 2001-12-31 2006-08-15 Richard S. Norman Wavefront clock synchronization
EP1335520B1 (de) * 2002-02-11 2018-05-30 Semiconductor Components Industries, LLC Multiplex-bussystem mit tastverhältniskorrektur
US7139348B1 (en) * 2002-04-09 2006-11-21 Applied Micro Circuits Corporation Distributed clock network using all-digital master-slave delay lock loops
JP3789387B2 (ja) * 2002-04-26 2006-06-21 富士通株式会社 クロック復元回路
US6819599B2 (en) * 2002-08-01 2004-11-16 Micron Technology, Inc. Programmable DQS preamble
JP4168439B2 (ja) * 2002-09-17 2008-10-22 富士ゼロックス株式会社 信号伝送システム
US7123675B2 (en) * 2002-09-25 2006-10-17 Lucent Technologies Inc. Clock, data and time recovery using bit-resolved timing registers
KR100486268B1 (ko) * 2002-10-05 2005-05-03 삼성전자주식회사 내부에서 자체적으로 듀티싸이클 보정을 수행하는지연동기루프 회로 및 이의 듀티싸이클 보정방법
TWI248259B (en) * 2002-10-10 2006-01-21 Mstar Semiconductor Inc Apparatus for generating quadrature phase signals and data recovery circuit using the same
US20040113667A1 (en) * 2002-12-13 2004-06-17 Huawen Jin Delay locked loop with improved strobe skew control
KR100510515B1 (ko) * 2003-01-17 2005-08-26 삼성전자주식회사 공정의 변화에 따라서 클럭신호의 듀티 사이클을 보정하는듀티 사이클 보정회로를 구비하는 반도체 장치
JP2004287691A (ja) * 2003-03-20 2004-10-14 Renesas Technology Corp 半導体集積回路
CN100521597C (zh) * 2003-05-01 2009-07-29 三菱电机株式会社 时钟数据恢复电路
US7336749B2 (en) * 2004-05-18 2008-02-26 Rambus Inc. Statistical margin test methods and circuits
US7590175B2 (en) * 2003-05-20 2009-09-15 Rambus Inc. DFE margin test methods and circuits that decouple sample and feedback timing
US7408981B2 (en) * 2003-05-20 2008-08-05 Rambus Inc. Methods and circuits for performing margining tests in the presence of a decision feedback equalizer
US7627029B2 (en) 2003-05-20 2009-12-01 Rambus Inc. Margin test methods and circuits
KR100546368B1 (ko) * 2003-08-22 2006-01-26 삼성전자주식회사 센터링 에러를 일으키는 클럭 스큐를 자체적으로 보상하는메모리 장치 및 그 클럭 스큐 보상 방법
US6930932B2 (en) * 2003-08-27 2005-08-16 Hewlett-Packard Development Company, L.P. Data signal reception latch control using clock aligned relative to strobe signal
US7132866B2 (en) 2003-09-03 2006-11-07 Broadcom Corporation Method and apparatus for glitch-free control of a delay-locked loop in a network device
JP4450586B2 (ja) * 2003-09-03 2010-04-14 株式会社ルネサステクノロジ 半導体集積回路
JP4242741B2 (ja) * 2003-09-19 2009-03-25 パナソニック株式会社 デバッグ用信号処理回路
US8675722B2 (en) * 2003-09-23 2014-03-18 International Business Machines Corporation Methods and apparatus for snapshot-based equalization of a communications channel
US7230506B2 (en) * 2003-10-09 2007-06-12 Synopsys, Inc. Crosstalk reduction for a system of differential line pairs
KR100550796B1 (ko) * 2003-12-11 2006-02-08 주식회사 하이닉스반도체 반도체 메모리 소자의 데이터 전송 장치 및 그 제어 방법
US7702030B2 (en) * 2003-12-17 2010-04-20 Mindspeed Technologies, Inc. Module to module signaling with jitter modulation
US7031221B2 (en) * 2003-12-30 2006-04-18 Intel Corporation Fixed phase clock and strobe signals in daisy chained chips
EP1555675B1 (de) * 2004-01-15 2007-07-04 Infineon Technologies AG Vorrichtung zur Bestimmung der Zugriffszeit und/oder der minimalen Zykluszeit eines Speichers
KR100558557B1 (ko) * 2004-01-20 2006-03-10 삼성전자주식회사 반도체 메모리 장치에서의 데이터 샘플링 방법 및 그에따른 데이터 샘플링 회로
US7259606B2 (en) 2004-01-27 2007-08-21 Nvidia Corporation Data sampling clock edge placement training for high speed GPU-memory interface
US7234069B1 (en) 2004-03-12 2007-06-19 Altera Corporation Precise phase shifting using a DLL controlled, multi-stage delay chain
US7319345B2 (en) * 2004-05-18 2008-01-15 Rambus Inc. Wide-range multi-phase clock generator
WO2005117259A1 (ja) * 2004-05-26 2005-12-08 Matsushita Electric Industrial Co., Ltd. スキュー補正装置
US7126399B1 (en) 2004-05-27 2006-10-24 Altera Corporation Memory interface phase-shift circuitry to support multiple frequency ranges
US7123051B1 (en) 2004-06-21 2006-10-17 Altera Corporation Soft core control of dedicated memory interface hardware in a programmable logic device
JP4416580B2 (ja) * 2004-06-28 2010-02-17 株式会社リコー 遅延制御装置
JP4390646B2 (ja) * 2004-07-09 2009-12-24 Ｎｅｃエレクトロニクス株式会社 スプレッドスペクトラムクロック生成器及びその変調方法
US7551852B2 (en) * 2004-08-10 2009-06-23 Mindspeed Technologies, Inc. Module to module signaling
US7583902B2 (en) * 2004-08-10 2009-09-01 Mindspeed Technologies, Inc. Module to module signaling utilizing amplitude modulation
US7171321B2 (en) 2004-08-20 2007-01-30 Rambus Inc. Individual data line strobe-offset control in memory systems
US7126874B2 (en) * 2004-08-31 2006-10-24 Micron Technology, Inc. Memory system and method for strobing data, command and address signals
US7504610B2 (en) * 2004-09-03 2009-03-17 Mindspeed Technologies, Inc. Optical modulation amplitude compensation system having a laser driver with modulation control signals
US7173877B2 (en) * 2004-09-30 2007-02-06 Infineon Technologies Ag Memory system with two clock lines and a memory device
US20060077893A1 (en) * 2004-10-13 2006-04-13 Aiguo Yan Methods and apparatus for wireless system communication
US7555091B1 (en) * 2004-10-26 2009-06-30 National Semiconductor Corporation System and method for providing a clock and data recovery circuit with a self test capability
US7543172B2 (en) 2004-12-21 2009-06-02 Rambus Inc. Strobe masking in a signaling system having multiple clock domains
US7627069B2 (en) * 2005-01-27 2009-12-01 Rambus Inc. Digital transmit phase trimming
US7583772B2 (en) * 2005-02-22 2009-09-01 Broadcom Corporation System for shifting data bits multiple times per clock cycle
US20060187729A1 (en) * 2005-02-24 2006-08-24 Broadcom Corporation Source synchronous communication channel interface receive logic
US20060188046A1 (en) * 2005-02-24 2006-08-24 Broadcom Corporation Prediction of an optimal sampling point for clock resynchronization in a source synchronous data channel
US7209396B2 (en) * 2005-02-28 2007-04-24 Infineon Technologies Ag Data strobe synchronization for DRAM devices
US7332916B2 (en) * 2005-03-03 2008-02-19 Semiconductor Technology Academic Research Center On-chip signal waveform measurement apparatus for measuring signal waveforms at detection points on IC chip
US7688672B2 (en) * 2005-03-14 2010-03-30 Rambus Inc. Self-timed interface for strobe-based systems
DE102005019041B4 (de) * 2005-04-23 2009-04-16 Qimonda Ag Halbleiterspeicher und Verfahren zur Anpassung der Phasenbeziehung zwischen einem Taktsignal und Strobe-Signal bei der Übernahme von zu übertragenden Schreibdaten
KR100709475B1 (ko) 2005-05-30 2007-04-18 주식회사 하이닉스반도체 Ｄｌｌ 회로의 듀티 사이클 보정회로
US7743288B1 (en) * 2005-06-01 2010-06-22 Altera Corporation Built-in at-speed bit error ratio tester
US7512201B2 (en) * 2005-06-14 2009-03-31 International Business Machines Corporation Multi-channel synchronization architecture
US7332950B2 (en) * 2005-06-14 2008-02-19 Micron Technology, Inc. DLL measure initialization circuit for high frequency operation
US7688925B2 (en) * 2005-08-01 2010-03-30 Ati Technologies, Inc. Bit-deskewing IO method and system
US7250801B2 (en) * 2005-08-25 2007-07-31 Infineon Technologies Ag Differential duty cycle restoration
KR100834400B1 (ko) * 2005-09-28 2008-06-04 주식회사 하이닉스반도체 Ｄｒａｍ의 동작 주파수를 높이기 위한 지연고정루프 및 그의 출력드라이버
US7555670B2 (en) * 2005-10-26 2009-06-30 Intel Corporation Clocking architecture using a bidirectional clock port
US7450535B2 (en) * 2005-12-01 2008-11-11 Rambus Inc. Pulsed signaling multiplexer
JP2007164599A (ja) 2005-12-15 2007-06-28 Elpida Memory Inc メモリモジュール
KR100759786B1 (ko) * 2006-02-01 2007-09-20 삼성전자주식회사 반도체 장치의 지연동기루프 회로 및 지연동기루프제어방법
JP4371113B2 (ja) 2006-02-21 2009-11-25 ソニー株式会社 デジタルｄｌｌ回路
JP2007228044A (ja) 2006-02-21 2007-09-06 Sony Corp デジタルｄｌｌ回路
JP4371112B2 (ja) 2006-02-21 2009-11-25 ソニー株式会社 デジタルｄｌｌ回路
US7716511B2 (en) * 2006-03-08 2010-05-11 Freescale Semiconductor, Inc. Dynamic timing adjustment in a circuit device
US8121237B2 (en) 2006-03-16 2012-02-21 Rambus Inc. Signaling system with adaptive timing calibration
US7664978B2 (en) * 2006-04-07 2010-02-16 Altera Corporation Memory interface circuitry with phase detection
US7647467B1 (en) 2006-05-25 2010-01-12 Nvidia Corporation Tuning DRAM I/O parameters on the fly
JP4878215B2 (ja) * 2006-05-26 2012-02-15 ルネサスエレクトロニクス株式会社 インタフェース回路及びメモリ制御装置
KR100809692B1 (ko) * 2006-08-01 2008-03-06 삼성전자주식회사 작은 지터를 갖는 지연동기 루프 회로 및 이의 지터감소방법
US7948812B2 (en) * 2006-11-20 2011-05-24 Rambus Inc. Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
US7978541B2 (en) * 2007-01-02 2011-07-12 Marvell World Trade Ltd. High speed interface for multi-level memory
JP4930074B2 (ja) * 2007-01-24 2012-05-09 富士通株式会社 位相調整機能の評価方法、情報処理装置、プログラム及びコンピュータ読取可能な情報記録媒体
JP4837586B2 (ja) * 2007-01-30 2011-12-14 ルネサスエレクトロニクス株式会社 半導体装置
FR2914807B1 (fr) * 2007-04-06 2012-11-16 Centre Nat Detudes Spatiales Cnes Dispositif d'extraction d'horloge a asservissement numerique de phase sans reglage externe
JP4774005B2 (ja) * 2007-04-11 2011-09-14 ザインエレクトロニクス株式会社 受信装置
CN101681670B (zh) * 2007-04-19 2014-02-05 拉姆伯斯公司 存储器系统中的时钟同步
US8504865B2 (en) * 2007-04-20 2013-08-06 Easic Corporation Dynamic phase alignment
JP4657252B2 (ja) * 2007-06-04 2011-03-23 三洋電機株式会社 チャージポンプ回路及びスライスレベルコントロール回路
US7861105B2 (en) * 2007-06-25 2010-12-28 Analogix Semiconductor, Inc. Clock data recovery (CDR) system using interpolator and timing loop module
US7913103B2 (en) * 2007-08-31 2011-03-22 Globalfoundries Inc. Method and apparatus for clock cycle stealing
US20090068314A1 (en) * 2007-09-12 2009-03-12 Robert Chatel Granulation Method And Additives With Narrow Particle Size Distribution Produced From Granulation Method
KR100930401B1 (ko) * 2007-10-09 2009-12-08 주식회사 하이닉스반도체 반도체 메모리 장치
US8793525B2 (en) 2007-10-22 2014-07-29 Rambus Inc. Low-power source-synchronous signaling
KR100903365B1 (ko) * 2007-11-02 2009-06-23 주식회사 하이닉스반도체 반도체 메모리 장치
JP5369430B2 (ja) 2007-11-20 2013-12-18 富士通株式会社 可変遅延回路，メモリ制御回路，遅延量設定装置，遅延量設定方法および遅延量設定プログラム
US8750341B2 (en) * 2008-01-04 2014-06-10 Mindspeed Technologies, Inc. Method and apparatus for reducing optical signal speckle
US8824223B2 (en) * 2008-02-05 2014-09-02 SK Hynix Inc. Semiconductor memory apparatus with clock and data strobe phase detection
KR101442173B1 (ko) * 2008-02-15 2014-09-18 삼성전자주식회사 데이터 송수신 시스템 및 에러 교정 방법
JP2009231896A (ja) * 2008-03-19 2009-10-08 Fujitsu Ltd 受信装置および受信方法
JP2011522280A (ja) 2008-03-31 2011-07-28 マインドスピード・テクノロジーズ・インコーポレイテッド 携帯用ＬＣｏＳ／ＬＣＤ／ＤＬＰ投影システムにおける電力損の低減
US7728638B2 (en) * 2008-04-25 2010-06-01 Qimonda North America Corp. Electronic system that adjusts DLL lock state acquisition time
US8300752B2 (en) * 2008-08-15 2012-10-30 International Business Machines Corporation Method, circuit, and design structure for capturing data across a pseudo-synchronous interface
US8189723B2 (en) * 2008-08-15 2012-05-29 International Business Machines Corporation Method, circuit, and design structure for capturing data across a pseudo-synchronous interface
US8237475B1 (en) * 2008-10-08 2012-08-07 Altera Corporation Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop
KR101529675B1 (ko) * 2008-12-26 2015-06-29 삼성전자주식회사 멀티 칩 패키지 메모리 장치
JP2010171826A (ja) * 2009-01-23 2010-08-05 Ricoh Co Ltd メモリモジュールのコントローラ
EP2405601A1 (de) * 2009-03-04 2012-01-11 Fujitsu Limited Datentransfereinrichtung, datenübertragungseinrichtung, datenempfangseinrichtung und steuerverfahren
US8098535B2 (en) * 2009-03-30 2012-01-17 Cadence Design Systems, Inc. Method and apparatus for gate training in memory interfaces
US8269538B2 (en) * 2009-04-27 2012-09-18 Mosys, Inc. Signal alignment system
US8363492B2 (en) * 2009-05-27 2013-01-29 Panasonic Corporation Delay adjustment device and delay adjustment method
KR101003155B1 (ko) * 2009-06-29 2010-12-22 한양대학교 산학협력단 반도체 메모리 장치의 데이터 정렬 회로 및 방법
US8489912B2 (en) * 2009-09-09 2013-07-16 Ati Technologies Ulc Command protocol for adjustment of write timing delay
US8228101B2 (en) * 2009-09-14 2012-07-24 Achronix Semiconductor Corporation Source-synchronous clocking
JP5537568B2 (ja) * 2009-12-25 2014-07-02 富士通株式会社 信号受信回路、メモリコントローラ、プロセッサ、コンピュータ及び位相制御方法
US8362996B2 (en) * 2010-02-12 2013-01-29 Au Optronics Corporation Display with CLK phase auto-adjusting mechanism and method of driving same
KR20120044668A (ko) * 2010-10-28 2012-05-08 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그를 포함하는 반도체 시스템
KR20120046885A (ko) * 2010-10-29 2012-05-11 에스케이하이닉스 주식회사 반도체 집적회로
US8643296B2 (en) 2010-11-22 2014-02-04 Mindspeed Technologies, Inc. Color mixing and desaturation with reduced number of converters
WO2012074689A1 (en) 2010-11-29 2012-06-07 Rambus Inc. Clock generation for timing communications with ranks of memory devices
TWI469522B (zh) * 2011-01-06 2015-01-11 Raydium Semiconductor Corp 訊號電路
US8644085B2 (en) * 2011-04-05 2014-02-04 International Business Machines Corporation Duty cycle distortion correction
US9107245B2 (en) 2011-06-09 2015-08-11 Mindspeed Technologies, Inc. High accuracy, high dynamic range LED/laser driver
US9431089B2 (en) * 2012-06-12 2016-08-30 Rambus Inc. Optimizing power in a memory device
US9363115B2 (en) * 2012-07-02 2016-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for aligning data bits
US9385606B2 (en) 2012-12-03 2016-07-05 M/A-Com Technology Solutions Holdings, Inc. Automatic buck/boost mode selection system for DC-DC converter
US8766695B1 (en) * 2012-12-28 2014-07-01 Sandisk Technologies Inc. Clock generation and delay architecture
JP5794352B2 (ja) 2013-05-29 2015-10-14 株式会社デンソー 受信装置及び受信ビット列の同一値ビット数検出方法
JP5751290B2 (ja) 2013-07-11 2015-07-22 株式会社デンソー データ受信装置及び受信ビット列の同一値ビット長判定方法
JP6098418B2 (ja) 2013-07-26 2017-03-22 富士通株式会社 信号制御回路、情報処理装置及びデューティ算出方法
WO2015038867A1 (en) 2013-09-16 2015-03-19 Rambus Inc. Source-synchronous receiver using edged-detection clock recovery
US9021154B2 (en) 2013-09-27 2015-04-28 Intel Corporation Read training a memory controller
US9331701B1 (en) * 2014-06-11 2016-05-03 Xilinx, Inc. Receivers and methods of enabling the calibration of circuits receiving input data
US10097908B2 (en) 2014-12-31 2018-10-09 Macom Technology Solutions Holdings, Inc. DC-coupled laser driver with AC-coupled termination element
KR102263803B1 (ko) * 2015-01-05 2021-06-10 에스케이텔레콤 주식회사 메모리장치 및 메모리장치의 동작 방법
US9305622B1 (en) * 2015-01-23 2016-04-05 Apple Inc. Data strobe to data delay calibration
US9251906B1 (en) * 2015-05-18 2016-02-02 Freescale Semiconductor, Inc. Data strobe signal generation for flash memory
US9407273B1 (en) * 2015-06-04 2016-08-02 Intel Corporation Digital delay-locked loop (DLL) training
US9485082B1 (en) * 2015-06-23 2016-11-01 Qualcomm Incorporated Multi-mode phase-frequency detector for clock and data recovery
US9786353B2 (en) 2016-02-18 2017-10-10 Intel Corporation Reconfigurable clocking architecture
WO2018045093A1 (en) 2016-08-30 2018-03-08 Macom Technology Solutions Holdings, Inc. Driver with distributed architecture
US9698792B1 (en) * 2016-11-22 2017-07-04 Nxp B.V. System and method for clocking digital logic circuits
US9990973B1 (en) * 2017-02-17 2018-06-05 Apple Inc. Systems and methods using neighboring sample points in memory subsystem calibration
US10325636B1 (en) 2017-05-01 2019-06-18 Rambus Inc. Signal receiver with skew-tolerant strobe gating
US10622044B2 (en) 2017-09-22 2020-04-14 Qualcomm Incorporated Memory hold margin characterization and correction circuit
US10063222B1 (en) 2017-09-25 2018-08-28 International Business Machines Corporation Dynamic control of edge shift for duty cycle correction
US10892744B2 (en) 2017-09-25 2021-01-12 International Business Machines Corporation Correcting duty cycle and compensating for active clock edge shift
US10622981B2 (en) * 2017-09-25 2020-04-14 International Business Machines Corporation Static compensation of an active clock edge shift for a duty cycle correction circuit
US10630052B2 (en) 2017-10-04 2020-04-21 Macom Technology Solutions Holdings, Inc. Efficiency improved driver for laser diode in optical communication
KR102499037B1 (ko) 2018-01-10 2023-02-13 삼성전자주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
US10771068B2 (en) 2018-02-20 2020-09-08 International Business Machines Corporation Reducing chip latency at a clock boundary by reference clock phase adjustment
US10243762B1 (en) * 2018-04-16 2019-03-26 Macom Connectivity Solutions, Llc Analog delay based fractionally spaced n-tap feed-forward equalizer for wireline and optical transmitters
KR20190121121A (ko) * 2018-04-17 2019-10-25 에스케이하이닉스 주식회사 반도체장치
US10395702B1 (en) 2018-05-11 2019-08-27 Micron Technology, Inc. Memory device with a clocking mechanism
US10418125B1 (en) * 2018-07-19 2019-09-17 Marvell Semiconductor Write and read common leveling for 4-bit wide DRAMs
KR102644052B1 (ko) * 2018-09-28 2024-03-07 에스케이하이닉스 주식회사 데이터 수신 회로
KR20200049985A (ko) * 2018-10-30 2020-05-11 삼성전자주식회사 복수의 트레이닝들을 동시에 수행하는 시스템 온 칩, 시스템 온 칩의 동작 방법, 및 시스템 온 칩을 포함하는 전자 장치
US11005573B2 (en) 2018-11-20 2021-05-11 Macom Technology Solutions Holdings, Inc. Optic signal receiver with dynamic control
CN111355484B (zh) * 2018-12-20 2023-09-05 深圳市中兴微电子技术有限公司 一种实现数据同步的装置和方法
US10734983B1 (en) * 2019-02-15 2020-08-04 Apple Inc. Duty cycle correction with read and write calibration
US10686582B1 (en) * 2019-02-25 2020-06-16 Intel Corporation Clock phase compensation apparatus and method
WO2020176448A1 (en) 2019-02-27 2020-09-03 Rambus Inc. Low power memory with on-demand bandwidth boost
US11127444B1 (en) 2019-08-20 2021-09-21 Rambus Inc. Signal receiver with skew-tolerant strobe gating
US11575437B2 (en) 2020-01-10 2023-02-07 Macom Technology Solutions Holdings, Inc. Optimal equalization partitioning
EP4088394A4 (de) 2020-01-10 2024-02-07 Macom Tech Solutions Holdings Inc Optimale entzerrung der partitionierung
TWI733415B (zh) * 2020-04-16 2021-07-11 瑞昱半導體股份有限公司 鎖相迴路裝置與時脈產生方法
US10972106B1 (en) * 2020-11-06 2021-04-06 Movellus Circuits, Inc. Phase and delay compensation circuit and method
US11165432B1 (en) 2020-11-06 2021-11-02 Movellus Circuits, Inc. Glitch-free digital controlled delay line apparatus and method
US11374578B2 (en) 2020-11-06 2022-06-28 Movellus Circuits Inc. Zero-offset phase detector apparatus and method
US11782476B2 (en) 2020-12-04 2023-10-10 Rambus Inc. Circuits and methods for sample timing in correlated and uncorrelated signaling environments
US11658630B2 (en) 2020-12-04 2023-05-23 Macom Technology Solutions Holdings, Inc. Single servo loop controlling an automatic gain control and current sourcing mechanism
US11616529B2 (en) 2021-02-12 2023-03-28 Macom Technology Solutions Holdings, Inc. Adaptive cable equalizer
KR20220121632A (ko) 2021-02-25 2022-09-01 삼성전자주식회사 집적회로 및 집적회로 동작 방법
JP2022146543A (ja) * 2021-03-22 2022-10-05 キオクシア株式会社 半導体記憶装置、メモリシステム、および方法
US20230393929A1 (en) * 2022-06-01 2023-12-07 Micron Technology, Inc. System And Method To Control Memory Error Detection With Automatic Disabling

Family Cites Families (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6570944B2 (en) 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
US4531526A (en) * 1981-08-07 1985-07-30 Genest Leonard Joseph Remote sensor telemetering system
US4663735A (en) 1983-12-30 1987-05-05 Texas Instruments Incorporated Random/serial access mode selection circuit for a video memory system
US5056118A (en) * 1989-05-16 1991-10-08 Rockwell International Corporation Method and apparatus for clock and data recovery with high jitter tolerance
US5097489A (en) * 1989-05-19 1992-03-17 Tucci Patrick A Method for incorporating window strobe in a data synchronizer
JPH088514B2 (ja) * 1991-11-20 1996-01-29 クラリオン株式会社 ディジタル相関装置
US5485490A (en) 1992-05-28 1996-01-16 Rambus, Inc. Method and circuitry for clock synchronization
US5367542A (en) * 1992-06-19 1994-11-22 Advanced Micro Devices, Inc. Digital data recovery using delay time rulers
US5400370A (en) * 1993-02-24 1995-03-21 Advanced Micro Devices Inc. All digital high speed algorithmic data recovery method and apparatus using locally generated compensated broad band time rulers and data edge position averaging
JP3489147B2 (ja) * 1993-09-20 2004-01-19 株式会社日立製作所 データ転送方式
US5870549A (en) 1995-04-28 1999-02-09 Bobo, Ii; Charles R. Systems and methods for storing, delivering, and managing messages
US5642386A (en) * 1994-06-30 1997-06-24 Massachusetts Institute Of Technology Data sampling circuit for a burst mode communication system
US5838749A (en) * 1995-06-05 1998-11-17 Broadband Communications Products, Inc. Method and apparatus for extracting an embedded clock from a digital data signal
US5850422A (en) * 1995-07-21 1998-12-15 Symbios, Inc. Apparatus and method for recovering a clock signal which is embedded in an incoming data stream
JP3673303B2 (ja) * 1995-07-27 2005-07-20 株式会社日立製作所 映像信号処理装置
US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
US6470405B2 (en) 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US5646968A (en) * 1995-11-17 1997-07-08 Analog Devices, Inc. Dynamic phase selector phase locked loop circuit
US5790607A (en) * 1995-11-28 1998-08-04 Motorola Inc. Apparatus and method for recovery of symbol timing for asynchronous data transmission
US5870446A (en) * 1996-03-11 1999-02-09 Adtran, Inc. Mechanism for automatically adjusting the phase of a transmission strobe clock signal to correct for misalignment of transmission clock and data signals
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
GB9609702D0 (en) 1996-05-09 1996-07-10 Royal Free Hosp School Med Anticoagulant peptides
TW340262B (en) 1996-08-13 1998-09-11 Fujitsu Ltd Semiconductor device, system consisting of semiconductor devices and digital delay circuit
US5844436A (en) * 1996-11-06 1998-12-01 Northern Telecom Ltd. Method of recovering a sampling clock in a framed data communications format with reduced phase jitter and wander
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
JP3420018B2 (ja) * 1997-04-25 2003-06-23 株式会社東芝 データレシーバ
JP3209943B2 (ja) * 1997-06-13 2001-09-17 沖電気工業株式会社 電圧制御遅延回路、直接位相制御型電圧制御発振器、クロック／データ再生回路及びクロック／データ再生装置
US5910740A (en) * 1997-06-18 1999-06-08 Raytheon Company Phase locked loop having memory
US6442644B1 (en) 1997-08-11 2002-08-27 Advanced Memory International, Inc. Memory system having synchronous-link DRAM (SLDRAM) devices and controller
JPH1174878A (ja) * 1997-08-28 1999-03-16 Mitsubishi Electric Corp デジタルデータ伝送システム
US5948083A (en) * 1997-09-30 1999-09-07 S3 Incorporated System and method for self-adjusting data strobe
JPH11122229A (ja) * 1997-10-17 1999-04-30 Fujitsu Ltd リタイミング回路およびリタイミング方法
JP3649878B2 (ja) * 1997-10-20 2005-05-18 富士通株式会社 デジタル無線通信装置の検波方法及びその回路
EP1674881A3 (de) * 1997-11-19 2008-04-16 IMEC vzw Verfahren und Vorrichtung zum Empfang von GPS-/GLONASS-Signalen
US6085345A (en) 1997-12-24 2000-07-04 Intel Corporation Timing control for input/output testability
GB2333916B (en) * 1998-01-09 2001-08-01 Plessey Semiconductors Ltd A phase detector
US6111446A (en) 1998-03-20 2000-08-29 Micron Technology, Inc. Integrated circuit data latch driver circuit
US6172937B1 (en) * 1998-05-13 2001-01-09 Intel Corporation Multiple synthesizer based timing signal generation scheme
US6100733A (en) 1998-06-09 2000-08-08 Siemens Aktiengesellschaft Clock latency compensation circuit for DDR timing
US6510503B2 (en) 1998-07-27 2003-01-21 Mosaid Technologies Incorporated High bandwidth memory interface
US6279090B1 (en) * 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
JP3880286B2 (ja) * 1999-05-12 2007-02-14 エルピーダメモリ株式会社 方向性結合式メモリシステム
US6401213B1 (en) * 1999-07-09 2002-06-04 Micron Technology, Inc. Timing circuit for high speed memory
US6775345B1 (en) * 1999-12-30 2004-08-10 Intel Corporation Delay locked loop based data recovery circuit for data communication
EP1128594A1 (de) * 2000-02-24 2001-08-29 STMicroelectronics S.r.l. Synchroner Schalter zur Datenrückgewinnung
US6518794B2 (en) * 2000-04-24 2003-02-11 International Business Machines Corporation AC drive cross point adjust method and apparatus
JP2001306176A (ja) 2000-04-26 2001-11-02 Nec Corp クロック位相自動調整回路
US6701140B1 (en) * 2000-09-14 2004-03-02 3Com Corporation Digital receive phase lock loop with cumulative phase error correction and dynamically programmable correction rate
KR100360408B1 (ko) * 2000-09-16 2002-11-13 삼성전자 주식회사 독출동작시 데이터 스트로브 신호와 동일한 신호를출력하는 데이터 마스킹핀을 갖는 반도체 메모리장치 및이를 구비하는 메모리 시스템
US20020090045A1 (en) * 2001-01-10 2002-07-11 Norm Hendrickson Digital clock recovery system
US6678811B2 (en) * 2001-04-07 2004-01-13 Hewlett-Packard Development Company, L.P. Memory controller with 1X/MX write capability
US6570813B2 (en) * 2001-05-25 2003-05-27 Micron Technology, Inc. Synchronous mirror delay with reduced delay line taps
US6819599B2 (en) * 2002-08-01 2004-11-16 Micron Technology, Inc. Programmable DQS preamble
DE10344818B4 (de) 2003-09-27 2008-08-14 Qimonda Ag Vorrichtung zum Kalibrieren der relativen Phase zweier Empfangssignale eines Speicherbausteins
US7171321B2 (en) 2004-08-20 2007-01-30 Rambus Inc. Individual data line strobe-offset control in memory systems
US7307900B2 (en) 2004-11-30 2007-12-11 Intel Corporation Method and apparatus for optimizing strobe to clock relationship
DE102005019041B4 (de) 2005-04-23 2009-04-16 Qimonda Ag Halbleiterspeicher und Verfahren zur Anpassung der Phasenbeziehung zwischen einem Taktsignal und Strobe-Signal bei der Übernahme von zu übertragenden Schreibdaten
US7379382B2 (en) 2005-10-28 2008-05-27 Micron Technology, Inc. System and method for controlling timing of output signals

Also Published As

Publication number Publication date
US9741423B2 (en) 2017-08-22
US6836503B2 (en) 2004-12-28
US20190198085A1 (en) 2019-06-27
EP1400052A1 (de) 2004-03-24
US20030112909A1 (en) 2003-06-19
US7970089B2 (en) 2011-06-28
US20080181348A1 (en) 2008-07-31
WO2003001732A1 (en) 2003-01-03
US6570944B2 (en) 2003-05-27
US20100073047A1 (en) 2010-03-25
US20170154665A1 (en) 2017-06-01
EP1400052A4 (de) 2006-08-02
US20040213067A1 (en) 2004-10-28
US20120166863A1 (en) 2012-06-28
EP2197143A3 (de) 2010-07-28
EP2302831B1 (de) 2012-06-06
US8355480B2 (en) 2013-01-15
US9466353B2 (en) 2016-10-11
US10699769B2 (en) 2020-06-30
US20160125929A1 (en) 2016-05-05
US10192610B2 (en) 2019-01-29
EP2197143A2 (de) 2010-06-16
US20020196883A1 (en) 2002-12-26
US7627066B2 (en) 2009-12-01
US9159388B2 (en) 2015-10-13
EP2302831A1 (de) 2011-03-30
US20130094310A1 (en) 2013-04-18
EP2197143B1 (de) 2011-11-02
US20210027826A1 (en) 2021-01-28
US8208595B2 (en) 2012-06-26
US7349510B2 (en) 2008-03-25
JP4065234B2 (ja) 2008-03-19
US8666007B2 (en) 2014-03-04
EP1400052B1 (de) 2010-03-17
US20140233333A1 (en) 2014-08-21
US20180047437A1 (en) 2018-02-15
US20110255615A1 (en) 2011-10-20
JP2004531981A (ja) 2004-10-14

Similar Documents

Publication Publication Date Title
DE60235697D1 (de) Vorrichtung zur datenwiederherstellung in einem synchronen chip-zu-chip-system
DE60135264D1 (de) Persönliches Betrachtungsgerät mit einem System zur Identifizierung zu einem angeschlossenen System
HK1078159A1 (zh) 資訊組織系統及方法
DE60237664D1 (de) Vorrichtung zur datenspeicherung
DE60213867D1 (de) Vorrichtung zur verwaltung von datenreplikation
DE60231696D1 (de) Synchronisierung in einem verteilten System
DE60227220D1 (de) Vorrichtung zur informationsverarbeitung
GB0323780D0 (en) A data brokering method and system
GB2385959B (en) Data collection system
EP1446735A4 (de) System und verfahren zum durchsuchen von datenquellen
SI1800484T1 (sl) Sistem in postopek za identificiranje in obdelavo podatkov znotraj podatkovnega toka
EP1454291A4 (de) Systeme zum sicheren markieren von daten
DE602004029315D1 (de) Verfahren und Vorrichtung zur Verteilung von Weglenkungsinformation in einem Kommunikationssystem
GB0412458D0 (en) Parallel board connection system and method
DE60035731D1 (de) Vorrichtung zur Taktrückgewinnung
GB2405237B (en) A method and system for archiving and restoring data from an operations center in a utility data center
DE50107624D1 (de) Verfahren zur erhöhung des datendurchsatzes in einem kommunikationssystem
DE60030902D1 (de) Vorrichtung zum Datenempfang
NO20016285L (no) Datainnsamlingssystem for et fartöy
EP1368202A4 (de) Vorrichtung, system und verfahren zur etikettierung von dreidimensionalen objekten
ATA4292001A (de) Kommunikationsverfahren zur realisierung von ereigniskanälen in einem zeitgesteuerten kommunikationssystem
DE60211854D1 (de) Vorrichtung zur datenverarbeitung
EP1586388A4 (de) Trenn-rückgewinnungsverfahren und trennrückgewinnungssystem sowie trennrückgewinnungsvorrichtung für mit einem papierbogen verbundenes ic-etikett
TWI319850B (en) System and method for error capture and logging in computer systems
AU2002366408A8 (en) Method for data processing in a multi-processor data processing system and a corresponding data processing system

Legal Events

Date Code Title Description
8364 No opposition during term of opposition