DE60303511D1 - Verfahren zum löschen eines flash-speichers unter verwendung eines prä-lösch verfahrensschritts - Google Patents
Verfahren zum löschen eines flash-speichers unter verwendung eines prä-lösch verfahrensschrittsInfo
- Publication number
- DE60303511D1 DE60303511D1 DE60303511T DE60303511T DE60303511D1 DE 60303511 D1 DE60303511 D1 DE 60303511D1 DE 60303511 T DE60303511 T DE 60303511T DE 60303511 T DE60303511 T DE 60303511T DE 60303511 D1 DE60303511 D1 DE 60303511D1
- Authority
- DE
- Germany
- Prior art keywords
- procedure
- erring
- deleting
- flash memory
- flash
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/107—Programming all cells in an array, sector or block to the same state prior to flash erasing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
- G11C11/5635—Erasing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/155,767 US20030218913A1 (en) | 2002-05-24 | 2002-05-24 | Stepped pre-erase voltages for mirrorbit erase |
| US155767 | 2002-05-24 | ||
| PCT/US2003/012636 WO2003100790A1 (en) | 2002-05-24 | 2003-04-22 | Method of erasing a flashing memory using a pre-erasing step |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE60303511D1 true DE60303511D1 (de) | 2006-04-20 |
| DE60303511T2 DE60303511T2 (de) | 2006-09-28 |
Family
ID=29549160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60303511T Expired - Lifetime DE60303511T2 (de) | 2002-05-24 | 2003-04-22 | Verfahren zum löschen eines flash-speichers unter verwendung eines prä-lösch verfahrensschritts |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US20030218913A1 (de) |
| EP (1) | EP1518247B1 (de) |
| JP (1) | JP2005527061A (de) |
| KR (1) | KR100960352B1 (de) |
| CN (1) | CN100470679C (de) |
| AU (1) | AU2003228669A1 (de) |
| DE (1) | DE60303511T2 (de) |
| TW (1) | TWI300566B (de) |
| WO (1) | WO2003100790A1 (de) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6700818B2 (en) * | 2002-01-31 | 2004-03-02 | Saifun Semiconductors Ltd. | Method for operating a memory device |
| US6917544B2 (en) | 2002-07-10 | 2005-07-12 | Saifun Semiconductors Ltd. | Multiple use memory chip |
| US7136304B2 (en) | 2002-10-29 | 2006-11-14 | Saifun Semiconductor Ltd | Method, system and circuit for programming a non-volatile memory array |
| US7178004B2 (en) | 2003-01-31 | 2007-02-13 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
| WO2005017911A1 (en) * | 2003-08-13 | 2005-02-24 | Koninklijke Philips Electronics N.V. | Improved erase and read schemes for charge trapping non-volatile memories |
| WO2005094178A2 (en) | 2004-04-01 | 2005-10-13 | Saifun Semiconductors Ltd. | Method, circuit and systems for erasing one or more non-volatile memory cells |
| US7638850B2 (en) | 2004-10-14 | 2009-12-29 | Saifun Semiconductors Ltd. | Non-volatile memory structure and method of fabrication |
| WO2006080063A1 (ja) * | 2005-01-27 | 2006-08-03 | Spansion Llc | 半導体装置、アドレス割り付け方法及びベリファイ方法 |
| US8053812B2 (en) | 2005-03-17 | 2011-11-08 | Spansion Israel Ltd | Contact in planar NROM technology |
| US8400841B2 (en) | 2005-06-15 | 2013-03-19 | Spansion Israel Ltd. | Device to program adjacent storage cells of different NROM cells |
| EP1746645A3 (de) | 2005-07-18 | 2009-01-21 | Saifun Semiconductors Ltd. | Speicherzellenanordnung mit sub-minimalem Wortleitungsabstand und Verfahren zu deren Herstellung |
| US7668017B2 (en) | 2005-08-17 | 2010-02-23 | Saifun Semiconductors Ltd. | Method of erasing non-volatile memory cells |
| US8116142B2 (en) * | 2005-09-06 | 2012-02-14 | Infineon Technologies Ag | Method and circuit for erasing a non-volatile memory cell |
| US7808818B2 (en) | 2006-01-12 | 2010-10-05 | Saifun Semiconductors Ltd. | Secondary injection for NROM |
| US7760554B2 (en) | 2006-02-21 | 2010-07-20 | Saifun Semiconductors Ltd. | NROM non-volatile memory and mode of operation |
| US8253452B2 (en) | 2006-02-21 | 2012-08-28 | Spansion Israel Ltd | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
| US7692961B2 (en) | 2006-02-21 | 2010-04-06 | Saifun Semiconductors Ltd. | Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection |
| US20070247924A1 (en) * | 2006-04-06 | 2007-10-25 | Wei Zheng | Methods for erasing memory devices and multi-level programming memory device |
| US7701779B2 (en) | 2006-04-27 | 2010-04-20 | Sajfun Semiconductors Ltd. | Method for programming a reference cell |
| US7746706B2 (en) * | 2006-12-15 | 2010-06-29 | Spansion Llc | Methods and systems for memory devices |
| US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
| JP5112217B2 (ja) * | 2008-08-07 | 2013-01-09 | 三星電子株式会社 | 不揮発性半導体記憶装置のチップ消去方法 |
| US7986558B2 (en) * | 2008-12-02 | 2011-07-26 | Macronix International Co., Ltd. | Method of operating non-volatile memory cell and memory device utilizing the method |
| CN102568571B (zh) * | 2010-12-10 | 2016-03-09 | 华邦电子股份有限公司 | 或非门型快闪存储器与其过抹除验证与修复方法 |
| US9129700B2 (en) * | 2013-01-22 | 2015-09-08 | Freescale Semiconductor, Inc. | Systems and methods for adaptive soft programming for non-volatile memory using temperature sensor |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US31012A (en) * | 1861-01-01 | Caleb h | ||
| JPH07320488A (ja) * | 1994-05-19 | 1995-12-08 | Hitachi Ltd | 一括消去型不揮発性記憶装置とその消去方法 |
| KR980005016A (ko) * | 1996-06-29 | 1998-03-30 | 김주용 | 플래쉬 메모리 소자의 소거방법 |
| JP3211869B2 (ja) * | 1996-12-10 | 2001-09-25 | 日本電気株式会社 | 不揮発性半導体メモリの消去方法及び消去装置 |
| US6147904A (en) * | 1999-02-04 | 2000-11-14 | Tower Semiconductor Ltd. | Redundancy method and structure for 2-bit non-volatile memory cells |
| US6198662B1 (en) * | 1999-06-24 | 2001-03-06 | Amic Technology, Inc. | Circuit and method for pre-erasing/erasing flash memory array |
-
2002
- 2002-05-24 US US10/155,767 patent/US20030218913A1/en not_active Abandoned
-
2003
- 2003-04-22 EP EP03726431A patent/EP1518247B1/de not_active Expired - Lifetime
- 2003-04-22 CN CNB038118637A patent/CN100470679C/zh not_active Expired - Lifetime
- 2003-04-22 WO PCT/US2003/012636 patent/WO2003100790A1/en active IP Right Grant
- 2003-04-22 AU AU2003228669A patent/AU2003228669A1/en not_active Abandoned
- 2003-04-22 KR KR1020047018786A patent/KR100960352B1/ko not_active IP Right Cessation
- 2003-04-22 DE DE60303511T patent/DE60303511T2/de not_active Expired - Lifetime
- 2003-04-22 JP JP2004508353A patent/JP2005527061A/ja active Pending
- 2003-04-29 TW TW092109955A patent/TWI300566B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TW200307947A (en) | 2003-12-16 |
| EP1518247B1 (de) | 2006-02-08 |
| EP1518247A1 (de) | 2005-03-30 |
| JP2005527061A (ja) | 2005-09-08 |
| DE60303511T2 (de) | 2006-09-28 |
| CN100470679C (zh) | 2009-03-18 |
| AU2003228669A1 (en) | 2003-12-12 |
| TWI300566B (en) | 2008-09-01 |
| CN1656567A (zh) | 2005-08-17 |
| US20030218913A1 (en) | 2003-11-27 |
| KR100960352B1 (ko) | 2010-05-28 |
| WO2003100790A1 (en) | 2003-12-04 |
| KR20050008725A (ko) | 2005-01-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8327 | Change in the person/name/address of the patent owner |
Owner name: SPANSION LLC (N.D.GES.D. STAATES DELAWARE), SU, US |