DE60317796D1 - Schaltung für synchrone mirror-verzögerung (smd) und verfahren mit einem zähler und bidirektionale verzögerungsleitung mit verringerter grösse - Google Patents

Schaltung für synchrone mirror-verzögerung (smd) und verfahren mit einem zähler und bidirektionale verzögerungsleitung mit verringerter grösse

Info

Publication number
DE60317796D1
DE60317796D1 DE60317796T DE60317796T DE60317796D1 DE 60317796 D1 DE60317796 D1 DE 60317796D1 DE 60317796 T DE60317796 T DE 60317796T DE 60317796 T DE60317796 T DE 60317796T DE 60317796 D1 DE60317796 D1 DE 60317796D1
Authority
DE
Germany
Prior art keywords
delay
smd
circuit
clock signal
input clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60317796T
Other languages
English (en)
Other versions
DE60317796T2 (de
Inventor
Howard C Kirsch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE60317796D1 publication Critical patent/DE60317796D1/de
Application granted granted Critical
Publication of DE60317796T2 publication Critical patent/DE60317796T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
DE60317796T 2002-06-20 2003-06-19 Synchrone Spiegelverzögerungseinrichtung (SMD) und Verfahren mit einem Zähler und bidirektionale Verzögerungsleitung mit verringerter Grösse Expired - Lifetime DE60317796T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/176,865 US6621316B1 (en) 2002-06-20 2002-06-20 Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line
US176865 2002-06-20
PCT/US2003/019426 WO2004001972A1 (en) 2002-06-20 2003-06-19 Synchronous mirror delay (smd) circuit and method including a counter and reduced size bi-directional delay line

Publications (2)

Publication Number Publication Date
DE60317796D1 true DE60317796D1 (de) 2008-01-10
DE60317796T2 DE60317796T2 (de) 2008-10-30

Family

ID=27804701

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60317796T Expired - Lifetime DE60317796T2 (de) 2002-06-20 2003-06-19 Synchrone Spiegelverzögerungseinrichtung (SMD) und Verfahren mit einem Zähler und bidirektionale Verzögerungsleitung mit verringerter Grösse

Country Status (9)

Country Link
US (2) US6621316B1 (de)
EP (1) EP1532737B1 (de)
KR (1) KR100847429B1 (de)
CN (1) CN100542036C (de)
AT (1) ATE379878T1 (de)
AU (1) AU2003245594A1 (de)
DE (1) DE60317796T2 (de)
TW (1) TWI324446B (de)
WO (1) WO2004001972A1 (de)

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US9356769B2 (en) * 2014-09-24 2016-05-31 Qualcomm Incorporated Synchronous reset and phase detecting for interchain local oscillator (LO) divider phase alignment
US20170207777A1 (en) * 2016-01-15 2017-07-20 Macronix International Co., Ltd. Integrated circuit device and delay circuit device having varied delay time structure
KR20180119071A (ko) * 2017-04-24 2018-11-01 에스케이하이닉스 주식회사 전자장치
US10148269B1 (en) 2017-07-24 2018-12-04 Micron Technology, Inc. Dynamic termination edge control
US10153014B1 (en) * 2017-08-17 2018-12-11 Micron Technology, Inc. DQS-offset and read-RTT-disable edge control
CN107622600B (zh) * 2017-09-21 2020-08-18 深圳怡化电脑股份有限公司 图像镜像数据的生成方法、装置及自动柜员机
TWI685200B (zh) 2018-08-10 2020-02-11 華邦電子股份有限公司 同步鏡延遲電路和同步鏡延遲操作方法
US10841525B1 (en) * 2019-08-23 2020-11-17 Omnivision Technologies, Inc. Image data readout circuit with shared data bus

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Also Published As

Publication number Publication date
ATE379878T1 (de) 2007-12-15
US20030234673A1 (en) 2003-12-25
TWI324446B (en) 2010-05-01
KR100847429B1 (ko) 2008-07-21
EP1532737B1 (de) 2007-11-28
TW200418268A (en) 2004-09-16
US6621316B1 (en) 2003-09-16
EP1532737A4 (de) 2005-11-16
CN1675838A (zh) 2005-09-28
AU2003245594A1 (en) 2004-01-06
KR20050024413A (ko) 2005-03-10
WO2004001972A1 (en) 2003-12-31
CN100542036C (zh) 2009-09-16
DE60317796T2 (de) 2008-10-30
EP1532737A1 (de) 2005-05-25
US6924686B2 (en) 2005-08-02

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