DE60328520D1 - Verfahren und methode zur steuerung der adressbus-spannungsversorgung - Google Patents

Verfahren und methode zur steuerung der adressbus-spannungsversorgung

Info

Publication number
DE60328520D1
DE60328520D1 DE60328520T DE60328520T DE60328520D1 DE 60328520 D1 DE60328520 D1 DE 60328520D1 DE 60328520 T DE60328520 T DE 60328520T DE 60328520 T DE60328520 T DE 60328520T DE 60328520 D1 DE60328520 D1 DE 60328520D1
Authority
DE
Germany
Prior art keywords
sense amplifiers
data
address
response
asserted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60328520T
Other languages
English (en)
Inventor
Tsvika Kurts
Doron Orenstien
Marcelo Yuffe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/317,798 external-priority patent/US7216240B2/en
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE60328520D1 publication Critical patent/DE60328520D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3253—Power saving in bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
DE60328520T 2002-12-11 2003-11-24 Verfahren und methode zur steuerung der adressbus-spannungsversorgung Expired - Lifetime DE60328520D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/317,798 US7216240B2 (en) 2002-12-11 2002-12-11 Apparatus and method for address bus power control
US10/436,903 US20040128416A1 (en) 2002-12-11 2003-05-12 Apparatus and method for address bus power control
PCT/US2003/037614 WO2004053706A2 (en) 2002-12-11 2003-11-24 An apparatus and method for address bus power control

Publications (1)

Publication Number Publication Date
DE60328520D1 true DE60328520D1 (de) 2009-09-03

Family

ID=32511034

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60328520T Expired - Lifetime DE60328520D1 (de) 2002-12-11 2003-11-24 Verfahren und methode zur steuerung der adressbus-spannungsversorgung

Country Status (11)

Country Link
US (1) US20040128416A1 (de)
EP (2) EP2109029B1 (de)
JP (1) JP4813180B2 (de)
KR (1) KR100737549B1 (de)
CN (1) CN100422905C (de)
AT (1) ATE437394T1 (de)
AU (1) AU2003293030A1 (de)
DE (1) DE60328520D1 (de)
HK (1) HK1075949A1 (de)
TW (1) TWI310910B (de)
WO (1) WO2004053706A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7000065B2 (en) 2002-01-02 2006-02-14 Intel Corporation Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers
US7484016B2 (en) * 2004-06-30 2009-01-27 Intel Corporation Apparatus and method for high performance volatile disk drive memory access using an integrated DMA engine
US7822978B2 (en) * 2005-07-22 2010-10-26 Intel Corporation Quiescing a manageability engine
US7870407B2 (en) * 2007-05-18 2011-01-11 Advanced Micro Devices, Inc. Dynamic processor power management device and method thereof
US7477178B1 (en) * 2007-06-30 2009-01-13 Cirrus Logic, Inc. Power-optimized analog-to-digital converter (ADC) input circuit
US8581756B1 (en) 2012-09-27 2013-11-12 Cirrus Logic, Inc. Signal-characteristic determined digital-to-analog converter (DAC) filter stage configuration
US11138348B2 (en) * 2018-10-09 2021-10-05 Intel Corporation Heterogeneous compute architecture hardware/software co-design for autonomous driving

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4202045A (en) * 1979-03-05 1980-05-06 Motorola, Inc. Write circuit for a read/write memory
JPH0715674B2 (ja) * 1986-01-20 1995-02-22 日本電気株式会社 マイクロコンピユ−タ
JPH0812756B2 (ja) * 1987-06-22 1996-02-07 松下電子工業株式会社 スタチックｒａｍ回路
US5432944A (en) * 1991-08-05 1995-07-11 Motorola, Inc. Data processing system having a dynamically enabled input synchronizer for selectively minimizing power consumption
US5327394A (en) * 1992-02-04 1994-07-05 Micron Technology, Inc. Timing and control circuit for a static RAM responsive to an address transition pulse
US5430683A (en) * 1994-03-15 1995-07-04 Intel Corporation Method and apparatus for reducing power in on-chip tag SRAM
US5692202A (en) * 1995-12-29 1997-11-25 Intel Corporation System, apparatus, and method for managing power in a computer system
US5911153A (en) * 1996-10-03 1999-06-08 International Business Machines Corporation Memory design which facilitates incremental fetch and store requests off applied base address requests
US5848428A (en) * 1996-12-19 1998-12-08 Compaq Computer Corporation Sense amplifier decoding in a memory device to reduce power consumption
US6141765A (en) * 1997-05-19 2000-10-31 Gigabus, Inc. Low power, high speed communications bus
US6243817B1 (en) * 1997-12-22 2001-06-05 Compaq Computer Corporation Device and method for dynamically reducing power consumption within input buffers of a bus interface unit
US6330679B1 (en) 1997-12-31 2001-12-11 Intel Corporation Input buffer circuit with dual power down functions
JPH11212687A (ja) * 1998-01-26 1999-08-06 Fujitsu Ltd バス制御装置
US6058059A (en) * 1999-08-30 2000-05-02 United Microelectronics Corp. Sense/output circuit for a semiconductor memory device
JP4216415B2 (ja) * 1999-08-31 2009-01-28 株式会社ルネサステクノロジ 半導体装置
JP2001167580A (ja) * 1999-12-07 2001-06-22 Toshiba Corp 半導体記憶装置
US6609171B1 (en) * 1999-12-29 2003-08-19 Intel Corporation Quad pumped bus architecture and protocol
KR100546184B1 (ko) * 2000-10-20 2006-01-24 주식회사 하이닉스반도체 센스 앰프 회로
US7000065B2 (en) * 2002-01-02 2006-02-14 Intel Corporation Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers
US6961787B2 (en) * 2002-01-07 2005-11-01 Intel Corporation Method and apparatus for updating task files
US7152167B2 (en) * 2002-12-11 2006-12-19 Intel Corporation Apparatus and method for data bus power control

Also Published As

Publication number Publication date
EP1570335A2 (de) 2005-09-07
KR20050085590A (ko) 2005-08-29
JP4813180B2 (ja) 2011-11-09
EP1570335B1 (de) 2009-07-22
WO2004053706A3 (en) 2004-11-18
US20040128416A1 (en) 2004-07-01
TWI310910B (en) 2009-06-11
CN100422905C (zh) 2008-10-01
JP2006511897A (ja) 2006-04-06
AU2003293030A8 (en) 2004-06-30
CN1726451A (zh) 2006-01-25
WO2004053706A2 (en) 2004-06-24
HK1075949A1 (en) 2005-12-30
EP2109029A1 (de) 2009-10-14
ATE437394T1 (de) 2009-08-15
EP2109029B1 (de) 2012-12-26
AU2003293030A1 (en) 2004-06-30
TW200428279A (en) 2004-12-16
KR100737549B1 (ko) 2007-07-10

Similar Documents

Publication Publication Date Title
ATE481672T1 (de) Verfahren zum aufrechterhalten eines usb- aktivzustands ohne datentransfer
HK1075949A1 (en) An apparatus and method for address bus power control
NL1024869A1 (nl) Werkwijze en systeem voor het meten van voor ziekte relevante weefselveranderingen.
ATE260272T1 (de) Beta-aminsäure-derivate zur verwendung als matrix-metalloproteasen- und tna-alpha-inhibitoren
DE602004024499D1 (de) Speichersteuerung, die Prozessorenergiezustände berücksichtigt
ITRM20040396A1 (it) Sistema distribuito per l'alimentazione elettrica di bus di potenza e metodo di controllo della potenza utilizzante tale sistema.
TW200705165A (en) System and method of coherent data transfer during processor idle states
MY143407A (en) Indazole derivatives as inhibitors of hormone sensitive lipase
EP1628623A4 (de) Verfahren zur behandlung von erkrankungen mit hsp90-hemmenden mitteln in kombination mit enzymhemmern
NO20044279L (no) 5-{2-hydroksy-3-[1-(3-trifluormetylfenyl)-syklopropyl]-propionylamino} ftalid og beslektede forbindelser med progesteronreseptormodulerende aktivitet for anvendelse i fertilitetskontroll og harmonerstatningsterapi
TW200602852A (en) Real-time debug support for a DMA device and method thereof
D'Addario et al. Ethanol and acetaldehyde exposure induces specific epigenetic modifications in the prodynorphin gene promoter in a human neuroblastoma cell line
DE60322664D1 (de) Verfahren und sytem zur überwachung des dma-zustandes in einem rechnersystem
DE602004014169D1 (de) Prozessor-surrogat zur verwendung in mehrprozessor-systemen und mehrprozessor-system damit
ATE379812T1 (de) Neuadressierbare virtuelle dma-steuer und statusregister
ATE554438T1 (de) Vorrichtung und verfahren zur datenbusleistungssteuerung
GB2432944A (en) Implementing bufferless DMA controllers using split transactions
DE60315190D1 (de) Vorladevorschlag
ATE397247T1 (de) Mikroprozessor und verfahren zur anweisungsausrichtung
ATE363690T1 (de) Methode und vorrichtung welche einen externen zugriff zu internen konfigurationsregistern erlauben
DE602004018264D1 (de) Intelligente Spindel zum Festziehen mit integriertem Messwertaufnehmer, Servoverstärker und Datenverarbeitungsanlage
ATE478384T1 (de) Datenübertragungsvorrichtung, anfrageausgabeeinheit und anfrageausgabeverfahren
ATE477533T1 (de) Polymorphismus zur laufzeit
TW200629144A (en) System and method for specifying an immediate value in an instruction
FR2875319B1 (fr) Systeme et calculateur embarque permettant la mise en suspens du dechargement de donnees en cas d'arret du calculateur

Legal Events

Date Code Title Description
8364 No opposition during term of opposition