DE60331081D1 - Nicht-sequentielle dram-folgesteuerung - Google Patents

Nicht-sequentielle dram-folgesteuerung

Info

Publication number
DE60331081D1
DE60331081D1 DE60331081T DE60331081T DE60331081D1 DE 60331081 D1 DE60331081 D1 DE 60331081D1 DE 60331081 T DE60331081 T DE 60331081T DE 60331081 T DE60331081 T DE 60331081T DE 60331081 D1 DE60331081 D1 DE 60331081D1
Authority
DE
Germany
Prior art keywords
requests
memory
memory access
access requests
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60331081T
Other languages
English (en)
Inventor
Joseph M Jeddeloh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of DE60331081D1 publication Critical patent/DE60331081D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659Command handling arrangements, e.g. command buffers, queues, command scheduling
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14Protection against unauthorised use of memory or access to memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • G06F3/0613Improving I/O performance in relation to throughput
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0674Disk device
    • G06F3/0676Magnetic disk device
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656Data buffering arrangements
DE60331081T 2002-05-14 2003-05-14 Nicht-sequentielle dram-folgesteuerung Expired - Lifetime DE60331081D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/143,896 US7149857B2 (en) 2002-05-14 2002-05-14 Out of order DRAM sequencer
PCT/US2003/015184 WO2003098392A2 (en) 2002-05-14 2003-05-14 Out of order dram sequencer

Publications (1)

Publication Number Publication Date
DE60331081D1 true DE60331081D1 (de) 2010-03-11

Family

ID=29418478

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60331081T Expired - Lifetime DE60331081D1 (de) 2002-05-14 2003-05-14 Nicht-sequentielle dram-folgesteuerung

Country Status (9)

Country Link
US (4) US7149857B2 (de)
EP (1) EP1540485B1 (de)
JP (2) JP2005525652A (de)
KR (2) KR100724557B1 (de)
CN (1) CN100527107C (de)
AT (1) ATE456094T1 (de)
AU (1) AU2003232136A1 (de)
DE (1) DE60331081D1 (de)
WO (1) WO2003098392A2 (de)

Families Citing this family (96)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6694490B2 (en) * 2002-07-10 2004-02-17 Hewlett-Packard Development Company, L.P. DIMM and method for producing a DIMM
US7660998B2 (en) 2002-12-02 2010-02-09 Silverbrook Research Pty Ltd Relatively unique ID in integrated circuit
US7418706B1 (en) * 2003-05-08 2008-08-26 Teradota Us, Inc. Rescheduling table scan transactions
US7240141B2 (en) * 2004-04-09 2007-07-03 Broadcom Corporation Programmable inter-virtual channel and intra-virtual channel instructions issuing rules for an I/O bus of a system-on-a-chip processor
US20060026371A1 (en) * 2004-07-30 2006-02-02 Chrysos George Z Method and apparatus for implementing memory order models with order vectors
US7451282B2 (en) * 2005-03-09 2008-11-11 Dolphin Interconnect Solutions North America Inc. System and method for storing a sequential data stream
US9286198B2 (en) 2005-04-21 2016-03-15 Violin Memory Method and system for storage of data in non-volatile media
US8452929B2 (en) * 2005-04-21 2013-05-28 Violin Memory Inc. Method and system for storage of data in non-volatile media
US9384818B2 (en) 2005-04-21 2016-07-05 Violin Memory Memory power management
US8200887B2 (en) 2007-03-29 2012-06-12 Violin Memory, Inc. Memory management system and method
US8028186B2 (en) * 2006-10-23 2011-09-27 Violin Memory, Inc. Skew management in an interconnection system
US8019940B2 (en) 2006-12-06 2011-09-13 Fusion-Io, Inc. Apparatus, system, and method for a front-end, distributed raid
US8265169B2 (en) * 2006-12-29 2012-09-11 Intel Corporation Video block memory read request translation and tagging
US8028257B2 (en) * 2007-03-01 2011-09-27 International Business Machines Corporation Structure for data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode
US9632870B2 (en) * 2007-03-29 2017-04-25 Violin Memory, Inc. Memory system with multiple striping of raid groups and method for performing the same
US11010076B2 (en) 2007-03-29 2021-05-18 Violin Systems Llc Memory system with multiple striping of raid groups and method for performing the same
US8015375B1 (en) 2007-03-30 2011-09-06 Emc Corporation Methods, systems, and computer program products for parallel processing and saving tracking information for multiple write requests in a data replication environment including multiple storage devices
US7996599B2 (en) 2007-04-25 2011-08-09 Apple Inc. Command resequencing in memory operations
US7925796B1 (en) 2007-05-03 2011-04-12 Emc Corporation Methods, systems, and computer program products for performing an input/output (I/O) operation that includes a virtual drain
US8145976B1 (en) 2007-05-14 2012-03-27 Marvell International Ltd. Error correcting
US8001338B2 (en) * 2007-08-21 2011-08-16 Microsoft Corporation Multi-level DRAM controller to manage access to DRAM
US7870351B2 (en) * 2007-11-15 2011-01-11 Micron Technology, Inc. System, apparatus, and method for modifying the order of memory accesses
US7836226B2 (en) 2007-12-06 2010-11-16 Fusion-Io, Inc. Apparatus, system, and method for coordinating storage requests in a multi-processor/multi-thread environment
US8156415B1 (en) * 2007-12-26 2012-04-10 Marvell International Ltd. Method and system for command queuing in disk drives
US8180975B2 (en) * 2008-02-26 2012-05-15 Microsoft Corporation Controlling interference in shared memory systems using parallelism-aware batch scheduling
CN101520749B (zh) * 2008-02-29 2012-08-29 瑞昱半导体股份有限公司 管理存储器的方法
US8370717B1 (en) 2008-04-08 2013-02-05 Marvell International Ltd. Method and apparatus for flexible buffers in an XOR engine
EP2283485A1 (de) * 2008-05-21 2011-02-16 Nxp B.V. Datenhandhabungssystem mit neuanordnungsnetzwerk
CN101727398B (zh) * 2008-10-31 2012-07-11 西安奇维测控科技有限公司 经信息序列化实现闪存控制器管理数据存储与还原的方法
US8601205B1 (en) * 2008-12-31 2013-12-03 Synopsys, Inc. Dynamic random access memory controller
JP2010182092A (ja) * 2009-02-05 2010-08-19 Mitsubishi Electric Corp バス装置
KR101581679B1 (ko) * 2009-03-18 2015-12-31 삼성전자주식회사 저장 장치 및 저장 장치의 버퍼 메모리 관리 방법
US8199759B2 (en) * 2009-05-29 2012-06-12 Intel Corporation Method and apparatus for enabling ID based streams over PCI express
WO2010144587A2 (en) 2009-06-12 2010-12-16 Violin Memory, Inc. Memory system having persistent garbage collection
EP2465027B1 (de) * 2009-08-11 2019-03-20 Marvell World Trade Ltd. Steuerung zum lesen von daten aus einem nichtflüchtigen speicher
US8644140B2 (en) * 2009-09-09 2014-02-04 Mellanox Technologies Ltd. Data switch with shared port buffers
CN102253917B (zh) * 2010-05-19 2014-03-19 联芯科技有限公司 一种spi控制器及数据发送方法
KR101121902B1 (ko) * 2010-06-22 2012-03-20 성균관대학교산학협력단 변경된 메모리 주소를 추적하는 트랜잭션 메모리 시스템 및 방법
US9021192B1 (en) * 2010-09-21 2015-04-28 Western Digital Technologies, Inc. System and method for enhancing processing of memory access requests
US8699491B2 (en) * 2011-07-25 2014-04-15 Mellanox Technologies Ltd. Network element with shared buffers
JP5704012B2 (ja) * 2011-08-01 2015-04-22 富士通セミコンダクター株式会社 プロセッサ、及びプロセッサの制御方法
KR101292309B1 (ko) * 2011-12-27 2013-07-31 숭실대학교산학협력단 반도체칩 및 메모리 제어방법, 그리고 그 방법을 컴퓨터에서 실행시키기 위한 프로그램을 기록한 기록매체
CN102567246B (zh) * 2011-12-29 2014-08-13 中国人民解放军国防科学技术大学 一种支持操作乱序执行的与非型快闪存储控制器
KR101721273B1 (ko) * 2012-01-16 2017-03-29 한국전자통신연구원 Sdio 인터페이스를 사용한 비순차적 데이터 전송 장치 및 방법
US20130185491A1 (en) * 2012-01-17 2013-07-18 Skymedi Corporation Memory controller and a method thereof
US9251086B2 (en) 2012-01-24 2016-02-02 SanDisk Technologies, Inc. Apparatus, system, and method for managing a cache
US9348775B2 (en) 2012-03-16 2016-05-24 Analog Devices, Inc. Out-of-order execution of bus transactions
US8775762B2 (en) * 2012-05-07 2014-07-08 Advanced Micro Devices, Inc. Method and apparatus for batching memory requests
KR20140028618A (ko) * 2012-08-29 2014-03-10 삼성전자주식회사 쓰기 페일을 줄이는 메모리 장치, 이를 포함하는 메모리 시스템 및 그 쓰기 방법
US9047092B2 (en) * 2012-12-21 2015-06-02 Arm Limited Resource management within a load store unit
US9582440B2 (en) 2013-02-10 2017-02-28 Mellanox Technologies Ltd. Credit based low-latency arbitration with data transfer
US8989011B2 (en) 2013-03-14 2015-03-24 Mellanox Technologies Ltd. Communication over multiple virtual lanes using a shared buffer
WO2014178846A1 (en) * 2013-04-30 2014-11-06 Hewlett-Packard Development Company, L.P. Coalescing memory access requests
KR102120823B1 (ko) 2013-08-14 2020-06-09 삼성전자주식회사 비휘발성 메모리 장치의 독출 시퀀스 제어 방법 및 이를 수행하는 메모리 시스템
US9641465B1 (en) 2013-08-22 2017-05-02 Mellanox Technologies, Ltd Packet switch with reduced latency
US9548960B2 (en) 2013-10-06 2017-01-17 Mellanox Technologies Ltd. Simplified packet routing
US20150199134A1 (en) * 2014-01-10 2015-07-16 Qualcomm Incorporated System and method for resolving dram page conflicts based on memory access patterns
US9325641B2 (en) 2014-03-13 2016-04-26 Mellanox Technologies Ltd. Buffering schemes for communication over long haul links
US9875185B2 (en) * 2014-07-09 2018-01-23 Intel Corporation Memory sequencing with coherent and non-coherent sub-systems
US9584429B2 (en) 2014-07-21 2017-02-28 Mellanox Technologies Ltd. Credit based flow control for long-haul links
US9569119B2 (en) * 2014-09-04 2017-02-14 National Instruments Corporation Self-addressing memory
GB2550829B (en) 2014-10-14 2021-09-22 Advanced Risc Mach Ltd Transaction response modification within interconnect circuitry
KR20160049200A (ko) * 2014-10-27 2016-05-09 삼성전자주식회사 데이터 저장 장치의 작동 방법, 이를 포함하는 모바일 컴퓨팅 장치, 및 이의 작동 방법
CN104375963B (zh) * 2014-11-28 2019-03-15 上海兆芯集成电路有限公司 基于缓存一致性的控制系统和方法
US9740646B2 (en) * 2014-12-20 2017-08-22 Intel Corporation Early identification in transactional buffered memory
EP3126998A4 (de) * 2015-02-26 2017-11-29 Strato Scale Ltd. Reihungsschemata für netzwerk- und speicher-e/a-anforderungen zur minimierung der arbeitslaststillzeit und interferenz zwischen arbeitslasten
GB2539435B8 (en) * 2015-06-16 2018-02-21 Advanced Risc Mach Ltd Data processing memory access control, in which an owning process for a region of memory is specified independently of privilege level
JP2017027479A (ja) * 2015-07-24 2017-02-02 富士通株式会社 データ読出し方法及び情報処理システム
CN111475438B (zh) * 2015-08-12 2021-12-10 北京忆恒创源科技股份有限公司 提供服务质量的io请求处理方法及其装置
JP2017204170A (ja) * 2016-05-12 2017-11-16 キヤノン株式会社 画像処理装置及び画像処理方法
GB2551351B (en) * 2016-06-14 2019-05-08 Imagination Tech Ltd Executing memory requests out of order
US10353819B2 (en) * 2016-06-24 2019-07-16 Qualcomm Incorporated Next line prefetchers employing initial high prefetch prediction confidence states for throttling next line prefetches in a processor-based system
JP6992750B2 (ja) * 2016-06-29 2022-01-13 ソニーグループ株式会社 メモリコントローラ、メモリシステムおよび情報処理システム
KR20180069960A (ko) * 2016-12-15 2018-06-26 에스케이하이닉스 주식회사 메모리 시스템 및 그의 동작 방법
KR20180090039A (ko) * 2017-02-02 2018-08-10 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
JP2018205859A (ja) * 2017-05-31 2018-12-27 キヤノン株式会社 メモリコントローラとその制御方法
CN107770620B (zh) * 2017-09-21 2020-10-30 广州视源电子科技股份有限公司 请求信息响应方法、系统及可读存储介质
US10425456B2 (en) 2017-11-29 2019-09-24 Bank Of America Corporation Request processing system using a splitting engine
US10419265B2 (en) 2017-11-29 2019-09-17 Bank Of America Corporation Request processing system using a combining engine
CN108335719A (zh) * 2018-02-24 2018-07-27 上海兆芯集成电路有限公司 性能评估装置及性能评估方法
US11874782B1 (en) * 2018-07-20 2024-01-16 Robert Gezelter Fast mass storage access for digital computers
CN109683963A (zh) * 2018-12-10 2019-04-26 深圳忆联信息系统有限公司 基于多命令输入的重排序输出方法、装置和计算机设备
TWI701554B (zh) * 2018-12-13 2020-08-11 英屬維京群島商鯨鏈先進股份有限公司 適用於雜湊演算法的電路系統
US10951549B2 (en) 2019-03-07 2021-03-16 Mellanox Technologies Tlv Ltd. Reusing switch ports for external buffer network
CN110046053B (zh) 2019-04-19 2021-11-12 上海兆芯集成电路有限公司 用以分配任务的处理系统及其访存方法
CN110032453B (zh) 2019-04-19 2022-05-03 上海兆芯集成电路有限公司 用以任务调度与分配的处理系统及其加速方法
CN110083387B (zh) 2019-04-19 2021-11-12 上海兆芯集成电路有限公司 使用轮询机制的处理系统及其访存方法
CN110083388B (zh) * 2019-04-19 2021-11-12 上海兆芯集成电路有限公司 用于调度的处理系统及其访存方法
CN110058931B (zh) 2019-04-19 2022-03-22 上海兆芯集成电路有限公司 用以任务调度的处理系统及其加速方法
US11093404B2 (en) * 2019-10-14 2021-08-17 EMC IP Holding Company LLC Efficient pre-fetching on a storage system
GB2588618B (en) * 2019-10-29 2022-04-20 Advanced Risc Mach Ltd Methods and apparatus for issuing memory access commands
US11481152B2 (en) * 2019-12-30 2022-10-25 Micron Technology, Inc. Execution of commands addressed to a logical block
CN113377277A (zh) * 2020-03-09 2021-09-10 伊姆西Ip控股有限责任公司 管理存储器的方法、设备和计算机程序产品
US11727421B1 (en) 2020-09-21 2023-08-15 Cboe Exchange, Inc System and method for implementing a system execution delay in response to liquidity removal for resting orders
US11558316B2 (en) 2021-02-15 2023-01-17 Mellanox Technologies, Ltd. Zero-copy buffering of traffic of long-haul links
WO2022174367A1 (en) * 2021-02-18 2022-08-25 Micron Technology, Inc. Improved implicit ordered command handling

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3735354A (en) 1972-04-07 1973-05-22 Sperry Rand Corp Multiplexed memory request interface
JP3157507B2 (ja) * 1990-03-14 2001-04-16 日本電気株式会社 データ処理装置
US5537572A (en) 1992-03-31 1996-07-16 Vlsi Technology, Inc. Cache controller and method for dumping contents of a cache directory and cache data random access memory (RAM)
US5461718A (en) 1992-04-24 1995-10-24 Digital Equipment Corporation System for sequential read of memory stream buffer detecting page mode cycles availability fetching data into a selected FIFO, and sending data without aceessing memory
JP3010947B2 (ja) 1992-11-26 2000-02-21 日本電気株式会社 メモリアクセス制御装置
US5664153A (en) 1993-04-21 1997-09-02 Intel Corporation Page open/close scheme based on high order address bit and likelihood of page access
US5388247A (en) 1993-05-14 1995-02-07 Digital Equipment Corporation History buffer control to reduce unnecessary allocations in a memory stream buffer
US5630099A (en) 1993-12-10 1997-05-13 Advanced Micro Devices Non-volatile memory array controller capable of controlling memory banks having variable bit widths
US5638374A (en) * 1995-03-15 1997-06-10 Hughes Electronics Enhanced transaction reservation
US5701434A (en) 1995-03-16 1997-12-23 Hitachi, Ltd. Interleave memory controller with a common access queue
US5630096A (en) 1995-05-10 1997-05-13 Microunity Systems Engineering, Inc. Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order
US6204864B1 (en) 1995-06-07 2001-03-20 Seiko Epson Corporation Apparatus and method having improved memory controller request handler
US5692165A (en) 1995-09-12 1997-11-25 Micron Electronics Inc. Memory controller with low skew control signal
US5872822A (en) 1995-10-26 1999-02-16 Mcdata Corporation Method and apparatus for memory sequencing
US6061759A (en) 1996-02-09 2000-05-09 Apex Semiconductor, Inc. Hidden precharge pseudo cache DRAM
US5907863A (en) 1996-08-16 1999-05-25 Unisys Corporation Memory control unit using preloaded values to generate optimal timing of memory control sequences between different memory segments
US6272600B1 (en) * 1996-11-15 2001-08-07 Hyundai Electronics America Memory request reordering in a data processing system
JPH10191236A (ja) 1996-12-25 1998-07-21 Nec Corp 画像処理装置及び画像データメモリ配置方法
US5848025A (en) 1997-06-30 1998-12-08 Motorola, Inc. Method and apparatus for controlling a memory device in a page mode
US5983325A (en) 1997-12-09 1999-11-09 Advanced Micro Devices, Inc. Dataless touch to open a memory page
US6052134A (en) 1997-12-22 2000-04-18 Compaq Computer Corp. Memory controller and method for dynamic page management
US6052756A (en) 1998-01-23 2000-04-18 Oki Electric Industry Co., Ltd. Memory page management
US6295592B1 (en) 1998-07-31 2001-09-25 Micron Technology, Inc. Method of processing memory requests in a pipelined memory controller
US6434684B1 (en) 1998-09-03 2002-08-13 Micron Technology, Inc. Method and apparatus for coupling signals across different clock domains, and memory device and computer system using same
US6108795A (en) 1998-10-30 2000-08-22 Micron Technology, Inc. Method for aligning clock and data signals received from a RAM
US6212611B1 (en) * 1998-11-03 2001-04-03 Intel Corporation Method and apparatus for providing a pipelined memory controller
US6385708B1 (en) 1998-11-16 2002-05-07 Infineon Technologies Ag Using a timing-look-up-table and page timers to determine the time between two consecutive memory accesses
US6510474B1 (en) * 1998-11-16 2003-01-21 Infineon Technologies Ag Methods and apparatus for re-reordering command and data packets in order to restore an original order of out-of-order memory requests
US6212598B1 (en) 1998-11-30 2001-04-03 Micron Technology, Inc. Controlling a paging policy based on a requestor characteristic
US6295586B1 (en) 1998-12-04 2001-09-25 Advanced Micro Devices, Inc. Queue based memory controller
US6181638B1 (en) 1998-12-07 2001-01-30 Micron Technology, Inc. Method for receiving data from a synchronous random access memory
US6389529B1 (en) 1999-06-25 2002-05-14 International Business Machines Corporation Method for alternate preferred time delivery of load data
JP2001022529A (ja) * 1999-06-30 2001-01-26 Internatl Business Mach Corp <Ibm> ディスクドライブ装置及びその制御方法
US6330647B1 (en) 1999-08-31 2001-12-11 Micron Technology, Inc. Memory bandwidth allocation based on access count priority scheme
US6275913B1 (en) 1999-10-15 2001-08-14 Micron Technology, Inc. Method for preserving memory request ordering across multiple memory controllers
JP2001154913A (ja) * 1999-11-30 2001-06-08 Hitachi Ltd 主記憶制御装置
US6735677B1 (en) 2001-04-30 2004-05-11 Lsi Logic Corporation Parameterizable queued memory access system
US7242690B2 (en) 2002-03-05 2007-07-10 Hewlett-Packard Development Company, L.P. System for performing input processing on a data packet

Also Published As

Publication number Publication date
KR100724557B1 (ko) 2007-06-04
US8639902B2 (en) 2014-01-28
EP1540485B1 (de) 2010-01-20
WO2003098392A3 (en) 2005-04-21
US9904489B2 (en) 2018-02-27
US7620789B2 (en) 2009-11-17
JP2005525652A (ja) 2005-08-25
KR20050005481A (ko) 2005-01-13
ATE456094T1 (de) 2010-02-15
CN100527107C (zh) 2009-08-12
AU2003232136A1 (en) 2003-12-02
CN1669011A (zh) 2005-09-14
WO2003098392A2 (en) 2003-11-27
AU2003232136A8 (en) 2003-12-02
US20140223116A1 (en) 2014-08-07
US7149857B2 (en) 2006-12-12
EP1540485A2 (de) 2005-06-15
US20030217239A1 (en) 2003-11-20
US20100100670A1 (en) 2010-04-22
JP2008204487A (ja) 2008-09-04
US20070101075A1 (en) 2007-05-03
KR20060108357A (ko) 2006-10-17
JP4742116B2 (ja) 2011-08-10

Similar Documents

Publication Publication Date Title
DE60331081D1 (de) Nicht-sequentielle dram-folgesteuerung
US11237728B2 (en) Method for accessing extended memory, device, and system
WO2004055667A3 (en) System and method for data prefetching
ATE433584T1 (de) Verfahren, system und programm zur handhabung von eingabe-/ausgabebefehlen
WO2002073619A3 (en) System latency levelization for read data
TW200636482A (en) Predictive early write-back of owned cache blocks in a shared memory computer system
TW200513851A (en) Prefetch command control method, prefetch command control apparatus and cache memory control apparatus
WO2006026017A3 (en) Memory system and method having uni-directional data buses
AU3915300A (en) Arbitration methods and systems for arbitrating access to a disk controller memory
ATE444528T1 (de) Migrieren von daten, die einem zugang durch eingabe-/ausgabeeinrichtungen ausgesetzt sind
EP0772822B1 (de) Mikroprozessor mit pipeline-zugriffsanforderung zu einem externen speicher
AU2003294679A8 (en) Read-write switching method for a memory controller
DE69903630T2 (de) Mehrprozessorsystembrücke
TW200416535A (en) Method and apparatus for determining a dynamic random access memory page management implementation
DE60026836D1 (de) Anordnungen und verfahren für eine plattensteuerungspeicher architektur
EP1271543A3 (de) Vefahren und System zum schnellen Speicherzugriff
KR20130000963A (ko) 반도체 저장 시스템
DE50305302D1 (de) Speichersystem mit mehreren speichercontrollern and verfahren zu deren synchronisierung
JP2006185198A (ja) メモリアクセス制御回路
DE60118617D1 (de) Vorrichtung und verfahren zum pipeline-mehrfachspeicherzugriff
JP2006331252A (ja) バスブリッジ装置
JP2015014872A (ja) データ処理装置、データ処理方法およびプログラム
JP2007164388A (ja) バス調停方法及び装置及びプログラム
Rodriguez A contribution to the study of bus emulation (Spanish text)
SE9901743D0 (sv) Method and computer system for improved memory accessing by a DMA unit

Legal Events

Date Code Title Description
8364 No opposition during term of opposition