DE60333227D1 - Verfahren und vorrichtungen für verbesserten speicherzugriff - Google Patents

Verfahren und vorrichtungen für verbesserten speicherzugriff

Info

Publication number
DE60333227D1
DE60333227D1 DE60333227T DE60333227T DE60333227D1 DE 60333227 D1 DE60333227 D1 DE 60333227D1 DE 60333227 T DE60333227 T DE 60333227T DE 60333227 T DE60333227 T DE 60333227T DE 60333227 D1 DE60333227 D1 DE 60333227D1
Authority
DE
Germany
Prior art keywords
shift registers
data
sets
loaded
memory devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60333227T
Other languages
English (en)
Inventor
William T Lynch
David J Herbison
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RING TECHNOLOGY ENTPR S LLC
Original Assignee
RING TECHNOLOGY ENTPR S LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=32174817&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE60333227(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by RING TECHNOLOGY ENTPR S LLC filed Critical RING TECHNOLOGY ENTPR S LLC
Application granted granted Critical
Publication of DE60333227D1 publication Critical patent/DE60333227D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1036—Read-write modes for single port memories, i.e. having either a random port or a serial port using data shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C2029/3202—Scan chain
DE60333227T 2002-10-31 2003-10-23 Verfahren und vorrichtungen für verbesserten speicherzugriff Expired - Lifetime DE60333227D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/284,198 US6879526B2 (en) 2002-10-31 2002-10-31 Methods and apparatus for improved memory access
PCT/US2003/033679 WO2004042506A2 (en) 2002-10-31 2003-10-23 Methods and apparatus for improved memory access

Publications (1)

Publication Number Publication Date
DE60333227D1 true DE60333227D1 (de) 2010-08-12

Family

ID=32174817

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60333227T Expired - Lifetime DE60333227D1 (de) 2002-10-31 2003-10-23 Verfahren und vorrichtungen für verbesserten speicherzugriff

Country Status (8)

Country Link
US (3) US6879526B2 (de)
EP (1) EP1576445B1 (de)
JP (1) JP2006505066A (de)
KR (1) KR100994393B1 (de)
AT (1) ATE472802T1 (de)
AU (1) AU2003301774A1 (de)
DE (1) DE60333227D1 (de)
WO (1) WO2004042506A2 (de)

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Also Published As

Publication number Publication date
JP2006505066A (ja) 2006-02-09
US6879526B2 (en) 2005-04-12
US20040085818A1 (en) 2004-05-06
EP1576445A4 (de) 2006-08-16
AU2003301774A1 (en) 2004-06-07
AU2003301774A8 (en) 2004-06-07
EP1576445A2 (de) 2005-09-21
KR100994393B1 (ko) 2010-11-16
WO2004042506A2 (en) 2004-05-21
US7313035B2 (en) 2007-12-25
WO2004042506A3 (en) 2005-09-09
EP1576445B1 (de) 2010-06-30
US20050128823A1 (en) 2005-06-16
KR20050062781A (ko) 2005-06-27
US20070237009A1 (en) 2007-10-11
ATE472802T1 (de) 2010-07-15
US7808844B2 (en) 2010-10-05

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