DE68918469T2 - Serieller Lesezugriff von seriellen Speichern mit einer durch den Benutzer definierten Startadresse. - Google Patents
Serieller Lesezugriff von seriellen Speichern mit einer durch den Benutzer definierten Startadresse.Info
- Publication number
- DE68918469T2 DE68918469T2 DE68918469T DE68918469T DE68918469T2 DE 68918469 T2 DE68918469 T2 DE 68918469T2 DE 68918469 T DE68918469 T DE 68918469T DE 68918469 T DE68918469 T DE 68918469T DE 68918469 T2 DE68918469 T2 DE 68918469T2
- Authority
- DE
- Germany
- Prior art keywords
- serial
- user
- start address
- read access
- address defined
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/149,399 US4873671A (en) | 1988-01-28 | 1988-01-28 | Sequential read access of serial memories with a user defined starting address |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68918469D1 DE68918469D1 (de) | 1994-11-03 |
DE68918469T2 true DE68918469T2 (de) | 1995-04-20 |
Family
ID=22530107
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68918469T Expired - Lifetime DE68918469T2 (de) | 1988-01-28 | 1989-01-21 | Serieller Lesezugriff von seriellen Speichern mit einer durch den Benutzer definierten Startadresse. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4873671A (de) |
EP (1) | EP0326885B1 (de) |
JP (1) | JPH02257494A (de) |
CA (1) | CA1332470C (de) |
DE (1) | DE68918469T2 (de) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR950009681B1 (ko) * | 1988-06-30 | 1995-08-26 | 금성일렉트론주식회사 | 순서 선택 우선의 임의/순서 선택회로 |
JPH0221499A (ja) * | 1988-07-07 | 1990-01-24 | Toshiba Corp | サンプルホールド回路 |
KR910005615B1 (ko) * | 1988-07-18 | 1991-07-31 | 삼성전자 주식회사 | 프로그래머블 순차코오드 인식회로 |
JPH0776906B2 (ja) * | 1989-06-30 | 1995-08-16 | ディジタル イクイプメント コーポレーション | 分類加速装置のための速度及びメモリー制御 |
IL96808A (en) | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
US6324120B2 (en) | 1990-04-18 | 2001-11-27 | Rambus Inc. | Memory device having a variable data output length |
US6751696B2 (en) | 1990-04-18 | 2004-06-15 | Rambus Inc. | Memory device having a programmable register |
US5036489A (en) * | 1990-04-27 | 1991-07-30 | Codex Corp. | Compact expandable folded first-in-first-out queue |
US5088061A (en) * | 1990-07-24 | 1992-02-11 | Vlsi Technology, Inc. | Routing independent circuit components |
JPH04147493A (ja) * | 1990-10-09 | 1992-05-20 | Mitsubishi Electric Corp | 半導体メモリ |
JP2596208B2 (ja) * | 1990-10-19 | 1997-04-02 | 日本電気株式会社 | メモリ装置 |
KR920007805Y1 (ko) * | 1991-02-09 | 1992-10-19 | 조규섭 | 볍씨 침종겸용 최아장치 |
US5297029A (en) * | 1991-12-19 | 1994-03-22 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
JP3390482B2 (ja) * | 1992-06-12 | 2003-03-24 | 株式会社リコー | ファクシミリ装置 |
US5687389A (en) * | 1993-12-22 | 1997-11-11 | Adaptec, Inc. | System for controlling an automatic read operation of read cache control circuit in a disk drive controller utilizing a start counter, a working counter, and a sector counter |
US5526316A (en) * | 1994-04-29 | 1996-06-11 | Winbond Electronics Corp. | Serial access memory device |
GB2289777B (en) * | 1994-05-17 | 1999-02-17 | Winbond Electronics Corp | Memory device with page select capability |
US5621692A (en) * | 1994-05-24 | 1997-04-15 | Winbond Electronics Corporation | Memory device with page select capability |
US5613158A (en) * | 1994-05-25 | 1997-03-18 | Tandem Computers, Inc. | System for specifying addresses by creating a multi-bit ranked ordered anchor pattern and creating next address by shifting in the direction of the superior position |
US5657287A (en) * | 1995-05-31 | 1997-08-12 | Micron Technology, Inc. | Enhanced multiple block writes to adjacent blocks of memory using a sequential counter |
US5657444A (en) * | 1995-08-03 | 1997-08-12 | National Semiconductor Corporation | Microprocessor with secure programmable read only memory circuit |
US5835502A (en) * | 1996-06-28 | 1998-11-10 | International Business Machines Corporation | Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme |
US5940345A (en) * | 1997-12-12 | 1999-08-17 | Cypress Semiconductor Corp. | Combinational logic feedback circuit to ensure correct power-on-reset of a four-bit synchronous shift register |
US6557051B1 (en) * | 2000-01-15 | 2003-04-29 | Cirrus Logic, Inc. | Throughput for a serial interface |
JP4081963B2 (ja) | 2000-06-30 | 2008-04-30 | セイコーエプソン株式会社 | 記憶装置および記憶装置に対するアクセス方法 |
KR100424178B1 (ko) * | 2001-09-20 | 2004-03-24 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 내부어드레스 발생회로 |
US20050143171A1 (en) * | 2003-12-30 | 2005-06-30 | Loose Timothy C. | Gaming machine having sampled software verification |
US7246252B1 (en) * | 2003-12-31 | 2007-07-17 | Xilinx, Inc. | Delay compensation |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5255446A (en) * | 1975-10-31 | 1977-05-06 | Toshiba Corp | Information transfer control system |
US4236255A (en) * | 1978-12-15 | 1980-11-25 | Interlake, Inc. | Rack entry vehicle communication system |
JPS5694589A (en) * | 1979-12-27 | 1981-07-31 | Nec Corp | Memory device |
JPS57117168A (en) * | 1981-01-08 | 1982-07-21 | Nec Corp | Memory circuit |
US4507760A (en) * | 1982-08-13 | 1985-03-26 | At&T Bell Laboratories | First-in, first-out (FIFO) memory configuration for queue storage |
JPS5956276A (ja) * | 1982-09-24 | 1984-03-31 | Hitachi Ltd | 半導体記憶装置 |
US4509142A (en) * | 1982-12-15 | 1985-04-02 | Texas Instruments Incorporated | Semiconductor memory device with pipeline access |
US4646270A (en) * | 1983-09-15 | 1987-02-24 | Motorola, Inc. | Video graphic dynamic RAM |
JPH081745B2 (ja) * | 1984-12-10 | 1996-01-10 | 日本電気株式会社 | シリアルアクセスメモリ |
GB8515482D0 (en) * | 1985-06-19 | 1985-07-24 | Int Computers Ltd | Search apparatus |
JPS6286949A (ja) * | 1985-10-11 | 1987-04-21 | Mitsubishi Electric Corp | デ−タ受信方式 |
GB2183374A (en) * | 1985-11-23 | 1987-06-03 | Stc Plc | Sequential access memory |
-
1988
- 1988-01-28 US US07/149,399 patent/US4873671A/en not_active Expired - Lifetime
-
1989
- 1989-01-21 EP EP89101064A patent/EP0326885B1/de not_active Expired - Lifetime
- 1989-01-21 DE DE68918469T patent/DE68918469T2/de not_active Expired - Lifetime
- 1989-01-27 CA CA000589315A patent/CA1332470C/en not_active Expired - Fee Related
- 1989-01-30 JP JP1017851A patent/JPH02257494A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
CA1332470C (en) | 1994-10-11 |
US4873671A (en) | 1989-10-10 |
EP0326885A3 (de) | 1992-05-13 |
EP0326885B1 (de) | 1994-09-28 |
JPH02257494A (ja) | 1990-10-18 |
EP0326885A2 (de) | 1989-08-09 |
DE68918469D1 (de) | 1994-11-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |