DE68925303T2 - Zellenstapel für Serien-Architektur mit variabler Ziffernbreite - Google Patents

Zellenstapel für Serien-Architektur mit variabler Ziffernbreite

Info

Publication number
DE68925303T2
DE68925303T2 DE68925303T DE68925303T DE68925303T2 DE 68925303 T2 DE68925303 T2 DE 68925303T2 DE 68925303 T DE68925303 T DE 68925303T DE 68925303 T DE68925303 T DE 68925303T DE 68925303 T2 DE68925303 T2 DE 68925303T2
Authority
DE
Germany
Prior art keywords
cell stack
series architecture
digit width
variable digit
variable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68925303T
Other languages
English (en)
Other versions
DE68925303D1 (de
Inventor
Peter Frank Corbett
Richard Ian Hartley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Harris Corp
Original Assignee
Harris Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harris Corp filed Critical Harris Corp
Publication of DE68925303D1 publication Critical patent/DE68925303D1/de
Application granted granted Critical
Publication of DE68925303T2 publication Critical patent/DE68925303T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
DE68925303T 1988-04-18 1989-04-17 Zellenstapel für Serien-Architektur mit variabler Ziffernbreite Expired - Fee Related DE68925303T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/182,602 US4951221A (en) 1988-04-18 1988-04-18 Cell stack for variable digit width serial architecture

Publications (2)

Publication Number Publication Date
DE68925303D1 DE68925303D1 (de) 1996-02-15
DE68925303T2 true DE68925303T2 (de) 1996-08-29

Family

ID=22669188

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68925303T Expired - Fee Related DE68925303T2 (de) 1988-04-18 1989-04-17 Zellenstapel für Serien-Architektur mit variabler Ziffernbreite

Country Status (4)

Country Link
US (1) US4951221A (de)
EP (1) EP0338757B1 (de)
JP (1) JPH0216631A (de)
DE (1) DE68925303T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5084834A (en) * 1988-04-18 1992-01-28 General Electric Company Digit-serial linear combining apparatus
US5283753A (en) * 1991-07-25 1994-02-01 Motorola, Inc. Firm function block for a programmable block architected heterogeneous integrated circuit
JP3479538B2 (ja) * 1991-12-26 2003-12-15 テキサス インスツルメンツ インコーポレイテツド 半導体集積回路を製作する方法
JP3224885B2 (ja) * 1993-01-14 2001-11-05 三菱電機株式会社 集積回路装置及びその設計方法
US5623684A (en) * 1994-05-17 1997-04-22 Commquest Technologies, Inc. Application specific processor architecture comprising pre-designed reconfigurable application elements interconnected via a bus with high-level statements controlling configuration and data routing
JP3599368B2 (ja) * 1994-05-20 2004-12-08 株式会社ルネサステクノロジ 並列処理マイクロプロセッサ
US5867400A (en) * 1995-05-17 1999-02-02 International Business Machines Corporation Application specific processor and design method for same
US5838583A (en) * 1996-04-12 1998-11-17 Cadence Design Systems, Inc. Optimized placement and routing of datapaths
US6090151A (en) * 1997-07-01 2000-07-18 Motorola, Inc. Electronic device parameter estimator and method therefor
US6230175B1 (en) 1997-11-11 2001-05-08 Matsushita Electric Industrial Co., Ltd. Reconfigurable digit-serial arithmetic system having a plurality of digit-serial arithmetic units
US6502231B1 (en) * 2001-05-31 2002-12-31 Applied Micro Circuits Corporation Integrated circuit template cell system and method
GB2376819A (en) * 2001-06-21 2002-12-24 Ericsson Telefon Ab L M Electronic circuit having series connected circuit blocks
JP2004153138A (ja) * 2002-10-31 2004-05-27 Renesas Technology Corp 半導体集積回路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4739474A (en) * 1983-03-10 1988-04-19 Martin Marietta Corporation Geometric-arithmetic parallel processor
US4584653A (en) * 1983-03-22 1986-04-22 Fujitsu Limited Method for manufacturing a gate array integrated circuit device
US4621339A (en) * 1983-06-13 1986-11-04 Duke University SIMD machine using cube connected cycles network architecture for vector processing
EP0182041A3 (de) * 1984-11-15 1988-08-03 International Business Machines Corporation Integrierter Schaltungschip mit "gestapeltem Bit" funktionellen Blöcken
US4701860A (en) * 1985-03-07 1987-10-20 Harris Corporation Integrated circuit architecture formed of parametric macro-cells
US4791590A (en) * 1985-11-19 1988-12-13 Cornell Research Foundation, Inc. High performance signal processor

Also Published As

Publication number Publication date
EP0338757A3 (de) 1992-01-15
EP0338757A2 (de) 1989-10-25
DE68925303D1 (de) 1996-02-15
JPH0216631A (ja) 1990-01-19
US4951221A (en) 1990-08-21
EP0338757B1 (de) 1996-01-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee