DE68926036D1 - Speicherkonfiguration zur Verwendung für Schnittstellenbildung zwischen einer Systemsteuereinheit für ein Multiprozessorsystem und dem Hauptspeicher - Google Patents

Speicherkonfiguration zur Verwendung für Schnittstellenbildung zwischen einer Systemsteuereinheit für ein Multiprozessorsystem und dem Hauptspeicher

Info

Publication number
DE68926036D1
DE68926036D1 DE68926036T DE68926036T DE68926036D1 DE 68926036 D1 DE68926036 D1 DE 68926036D1 DE 68926036 T DE68926036 T DE 68926036T DE 68926036 T DE68926036 T DE 68926036T DE 68926036 D1 DE68926036 D1 DE 68926036D1
Authority
DE
Germany
Prior art keywords
memory
scu
transfer
segments
cpus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68926036T
Other languages
English (en)
Other versions
DE68926036T2 (de
Inventor
John Lynch
Kumar Chinnaswamy
Michael A Gagliardo
James E Tessari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of DE68926036D1 publication Critical patent/DE68926036D1/de
Publication of DE68926036T2 publication Critical patent/DE68926036T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
DE68926036T 1989-02-03 1989-09-13 Speicherkonfiguration zur Verwendung für Schnittstellenbildung zwischen einer Systemsteuereinheit für ein Multiprozessorsystem und dem Hauptspeicher Expired - Fee Related DE68926036T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/306,404 US5043874A (en) 1989-02-03 1989-02-03 Memory configuration for use with means for interfacing a system control unit for a multi-processor system with the system main memory

Publications (2)

Publication Number Publication Date
DE68926036D1 true DE68926036D1 (de) 1996-04-25
DE68926036T2 DE68926036T2 (de) 1997-01-02

Family

ID=23185151

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68926036T Expired - Fee Related DE68926036T2 (de) 1989-02-03 1989-09-13 Speicherkonfiguration zur Verwendung für Schnittstellenbildung zwischen einer Systemsteuereinheit für ein Multiprozessorsystem und dem Hauptspeicher

Country Status (7)

Country Link
US (1) US5043874A (de)
EP (1) EP0380855B1 (de)
JP (1) JPH02208771A (de)
AT (1) ATE135833T1 (de)
AU (1) AU628528B2 (de)
CA (1) CA1323929C (de)
DE (1) DE68926036T2 (de)

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JP2672916B2 (ja) * 1991-12-13 1997-11-05 富士通株式会社 アレイディスク装置のデータチェック方法
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EP0613088A1 (de) * 1993-02-24 1994-08-31 Digital Equipment Corporation Verfahren zur Speicherverschachtelung und dadurch verschachtelte Speichersysteme
CA2118662C (en) * 1993-03-22 1999-07-13 Paul A. Santeler Memory controller having all dram address and control signals provided synchronously from a single device
US5377338A (en) * 1993-10-12 1994-12-27 Wang Laboratories, Inc. Apparatus and methods for reducing numbers of read-modify-write cycles to a memory, and for improving DMA efficiency
US5464435A (en) * 1994-02-03 1995-11-07 Medtronic, Inc. Parallel processors in implantable medical device
US5617534A (en) * 1994-02-16 1997-04-01 Intel Corporation Interface protocol for testing of a cache memory
US5696917A (en) * 1994-06-03 1997-12-09 Intel Corporation Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory
TW304254B (de) * 1994-07-08 1997-05-01 Hitachi Ltd
JPH10507023A (ja) * 1994-10-06 1998-07-07 ヴァーク・インコーポレイテッド 共用メモリシステム
US5590299A (en) * 1994-10-28 1996-12-31 Ast Research, Inc. Multiprocessor system bus protocol for optimized accessing of interleaved storage modules
US5596740A (en) * 1995-01-26 1997-01-21 Cyrix Corporation Interleaved memory conflict resolution with accesses of variable bank widths and partial return of non-conflicting banks
US5875470A (en) * 1995-09-28 1999-02-23 International Business Machines Corporation Multi-port multiple-simultaneous-access DRAM chip
US5663924A (en) * 1995-12-14 1997-09-02 International Business Machines Corporation Boundary independent bit decode for a SDRAM
US5761727A (en) * 1996-04-02 1998-06-02 United Microelectronics Corporation Control apparatus for a memory architecture using dedicated and shared memory segments
US6041379A (en) * 1996-10-04 2000-03-21 Northrop Grumman Corporation Processor interface for a distributed memory addressing system
US5946710A (en) * 1996-11-14 1999-08-31 Unisys Corporation Selectable two-way, four-way double cache interleave scheme
US5931938A (en) * 1996-12-12 1999-08-03 Sun Microsystems, Inc. Multiprocessor computer having configurable hardware system domains
US5960455A (en) * 1996-12-30 1999-09-28 Unisys Corporation Scalable cross bar type storage controller
US6216240B1 (en) * 1997-06-26 2001-04-10 Samsung Electronics Co., Ltd. Merged memory and logic (MML) integrated circuits including memory test controlling circuits and methods
US5872993A (en) * 1997-12-01 1999-02-16 Advanced Micro Devices, Inc. Communications system with multiple, simultaneous accesses to a memory
US6128307A (en) * 1997-12-01 2000-10-03 Advanced Micro Devices, Inc. Programmable data flow processor for performing data transfers
US6012136A (en) * 1997-12-01 2000-01-04 Advanced Micro Devices, Inc. Communications system with a configurable data transfer architecture
EP0935199B1 (de) * 1998-02-04 2011-05-04 Panasonic Corporation Speichersteuerungseinheit und -verfahren und Medium mit Ausführungsprogramm
US6173367B1 (en) * 1999-05-19 2001-01-09 Ati Technologies, Inc. Method and apparatus for accessing graphics cache memory
EP1067461B1 (de) * 1999-07-08 2013-04-24 Texas Instruments France Vereinheitlichtes Speicherverwaltungssystem für heterogene Multiprozessor-Architektur
US7509391B1 (en) 1999-11-23 2009-03-24 Texas Instruments Incorporated Unified memory management system for multi processor heterogeneous architecture
US6748480B2 (en) * 1999-12-27 2004-06-08 Gregory V. Chudnovsky Multi-bank, fault-tolerant, high-performance memory addressing system and method
US6381669B1 (en) * 1999-12-27 2002-04-30 Gregory V. Chudnovsky Multi-bank, fault-tolerant, high-performance memory addressing system and method
US6760743B1 (en) 2000-01-04 2004-07-06 International Business Machines Corporation Instruction memory system for multi-processor environment and disjoint tasks
US7788642B2 (en) * 2005-05-16 2010-08-31 Texas Instruments Incorporated Displaying cache information using mark-up techniques
JP4617282B2 (ja) * 2006-08-31 2011-01-19 富士通株式会社 負荷発生装置及び負荷試験方法
US7908530B2 (en) * 2009-03-16 2011-03-15 Faraday Technology Corp. Memory module and on-line build-in self-test method thereof for enhancing memory system reliability
US8614920B2 (en) * 2012-04-02 2013-12-24 Winbond Electronics Corporation Method and apparatus for logic read in flash memory
US9595350B2 (en) * 2012-11-05 2017-03-14 Nxp Usa, Inc. Hardware-based memory initialization
US20140258780A1 (en) * 2013-03-05 2014-09-11 Micron Technology, Inc. Memory controllers including test mode engines and methods for repair of memory over busses used during normal operation of the memory

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US4392200A (en) * 1980-01-28 1983-07-05 Digital Equipment Corporation Cached multiprocessor system with pipeline timing
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US5067071A (en) * 1985-02-27 1991-11-19 Encore Computer Corporation Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus
JPS6289149A (ja) * 1985-10-15 1987-04-23 Agency Of Ind Science & Technol 多ポ−トメモリシステム
US4876643A (en) * 1987-06-24 1989-10-24 Kabushiki Kaisha Toshiba Parallel searching system having a master processor for controlling plural slave processors for independently processing respective search requests

Also Published As

Publication number Publication date
EP0380855B1 (de) 1996-03-20
ATE135833T1 (de) 1996-04-15
DE68926036T2 (de) 1997-01-02
AU5394290A (en) 1991-12-19
US5043874A (en) 1991-08-27
AU628528B2 (en) 1992-09-17
EP0380855A3 (de) 1991-02-06
EP0380855A2 (de) 1990-08-08
JPH02208771A (ja) 1990-08-20
CA1323929C (en) 1993-11-02

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee