DE68929518D1 - Verfahren zur Verwendung einer elektronisch wiederkonfigurierbaren Gatterfeld-Logik und dadurch hergestelltes Gerät - Google Patents

Verfahren zur Verwendung einer elektronisch wiederkonfigurierbaren Gatterfeld-Logik und dadurch hergestelltes Gerät

Info

Publication number
DE68929518D1
DE68929518D1 DE68929518T DE68929518T DE68929518D1 DE 68929518 D1 DE68929518 D1 DE 68929518D1 DE 68929518 T DE68929518 T DE 68929518T DE 68929518 T DE68929518 T DE 68929518T DE 68929518 D1 DE68929518 D1 DE 68929518D1
Authority
DE
Germany
Prior art keywords
functional circuit
electrical signals
reprogrammable
logic
stimulus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68929518T
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English (en)
Other versions
DE68929518T2 (de
Inventor
Michael R Butts
Jon A Batcheller
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Quickturn Design Systems Inc
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Quickturn Design Systems Inc
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Publication date
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22964407&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE68929518(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Quickturn Design Systems Inc filed Critical Quickturn Design Systems Inc
Publication of DE68929518D1 publication Critical patent/DE68929518D1/de
Application granted granted Critical
Publication of DE68929518T2 publication Critical patent/DE68929518T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
DE68929518T 1988-10-05 1989-10-04 Verfahren zur Verwendung einer elektronisch wiederkonfigurierbaren Gatterfeld-Logik und dadurch hergestelltes Gerät Expired - Lifetime DE68929518T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US25446388A 1988-10-05 1988-10-05
US254463 1988-10-05

Publications (2)

Publication Number Publication Date
DE68929518D1 true DE68929518D1 (de) 2004-06-03
DE68929518T2 DE68929518T2 (de) 2005-06-09

Family

ID=22964407

Family Applications (2)

Application Number Title Priority Date Filing Date
DE68925121T Expired - Lifetime DE68925121T2 (de) 1988-10-05 1989-10-04 Verfahren zur verwendung einer elektronisch wiederkonfigurierbaren gatterfeld-logik und dadurch hergestelltes gerät
DE68929518T Expired - Lifetime DE68929518T2 (de) 1988-10-05 1989-10-04 Verfahren zur Verwendung einer elektronisch wiederkonfigurierbaren Gatterfeld-Logik und dadurch hergestelltes Gerät

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE68925121T Expired - Lifetime DE68925121T2 (de) 1988-10-05 1989-10-04 Verfahren zur verwendung einer elektronisch wiederkonfigurierbaren gatterfeld-logik und dadurch hergestelltes gerät

Country Status (7)

Country Link
US (1) US5036473A (de)
EP (3) EP1462964A3 (de)
JP (6) JP3060018B2 (de)
AT (2) ATE131643T1 (de)
AU (1) AU4347189A (de)
DE (2) DE68925121T2 (de)
WO (1) WO1990004233A1 (de)

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EP0651343A1 (de) 1995-05-03
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JP2000236249A (ja) 2000-08-29
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JP3162687B2 (ja) 2001-05-08
ATE131643T1 (de) 1995-12-15
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JP2000036737A (ja) 2000-02-02
EP0651343B1 (de) 2004-04-28
AU4347189A (en) 1990-05-01
JPH04502985A (ja) 1992-05-28
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EP0437491B1 (de) 1995-12-13
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US5036473A (en) 1991-07-30
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WO1990004233A1 (en) 1990-04-19
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