DE69021745T2 - Schaltung zur Prüfbarkeit. - Google Patents
Schaltung zur Prüfbarkeit.Info
- Publication number
- DE69021745T2 DE69021745T2 DE69021745T DE69021745T DE69021745T2 DE 69021745 T2 DE69021745 T2 DE 69021745T2 DE 69021745 T DE69021745 T DE 69021745T DE 69021745 T DE69021745 T DE 69021745T DE 69021745 T2 DE69021745 T2 DE 69021745T2
- Authority
- DE
- Germany
- Prior art keywords
- testability
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1026593A JPH0758319B2 (ja) | 1989-02-07 | 1989-02-07 | テスト容易化回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69021745D1 DE69021745D1 (de) | 1995-09-28 |
DE69021745T2 true DE69021745T2 (de) | 1996-02-22 |
Family
ID=12197834
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69021745T Expired - Fee Related DE69021745T2 (de) | 1989-02-07 | 1990-02-07 | Schaltung zur Prüfbarkeit. |
Country Status (5)
Country | Link |
---|---|
US (1) | US5161160A (de) |
EP (1) | EP0382184B1 (de) |
JP (1) | JPH0758319B2 (de) |
KR (1) | KR930006094B1 (de) |
DE (1) | DE69021745T2 (de) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0455778A (ja) * | 1990-06-26 | 1992-02-24 | Toshiba Corp | 半導体装置のテスト方法 |
US5271019A (en) * | 1991-03-15 | 1993-12-14 | Amdahl Corporation | Scannable system with addressable scan reset groups |
JPH06506333A (ja) | 1991-03-18 | 1994-07-14 | クウォリティ・セミコンダクタ・インコーポレイテッド | 高速トランスミッションゲートスイッチ |
US6208195B1 (en) | 1991-03-18 | 2001-03-27 | Integrated Device Technology, Inc. | Fast transmission gate switch |
JP2822724B2 (ja) * | 1991-09-20 | 1998-11-11 | 日本電気株式会社 | 論理集積回路 |
US5390191A (en) * | 1992-01-31 | 1995-02-14 | Sony Corporation | Apparatus and method for testing the interconnection between integrated circuits |
US5270642A (en) * | 1992-05-15 | 1993-12-14 | Hewlett-Packard Company | Partitioned boundary-scan testing for the reduction of testing-induced damage |
JP3247937B2 (ja) * | 1992-09-24 | 2002-01-21 | 株式会社日立製作所 | 論理集積回路 |
US5951703A (en) * | 1993-06-28 | 1999-09-14 | Tandem Computers Incorporated | System and method for performing improved pseudo-random testing of systems having multi driver buses |
JP3533451B2 (ja) * | 1993-09-16 | 2004-05-31 | クウォリティ・セミコンダクタ・インコーポレイテッド | 高速伝送ゲートスイッチを用いたスキャンテスト回路 |
DE4340899A1 (de) * | 1993-12-01 | 1995-06-08 | Philips Patentverwaltung | Meßvorrichtung zum Testen der Verbindungen zwischen wenigstens zwei Baugruppen |
US5636227A (en) * | 1994-07-08 | 1997-06-03 | Advanced Risc Machines Limited | Integrated circuit test mechansim and method |
US5875197A (en) * | 1995-05-15 | 1999-02-23 | Motorola Inc. | Addressable serial test system |
US5828985A (en) * | 1996-11-20 | 1998-10-27 | Advantest Corp. | Semiconductor test system |
US5936976A (en) * | 1997-07-25 | 1999-08-10 | Vlsi Technology, Inc. | Selecting a test data input bus to supply test data to logical blocks within an integrated circuit |
US6115836A (en) * | 1997-09-17 | 2000-09-05 | Cypress Semiconductor Corporation | Scan path circuitry for programming a variable clock pulse width |
US6041427A (en) * | 1997-10-27 | 2000-03-21 | Vlsi Technology | Scan testable circuit arrangement |
US6405335B1 (en) | 1998-02-25 | 2002-06-11 | Texas Instruments Incorporated | Position independent testing of circuits |
US6728915B2 (en) | 2000-01-10 | 2004-04-27 | Texas Instruments Incorporated | IC with shared scan cells selectively connected in scan path |
US6769080B2 (en) | 2000-03-09 | 2004-07-27 | Texas Instruments Incorporated | Scan circuit low power adapter with counter |
JP3606520B2 (ja) * | 2001-12-05 | 2005-01-05 | 沖電気工業株式会社 | システムlsiのテストパターン作成方法,システムlsiのテストパターン作成装置,及びシステムlsiのテスト方法 |
US20040076166A1 (en) * | 2002-10-21 | 2004-04-22 | Patenaude Jean-Marc Guy | Multi-service packet network interface |
US7733900B2 (en) * | 2002-10-21 | 2010-06-08 | Broadcom Corporation | Multi-service ethernet-over-sonet silicon platform |
US7163458B2 (en) * | 2003-10-21 | 2007-01-16 | David Schugar | Casino game for betting on bidirectional linear progression |
US7294054B2 (en) * | 2003-04-10 | 2007-11-13 | David Schugar | Wagering method, device, and computer readable storage medium, for wagering on pieces in a progression |
KR100768549B1 (ko) * | 2006-07-27 | 2007-10-18 | 연세대학교 산학협력단 | 분할된 lfsr을 이용한 저전력 결정패턴 bist 방법및 장치 |
KR101116956B1 (ko) * | 2009-08-31 | 2012-03-14 | 한양대학교 산학협력단 | Tam 기반 테스트가 가능한 시스템 온 칩 및 이의 테스트 방법 |
US8694843B2 (en) * | 2011-08-04 | 2014-04-08 | Texas Instruments Incorporated | Clock control of pipelined memory for improved delay fault testing |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0668732B2 (ja) * | 1984-11-21 | 1994-08-31 | 株式会社日立製作所 | 情報処理装置のスキヤン方式 |
US4698588A (en) * | 1985-10-23 | 1987-10-06 | Texas Instruments Incorporated | Transparent shift register latch for isolating peripheral ports during scan testing of a logic circuit |
US4710931A (en) * | 1985-10-23 | 1987-12-01 | Texas Instruments Incorporated | Partitioned scan-testing system |
JPS62228178A (ja) * | 1986-03-29 | 1987-10-07 | Toshiba Corp | 論理回路の試験方式 |
JPS63148179A (ja) * | 1986-12-10 | 1988-06-21 | Nec Corp | スキヤン・パス回路 |
US4766593A (en) * | 1986-12-22 | 1988-08-23 | Motorola, Inc. | Monolithically integrated testable registers that cannot be directly addressed |
JPS63182585A (ja) * | 1987-01-26 | 1988-07-27 | Toshiba Corp | テスト容易化機能を備えた論理回路 |
EP0292116A3 (de) * | 1987-05-05 | 1990-08-01 | Control Data Corporation | Prüfsystem für VLSI-Schaltungen |
JPS643744A (en) * | 1987-06-26 | 1989-01-09 | Hitachi Ltd | Lsi test method |
JP2725258B2 (ja) * | 1987-09-25 | 1998-03-11 | 三菱電機株式会社 | 集積回路装置 |
JPH0820967B2 (ja) * | 1987-09-25 | 1996-03-04 | 三菱電機株式会社 | 集積回路 |
-
1989
- 1989-02-07 JP JP1026593A patent/JPH0758319B2/ja not_active Expired - Fee Related
-
1990
- 1990-02-01 US US07/472,382 patent/US5161160A/en not_active Expired - Lifetime
- 1990-02-07 EP EP90102402A patent/EP0382184B1/de not_active Expired - Lifetime
- 1990-02-07 DE DE69021745T patent/DE69021745T2/de not_active Expired - Fee Related
- 1990-02-07 KR KR1019900001520A patent/KR930006094B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JPH0758319B2 (ja) | 1995-06-21 |
DE69021745D1 (de) | 1995-09-28 |
EP0382184A3 (de) | 1991-08-21 |
JPH02206772A (ja) | 1990-08-16 |
KR930006094B1 (ko) | 1993-07-07 |
KR900013315A (ko) | 1990-09-05 |
US5161160A (en) | 1992-11-03 |
EP0382184A2 (de) | 1990-08-16 |
EP0382184B1 (de) | 1995-08-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |